From: Christophe Lyon <christophe.lyon@linaro.org>
To: gcc-patches@gcc.gnu.org
Subject: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
Date: Tue, 13 Jan 2015 15:19:00 -0000 [thread overview]
Message-ID: <1421162314-25779-14-git-send-email-christophe.lyon@linaro.org> (raw)
In-Reply-To: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
new file mode 100644
index 0000000..34cdbe8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
@@ -0,0 +1,78 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_N(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, float, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 4)
+
+ /* vector_res = vmlx_n(vector, vector2, val),
+ then store the result. */
+#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V) \
+ TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)
+
+ DECL_VMLX_N(vector);
+ DECL_VMLX_N(vector2);
+ DECL_VMLX_N(vector_res);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+ VDUP(vector2, , float, f, 32, 2, 55.2f);
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+ VDUP(vector2, q, float, f, 32, 4, 55.9f);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11);
+ TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44);
+ TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88);
+ TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
new file mode 100644
index 0000000..8376fe1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c,
+ 0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776,
+ 0x2777, 0x2778, 0x2779, 0x277a };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b,
+ 0x4568287b, 0x4568387b };
+
+#include "vmlX_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
new file mode 100644
index 0000000..b7619f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba,
+ 0xe3bb, 0xe3bc, 0xe3bd, 0xe3be };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13,
+ 0xffffde14, 0xffffde15 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870,
+ 0xd871, 0xd872, 0xd873, 0xd874 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9,
+ 0xffffd2ca, 0xffffd2cb };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b,
+ 0xc569e87b, 0xc569d87b };
+
+#include "vmlX_n.inc"
--
2.1.0
next prev parent reply other threads:[~2015-01-13 15:19 UTC|newest]
Thread overview: 144+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
2015-01-16 14:08 ` Tejas Belagod
2015-01-16 16:23 ` Christophe Lyon
2015-01-16 17:20 ` Marcus Shawcroft
2015-01-16 17:59 ` Christophe Lyon
2015-01-19 13:34 ` Marcus Shawcroft
2015-01-19 15:49 ` Christophe Lyon
2015-01-19 17:33 ` Marcus Shawcroft
2015-01-21 16:35 ` Christophe Lyon
2015-01-22 12:37 ` Tejas Belagod
2015-01-22 14:42 ` Christophe Lyon
2015-01-22 15:58 ` Tejas Belagod
2015-01-22 23:10 ` Christophe Lyon
2015-01-23 11:02 ` Tejas Belagod
2015-01-23 12:08 ` Christophe Lyon
2015-01-23 15:21 ` Christophe Lyon
2015-01-25 22:51 ` Christophe Lyon
2015-01-26 13:23 ` Tejas Belagod
2015-01-26 13:57 ` Christophe Lyon
2015-02-02 10:39 ` Christophe Lyon
2015-02-02 15:38 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
2015-01-16 16:21 ` Tejas Belagod
2015-01-16 16:35 ` Christophe Lyon
2015-01-20 15:30 ` Christophe Lyon
2015-01-26 14:03 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
2015-01-16 14:31 ` Tejas Belagod
2015-01-16 16:31 ` Christophe Lyon
2015-01-16 17:22 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
2015-01-21 0:02 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
2015-01-16 18:39 ` Tejas Belagod
2015-01-20 15:36 ` Christophe Lyon
2015-01-26 14:30 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
2015-01-19 16:46 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
2015-01-16 16:32 ` Christophe Lyon
2015-01-19 13:42 ` Marcus Shawcroft
2015-01-20 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
2015-01-19 16:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
2015-01-16 16:06 ` Tejas Belagod
2015-01-16 18:12 ` Christophe Lyon
2015-01-19 13:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
2015-01-16 18:48 ` Tejas Belagod
2015-01-16 19:05 ` Christophe Lyon
2015-01-16 20:34 ` Christophe Lyon
2015-01-20 15:50 ` Christophe Lyon
2015-01-26 14:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
2015-01-16 18:41 ` Tejas Belagod
2015-01-20 15:39 ` Christophe Lyon
2015-01-26 14:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
2015-01-16 18:24 ` Tejas Belagod
2015-01-19 15:23 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
2015-01-19 16:48 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` Christophe Lyon [this message]
2015-01-16 16:30 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Tejas Belagod
2015-01-20 15:33 ` Christophe Lyon
2015-01-26 14:08 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
2015-01-16 15:35 ` Tejas Belagod
2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
2015-01-22 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
2015-01-16 18:18 ` Tejas Belagod
2015-01-20 15:35 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
2015-01-19 16:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
2015-01-16 18:11 ` Tejas Belagod
2015-01-19 14:15 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
2015-01-16 17:54 ` Tejas Belagod
2015-01-16 18:02 ` Christophe Lyon
2015-01-20 15:34 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
2015-01-19 16:54 ` Marcus Shawcroft
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
2015-01-16 19:20 ` Christophe Lyon
2015-01-19 17:16 ` Marcus Shawcroft
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
2015-01-20 15:26 ` Christophe Lyon
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