From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 116993 invoked by alias); 11 May 2015 17:50:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 116918 invoked by uid 89); 11 May 2015 17:50:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 May 2015 17:50:08 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 67F7AD44B173C; Mon, 11 May 2015 18:50:02 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 11 May 2015 18:50:05 +0100 Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.224.2; Mon, 11 May 2015 18:50:05 +0100 Received: from [10.20.3.58] (10.20.3.58) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server (TLS) id 14.3.174.1; Mon, 11 May 2015 10:50:03 -0700 Message-ID: <1431366602.14613.210.camel@ubuntu-sellcey> Subject: RE: [RFC]: Remove Mem/address type assumption in combiner From: Steve Ellcey Reply-To: To: "Kumar, Venkataramanan" CC: Segher Boessenkool , "Jeff Law (law@redhat.com)" , "gcc-patches@gcc.gnu.org" , "maxim.kuvyrkov@linaro.org" , Matthew Fortune , clm Date: Mon, 11 May 2015 17:50:00 -0000 In-Reply-To: <7794A52CE4D579448B959EED7DD0A4723DCF68C1@satlexdag06.amd.com> References: <7794A52CE4D579448B959EED7DD0A4723DCF68C1@satlexdag06.amd.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-SW-Source: 2015-05/txt/msg00978.txt.bz2 On Thu, 2015-05-07 at 11:01 +0000, Kumar, Venkataramanan wrote: > Hi Segher, > > Thank you I committed as r222874. > Ref: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=222874 > > Regards, > Venkat. Venkat, This patch broke a number of MIPS tests, specifically mips32r6 tests that look for the lsa instruction (load scaled address) which shifts one register and then adds it to a second register. I am not sure if this needs to be addressed in combine.c or if we need to add a peephole optimization to mips.md to handle the new instruction sequence. What do you think? Is the change here what you would expect to see from your patch? With this C code: signed short test (signed short *a, int index) { return a[index]; } GCC/combine for mips32r6 used to produce: (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (mult:SI (reg:SI 5 $5 [ index ]) (const_int 2 [0x2])) (reg:SI 4 $4 [ a ]))) lsa.c:3 444 {lsa} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (nil)))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) And would generate: lsa $4,$5,$4,1 lh $2,0($4) But now it produces: (insn 7 4 8 2 (set (reg:SI 202) (ashift:SI (reg:SI 5 $5 [ index ]) (const_int 1 [0x1]))) lsa.c:3 432 {*ashlsi3} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (nil))) (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (reg:SI 4 $4 [ a ]) (reg:SI 202))) lsa.c:3 13 {*addsi3} (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (expr_list:REG_DEAD (reg:SI 202) (nil))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) Which generates: sll $5,$5,1 addu $4,$4,$5 lh $2,0($4) Steve Ellcey sellcey@imgtec.com