From: Christophe Lyon <christophe.lyon@linaro.org>
To: gcc-patches@gcc.gnu.org
Subject: [Patch ARM-AArch64/testsuite Neon intrinsics 12/13] Add vqshrn_n tests.
Date: Tue, 12 May 2015 20:31:00 -0000 [thread overview]
Message-ID: <1431462661-27247-13-git-send-email-christophe.lyon@linaro.org> (raw)
In-Reply-To: <1431462661-27247-1-git-send-email-christophe.lyon@linaro.org>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c
new file mode 100644
index 0000000..b3556f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c
@@ -0,0 +1,177 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+int VECT_VAR(expected_cumulative_sat,uint,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat,uint,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat,uint,64,2) = 1;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
+ 0xfa, 0xfa, 0xfb, 0xfb };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff8, 0xfff9, 0xfff9 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+
+/* Expected values of cumulative_saturation flag with max input value
+ shifted by 3. */
+int VECT_VAR(expected_cumulative_sat_max_sh3,int,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat_max_sh3,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat_max_sh3,int,64,2) = 1;
+int VECT_VAR(expected_cumulative_sat_max_sh3,uint,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat_max_sh3,uint,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat_max_sh3,uint,64,2) = 1;
+
+/* Expected results with max input value shifted by 3. */
+VECT_VAR_DECL(expected_max_sh3,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x7f, 0x7f, 0x7f, 0x7f };
+VECT_VAR_DECL(expected_max_sh3,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected_max_sh3,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected_max_sh3,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_max_sh3,uint,16,4) [] = { 0xffff, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_max_sh3,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+
+/* Expected values of cumulative_saturation flag with max input value
+ shifted by type size. */
+int VECT_VAR(expected_cumulative_sat_max_shmax,int,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat_max_shmax,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat_max_shmax,int,64,2) = 0;
+int VECT_VAR(expected_cumulative_sat_max_shmax,uint,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat_max_shmax,uint,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat_max_shmax,uint,64,2) = 0;
+
+/* Expected results with max input value shifted by type size. */
+VECT_VAR_DECL(expected_max_shmax,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x7f, 0x7f, 0x7f, 0x7f };
+VECT_VAR_DECL(expected_max_shmax,int,16,4) [] = { 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected_max_shmax,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected_max_shmax,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_max_shmax,uint,16,4) [] = { 0xffff, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_max_shmax,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+
+#define INSN vqshrn_n
+#define TEST_MSG "VQSHRN_N"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN)
+{
+ /* Basic test: y=vqshrn_n(x,v), then store the result. */
+#define TEST_VQSHRN_N2(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), \
+ VECT_VAR(vector_res, T1, W2, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN */
+#define TEST_VQSHRN_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQSHRN_N2(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQSHRN_N(T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQSHRN_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT)
+
+
+ /* vector is twice as large as vector_res. */
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Choose shift amount arbitrarily. */
+#define CMT ""
+ TEST_VQSHRN_N(int, s, 16, 8, 8, 1, expected_cumulative_sat, CMT);
+ TEST_VQSHRN_N(int, s, 32, 16, 4, 1, expected_cumulative_sat, CMT);
+ TEST_VQSHRN_N(int, s, 64, 32, 2, 2, expected_cumulative_sat, CMT);
+ TEST_VQSHRN_N(uint, u, 16, 8, 8, 2, expected_cumulative_sat, CMT);
+ TEST_VQSHRN_N(uint, u, 32, 16, 4, 3, expected_cumulative_sat, CMT);
+ TEST_VQSHRN_N(uint, u, 64, 32, 2, 3, expected_cumulative_sat, CMT);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+
+
+ /* Use max possible value as input. */
+ VDUP(vector, q, int, s, 16, 8, 0x7FFF);
+ VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF);
+ VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
+ VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
+ VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
+
+#undef CMT
+#define CMT " (check saturation: shift by 3)"
+ TEST_VQSHRN_N(int, s, 16, 8, 8, 3, expected_cumulative_sat_max_sh3, CMT);
+ TEST_VQSHRN_N(int, s, 32, 16, 4, 3, expected_cumulative_sat_max_sh3, CMT);
+ TEST_VQSHRN_N(int, s, 64, 32, 2, 3, expected_cumulative_sat_max_sh3, CMT);
+ TEST_VQSHRN_N(uint, u, 16, 8, 8, 3, expected_cumulative_sat_max_sh3, CMT);
+ TEST_VQSHRN_N(uint, u, 32, 16, 4, 3, expected_cumulative_sat_max_sh3, CMT);
+ TEST_VQSHRN_N(uint, u, 64, 32, 2, 3, expected_cumulative_sat_max_sh3, CMT);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh3, CMT);
+
+
+#undef CMT
+#define CMT " (check saturation: shift by max)"
+ TEST_VQSHRN_N(int, s, 16, 8, 8, 8, expected_cumulative_sat_max_shmax, CMT);
+ TEST_VQSHRN_N(int, s, 32, 16, 4, 16, expected_cumulative_sat_max_shmax, CMT);
+ TEST_VQSHRN_N(int, s, 64, 32, 2, 32, expected_cumulative_sat_max_shmax, CMT);
+ TEST_VQSHRN_N(uint, u, 16, 8, 8, 8, expected_cumulative_sat_max_shmax, CMT);
+ TEST_VQSHRN_N(uint, u, 32, 16, 4, 16, expected_cumulative_sat_max_shmax, CMT);
+ TEST_VQSHRN_N(uint, u, 64, 32, 2, 32, expected_cumulative_sat_max_shmax, CMT);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shmax, CMT);
+}
+
+int main (void)
+{
+ exec_vqshrn_n ();
+ return 0;
+}
--
2.1.4
next prev parent reply other threads:[~2015-05-12 20:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 20:31 [Patch ARM-AArch64/testsuite 00/13] Neon intrinsics executable tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 11/13] Add vqshlu_n tests Christophe Lyon
2015-05-12 20:31 ` Christophe Lyon [this message]
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 06/13] Add vqrshl tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 02/13] Add vqmovun tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 07/13] Add vqrshrn_n tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 10/13] Add vqshl_n tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 04/13] Add vqrdmulh_lane tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 01/13] Add vqmovn tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 03/13] Add vqrdmulh tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/13] Add vqrshrun_n tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 05/13] Add vqrdmulh_n tests Christophe Lyon
2015-05-12 20:31 ` [Patch ARM-AArch64/testsuite Neon intrinsics 13/13] Add vqshrun_n tests Christophe Lyon
2015-05-12 20:36 ` [Patch ARM-AArch64/testsuite Neon intrinsics 09/13] Add vqshl tests Christophe Lyon
2015-05-19 14:02 ` [Patch ARM-AArch64/testsuite 00/13] Neon intrinsics executable tests James Greenhalgh
2015-05-19 16:01 ` Christophe Lyon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1431462661-27247-13-git-send-email-christophe.lyon@linaro.org \
--to=christophe.lyon@linaro.org \
--cc=gcc-patches@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).