From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 35564 invoked by alias); 27 May 2015 20:15:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 35549 invoked by uid 89); 27 May 2015 20:15:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f179.google.com Received: from mail-wi0-f179.google.com (HELO mail-wi0-f179.google.com) (209.85.212.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 27 May 2015 20:15:56 +0000 Received: by wifw1 with SMTP id w1so36474996wif.0 for ; Wed, 27 May 2015 13:15:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id; bh=Xe/q23pSX2w1LCTByUZlmXP2MzjsnYdhLe9a4xCqJ8M=; b=Y0dsljAiqRn2O2PAgnlpoyLZ9t4e2QNzHAOvF7JQAiov0DTj3aC6khMXUXLkD9Rbqu BMPMC+LBuEjufQxAPdrHEmkiXSBpurfaFlCnLJ1GkJGrrEZ5FHDoqtWl89OhWPcb94+X tqsTvDqG7ZqIawVlJqKxno72LyAk92hUESq0txE3iBYRZZJ5GB92+7Qwnt0FRZ+TgC/f VkpZWe13cKGZAMUeoxJD7jTf8PvkRikJK0wJhkIOGSamdlApc5MQZYWqQSLXYKuah3F4 eq19Nmji6DkCZ6Nwckpv1uvkLmvYasDpISDbpZBEeM+EXDT4BUFaEr0FyDdTVMH+fube Hprg== X-Gm-Message-State: ALoCoQlKebBoNE/Y7KE9ynbZc/9xzK9daiVw5wdSnVqYh1deDYxNTZpCBez7aurjvSTGfcQRaJsC X-Received: by 10.194.187.15 with SMTP id fo15mr63343127wjc.100.1432757753237; Wed, 27 May 2015 13:15:53 -0700 (PDT) Received: from babel.clyon.hd.free.fr (vig38-2-82-225-222-175.fbx.proxad.net. [82.225.222.175]) by mx.google.com with ESMTPSA id u7sm76992wif.3.2015.05.27.13.15.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 May 2015 13:15:52 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Date: Wed, 27 May 2015 20:16:00 -0000 Message-Id: <1432757747-4891-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg02544.txt.bz2 This patch series is a follow-up to the tests I already contributed, converted from my original testsuite. This series consists in 20 new patches, which can be committed independently. For vrecpe, I added the setting of the "Flush-to-Zero" FP flag, to force AArch64 to behave the same as ARM by default. This is the final batch, except for the vget_lane tests which I will submit later. This should cover the subset of AdvSIMD intrinsics common to ARMv7 and AArch64. Tested with qemu on arm*linux, aarch64-linux. 2015-05-27 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (_ARM_FPSCR): Add FZ field. (clean_results): Force FZ=1 on AArch64. * gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise. Christophe Lyon (20): Add vrecpe tests. Add vrecps tests. Add vreinterpret tests. Add vrev tests. Add vrshl tests. Add vshr_n tests. Add vrshr_n tests. Add vrshrn_n tests. Add vrsqrte tests. Add vrsqrts tests. Add vrsra_n tests. Add vset_lane tests. Add vshll_n tests. Add vshl_n tests. Add vshrn_n tests. Add vsra_n tests. Add vst1_lane tests. Add vstX_lane tests. Add vtbX tests. Add vtst tests. .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 19 +- .../gcc.target/aarch64/advsimd-intrinsics/vrecpe.c | 154 +++++ .../gcc.target/aarch64/advsimd-intrinsics/vrecps.c | 117 ++++ .../aarch64/advsimd-intrinsics/vreinterpret.c | 741 +++++++++++++++++++++ .../gcc.target/aarch64/advsimd-intrinsics/vrev.c | 200 ++++++ .../gcc.target/aarch64/advsimd-intrinsics/vrshl.c | 627 +++++++++++++++++ .../aarch64/advsimd-intrinsics/vrshr_n.c | 504 ++++++++++++++ .../aarch64/advsimd-intrinsics/vrshrn_n.c | 143 ++++ .../aarch64/advsimd-intrinsics/vrsqrte.c | 157 +++++ .../aarch64/advsimd-intrinsics/vrsqrts.c | 118 ++++ .../aarch64/advsimd-intrinsics/vrsra_n.c | 553 +++++++++++++++ .../aarch64/advsimd-intrinsics/vset_lane.c | 99 +++ .../gcc.target/aarch64/advsimd-intrinsics/vshl_n.c | 96 +++ .../aarch64/advsimd-intrinsics/vshll_n.c | 56 ++ .../gcc.target/aarch64/advsimd-intrinsics/vshr_n.c | 95 +++ .../aarch64/advsimd-intrinsics/vshrn_n.c | 70 ++ .../gcc.target/aarch64/advsimd-intrinsics/vsra_n.c | 117 ++++ .../aarch64/advsimd-intrinsics/vst1_lane.c | 93 +++ .../aarch64/advsimd-intrinsics/vstX_lane.c | 578 ++++++++++++++++ .../gcc.target/aarch64/advsimd-intrinsics/vtbX.c | 289 ++++++++ .../gcc.target/aarch64/advsimd-intrinsics/vtst.c | 120 ++++ 21 files changed, 4940 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c -- 2.1.4