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From: Christophe Lyon <christophe.lyon@linaro.org>
To: gcc-patches@gcc.gnu.org
Subject: [Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests.
Date: Wed, 27 May 2015 20:30:00 -0000	[thread overview]
Message-ID: <1432757747-4891-21-git-send-email-christophe.lyon@linaro.org> (raw)
In-Reply-To: <1432757747-4891-1-git-send-email-christophe.lyon@linaro.org>


diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
new file mode 100644
index 0000000..7f96540
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -0,0 +1,120 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results with signed input.  */
+VECT_VAR_DECL(expected_signed,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+					       0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_signed,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_signed,uint,32,2) [] = { 0x0, 0xffffffff };
+VECT_VAR_DECL(expected_signed,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_signed,uint,16,8) [] = { 0x0, 0xffff, 0x0, 0xffff,
+						0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_signed,uint,32,4) [] = { 0x0, 0xffffffff,
+						0x0, 0xffffffff };
+
+/* Expected results with unsigned input.  */
+VECT_VAR_DECL(expected_unsigned,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+						 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_unsigned,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_unsigned,uint,32,2) [] = { 0x0, 0xffffffff };
+VECT_VAR_DECL(expected_unsigned,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+						  0xff, 0xff, 0xff, 0xff,
+						  0xff, 0xff, 0xff, 0xff,
+						  0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
+						  0x0, 0xffff,
+						  0xffff, 0xffff,
+						  0xffff, 0xffff };
+VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
+						  0x0, 0xffffffff };
+
+#ifndef INSN_NAME
+#define INSN_NAME vtst
+#define TEST_MSG "VTST/VTSTQ"
+#endif
+
+/* We can't use the standard ref_v_binary_op.c template because vtst
+   has no 64 bits variant, and outputs are always of uint type.  */
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+  /* Basic test: y=OP(x,x), then store the result.  */
+#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)		\
+  VECT_VAR(vector_res, uint, W, N) =			\
+    INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
+		      VECT_VAR(vector2, T1, W, N));	\
+  vst1##Q##_u##W(VECT_VAR(result, uint, W, N),		\
+		 VECT_VAR(vector_res, uint, W, N))
+
+#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N)	\
+  TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)	\
+
+  DECL_VARIABLE_ALL_VARIANTS(vector);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+  DECL_VARIABLE_UNSIGNED_VARIANTS(vector_res);
+
+
+  clean_results ();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+  /* Choose init value arbitrarily, will be used as comparison
+     value.  */
+  VDUP(vector2, , int, s, 8, 8, 15);
+  VDUP(vector2, , int, s, 16, 4, 5);
+  VDUP(vector2, , int, s, 32, 2, 1);
+  VDUP(vector2, , uint, u, 8, 8, 15);
+  VDUP(vector2, , uint, u, 16, 4, 5);
+  VDUP(vector2, , uint, u, 32, 2, 1);
+  VDUP(vector2, q, int, s, 8, 16, 15);
+  VDUP(vector2, q, int, s, 16, 8, 5);
+  VDUP(vector2, q, int, s, 32, 4, 1);
+  VDUP(vector2, q, uint, u, 8, 16, 15);
+  VDUP(vector2, q, uint, u, 16, 8, 5);
+  VDUP(vector2, q, uint, u, 32, 4, 1);
+
+#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
+  MACRO(VAR, , T1, T2, 8, 8);					\
+  MACRO(VAR, , T1, T2, 16, 4);					\
+  MACRO(VAR, , T1, T2, 32, 2);					\
+  MACRO(VAR, q, T1, T2, 8, 16);					\
+  MACRO(VAR, q, T1, T2, 16, 8);					\
+  MACRO(VAR, q, T1, T2, 32, 4)
+
+  /* Split the test, as both signed and unsigned variants output their
+     result in an unsigned form (thus the same output variable is used
+     in these tests).  */
+  TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME, int, s);
+
+#define CMT " (signed input)"
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_signed, CMT);
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_signed, CMT);
+  CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_signed, CMT);
+  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_signed, CMT);
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_signed, CMT);
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_signed, CMT);
+
+  TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME, uint, u);
+
+#undef CMT
+#define CMT " (unsigned input)"
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_unsigned, CMT);
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_unsigned, CMT);
+  CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_unsigned, CMT);
+  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
+}
+
+int main (void)
+{
+  exec_vtst ();
+  return 0;
+}
-- 
2.1.4

  parent reply	other threads:[~2015-05-27 20:17 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-05-27 20:16 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests Christophe Lyon
2015-05-27 20:26 ` [Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests Christophe Lyon
2015-05-27 20:30 ` Christophe Lyon [this message]
2015-05-27 20:40 ` [Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests Christophe Lyon
2015-05-27 20:51 ` [Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests Christophe Lyon
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-06-16 10:10   ` James Greenhalgh
2015-06-16 13:26     ` Christophe Lyon
2015-11-02 14:20   ` Jiong Wang
2015-11-02 14:38     ` Christophe Lyon
2015-11-02 14:47       ` Jiong Wang

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