[PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

[PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

[Daniel Cederman]

__builtin_apply* and __builtin_return accesses the floating point registers on
SPARC even when compiling with -msoft-float.

gcc/ChangeLog:

2015-06-26  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.c (sparc_function_value_regno_p): Floating
	  point registers cannot be used when compiling for a target
	  without FPU.
	* config/sparc/sparc.md: A function cannot return a value in a
	  floating point register when compiled without floating point
	  support.
---
 gcc/config/sparc/sparc.c  |  2 +-
 gcc/config/sparc/sparc.md | 26 ++++++++++++++++----------
 2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 2556eec..e0d40a5 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -7403,7 +7403,7 @@ sparc_libcall_value (machine_mode mode,
 static bool
 sparc_function_value_regno_p (const unsigned int regno)
 {
-  return (regno == 8 || regno == 32);
+  return (regno == 8 || (TARGET_FPU && regno == 32));
 }
 
 /* Do what is necessary for `va_start'.  We look at the current function
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index a561877..c296913 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -6398,7 +6398,6 @@
   ""
 {
   rtx valreg1 = gen_rtx_REG (DImode, 8);
-  rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
   rtx result = operands[1];
 
   /* Pass constm1 to indicate that it may expect a structure value, but
@@ -6407,8 +6406,12 @@
 
   /* Save the function value registers.  */
   emit_move_insn (adjust_address (result, DImode, 0), valreg1);
-  emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
-				  valreg2);
+  if (TARGET_FPU)
+    {
+      rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
+      emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
+                      valreg2);
+    }
 
   /* The optimizer does not know that the call sets the function value
      registers we stored in the result block.  We avoid problems by
@@ -6620,7 +6623,6 @@
   ""
 {
   rtx valreg1 = gen_rtx_REG (DImode, 24);
-  rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
   rtx result = operands[0];
 
   if (! TARGET_ARCH64)
@@ -6637,14 +6639,18 @@
       emit_insn (gen_update_return (rtnreg, value));
     }
 
-  /* Reload the function value registers.  */
+  /* Reload the function value registers.
+     Put USE insns before the return.  */
   emit_move_insn (valreg1, adjust_address (result, DImode, 0));
-  emit_move_insn (valreg2,
-		  adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
-
-  /* Put USE insns before the return.  */
   emit_use (valreg1);
-  emit_use (valreg2);
+
+  if ( TARGET_FPU )
+    {
+      rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
+      emit_move_insn (valreg2,
+                      adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
+      emit_use (valreg2);
+    }
 
   /* Construct the return.  */
   expand_naked_return ();
-- 
2.4.3

[PATCH] Update instruction cost for LEON

[Daniel Cederman]

gcc/ChangeLog:

2015-07-03  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.c (struct processor_costs): Set div cost
	for leon to match UT699 and AT697F. Set mul cost for leon3 to
	match standard leon3.
---
 gcc/config/sparc/sparc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index e0d40a5..54341c5 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -251,8 +251,8 @@ struct processor_costs leon_costs = {
   COSTS_N_INSNS (5), /* imul */
   COSTS_N_INSNS (5), /* imulX */
   0, /* imul bit factor */
-  COSTS_N_INSNS (5), /* idiv */
-  COSTS_N_INSNS (5), /* idivX */
+  COSTS_N_INSNS (35), /* idiv */
+  COSTS_N_INSNS (35), /* idivX */
   COSTS_N_INSNS (1), /* movcc/movr */
   0, /* shift penalty */
 };
@@ -272,8 +272,8 @@ struct processor_costs leon3_costs = {
   COSTS_N_INSNS (15), /* fdivd */
   COSTS_N_INSNS (22), /* fsqrts */
   COSTS_N_INSNS (23), /* fsqrtd */
-  COSTS_N_INSNS (5), /* imul */
-  COSTS_N_INSNS (5), /* imulX */
+  COSTS_N_INSNS (1), /* imul */
+  COSTS_N_INSNS (1), /* imulX */
   0, /* imul bit factor */
   COSTS_N_INSNS (35), /* idiv */
   COSTS_N_INSNS (35), /* idivX */
-- 
2.4.3

[PATCH] save takes a single integer (register or 13-bit signed immediate)

[Daniel Cederman]

This removes a warning about operand 0 missing mode

gcc/ChangeLog:

2015-06-26  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.md: Window save takes a single integer
---
 gcc/config/sparc/sparc.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index c296913..66f7306 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -6490,7 +6490,7 @@
 
 (define_insn "window_save"
   [(unspec_volatile
-	[(match_operand 0 "arith_operand" "rI")]
+	[(match_operand:SI 0 "arith_operand" "rI")]
 	UNSPECV_SAVEW)]
   "!TARGET_FLAT"
   "save\t%%sp, %0, %%sp"
-- 
2.4.3

Re: [PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

[Eric Botcazou]

> __builtin_apply* and __builtin_return accesses the floating point registers
> on SPARC even when compiling with -msoft-float.

Ouch.  The fix is OK for all active branches but...

> 2015-06-26  Daniel Cederman  <cederman@gaisler.com>
> 
> 	* config/sparc/sparc.c (sparc_function_value_regno_p): Floating
> 	  point registers cannot be used when compiling for a target
> 	  without FPU.
> 	* config/sparc/sparc.md: A function cannot return a value in a
> 	  floating point register when compiled without floating point
> 	  support.

ChangeLog must just describe the what, nothing more.  If the rationale is not 
obvious, then a comment must be added _in the code_ itself.

	* config/sparc/sparc.c (sparc_function_value_regno_p): Do not return
	true on %f0 for a target without FPU.
	* config/sparc/sparc.md (untyped_call): Do not save %f0 for a target
	without FPU.
	(untyped_return): Do not load %f0 for a target without FPU.

> +
> +  if ( TARGET_FPU )
> +    {
> +      rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
> +      emit_move_insn (valreg2,
> +                      adjust_address (result, TARGET_ARCH64 ? TFmode :
> DFmode, 8)); +      emit_use (valreg2);
> +    }

Superfluous spaces around TARGET_FPU here.

-- 
Eric Botcazou

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

[Eric Botcazou]

> 2015-06-26  Daniel Cederman  <cederman@gaisler.com>
> 
> 	* config/sparc/sparc.md: Window save takes a single integer

This will probably break in 64-bit mode, the operand can be a DImode register.

-- 
Eric Botcazou

Re: [PATCH] Update instruction cost for LEON

[Eric Botcazou]

> 2015-07-03  Daniel Cederman  <cederman@gaisler.com>
> 
> 	* config/sparc/sparc.c (struct processor_costs): Set div cost
> 	for leon to match UT699 and AT697F. Set mul cost for leon3 to
> 	match standard leon3.

So UT699 is not a standard LEON3?

-- 
Eric Botcazou

Re: [PATCH] Update instruction cost for LEON

[Daniel Cederman]

On 2015-07-07 12:37, Eric Botcazou wrote:
>> 2015-07-03  Daniel Cederman  <cederman@gaisler.com>
>>
>> 	* config/sparc/sparc.c (struct processor_costs): Set div cost
>> 	for leon to match UT699 and AT697F. Set mul cost for leon3 to
>> 	match standard leon3.
>
> So UT699 is not a standard LEON3?
>

LEON3 exists in multiple revisions and is configurable so I agree that 
using the word standard in this context is a bit ambiguous.

I think we should delay applying this patch. First we need to look into 
how to properly provide the information on FPU selection and multiplier 
size to GCC. Otherwise we risk having to change the values again in a 
short while.

-- 
Daniel Cederman

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

[Daniel Cederman]

On 2015-07-07 12:35, Eric Botcazou wrote:
>> 2015-06-26  Daniel Cederman  <cederman@gaisler.com>
>>
>> 	* config/sparc/sparc.md: Window save takes a single integer
>
> This will probably break in 64-bit mode, the operand can be a DImode register.
>

You are right, I forgot about that. Is there a mode one can use that 
changes depending on the target architecture (32-bit on 32-bit 
architectures and 64-bit on 64-bit architectures)? Or does one have to 
add a 32-bit and a 64-bit variant of window_save?

-- 
Daniel Cederman

Re: [PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

[Daniel Cederman]

On 2015-07-07 12:32, Eric Botcazou wrote:
>
> ChangeLog must just describe the what, nothing more.  If the rationale is not
> obvious, then a comment must be added _in the code_ itself.
>
> 	* config/sparc/sparc.c (sparc_function_value_regno_p): Do not return
> 	true on %f0 for a target without FPU.
> 	* config/sparc/sparc.md (untyped_call): Do not save %f0 for a target
> 	without FPU.
> 	(untyped_return): Do not load %f0 for a target without FPU.
>

Understood. Thank you for looking at my patches and coming with 
improvements.

-- 
Daniel Cederman

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

[Eric Botcazou]

> You are right, I forgot about that. Is there a mode one can use that
> changes depending on the target architecture (32-bit on 32-bit
> architectures and 64-bit on 64-bit architectures)?

Yes, Pmode does exactly that, but you cannot use it directly in the MD file.

> Or does one have to add a 32-bit and a 64-bit variant of window_save?

Sort of, you can use the P mode iterator, but the name of the pattern will 
vary so you'll need to adjust the callers.

-- 
Eric Botcazou