* [PATCH 4/7] use #if for HARD_FRAME_POINTER_IS_FRAME_POINTER less
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 14:46 ` Segher Boessenkool
2015-07-06 12:12 ` [PATCH 6/7] reduce conditional compilation based on AUTO_INC_DEC tbsaunde+gcc
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (can_combine_def_p): Don't check the value of
* HARD_FRAME_POINTER_IS_FRAME_POINTER with the preprocessor.
(combinable_i3pat): Likewise.
(mark_used_regs_combine): Likewise.
* regrename.c (rename_chains): Likewise.
* reload.c (find_reloads_address): Likewise.
* sel-sched.c (mark_unavailable_hard_regs): Likewise.
---
gcc/combine.c | 14 +++++---------
gcc/regrename.c | 10 ++++------
gcc/reload.c | 5 ++---
gcc/sel-sched.c | 9 ++++-----
4 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index 6935934..da5c335 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1011,10 +1011,9 @@ can_combine_def_p (df_ref def)
/* Do not combine frame pointer adjustments. */
if ((regno == FRAME_POINTER_REGNUM
&& (!reload_completed || frame_pointer_needed))
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- || (regno == HARD_FRAME_POINTER_REGNUM
+ || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
+ && regno == HARD_FRAME_POINTER_REGNUM
&& (!reload_completed || frame_pointer_needed))
-#endif
|| (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
&& regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
return false;
@@ -2227,9 +2226,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
&& REG_P (subdest)
&& reg_referenced_p (subdest, PATTERN (i3))
&& REGNO (subdest) != FRAME_POINTER_REGNUM
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
-#endif
+ && (HARD_FRAME_POINTER_IS_FRAME_POINTER || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
&& (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
|| (REGNO (subdest) != ARG_POINTER_REGNUM
|| ! fixed_regs [REGNO (subdest)]))
@@ -13316,9 +13313,8 @@ mark_used_regs_combine (rtx x)
{
/* None of this applies to the stack, frame or arg pointers. */
if (regno == STACK_POINTER_REGNUM
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- || regno == HARD_FRAME_POINTER_REGNUM
-#endif
+ || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
+ && regno == HARD_FRAME_POINTER_REGNUM)
|| (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
&& regno == ARG_POINTER_REGNUM && fixed_regs[regno])
|| regno == FRAME_POINTER_REGNUM)
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 6c7d650..2e08669 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -447,12 +447,10 @@ rename_chains (void)
continue;
if (fixed_regs[reg] || global_regs[reg]
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- || (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM)
-#else
- || (frame_pointer_needed && reg == FRAME_POINTER_REGNUM)
-#endif
- )
+ || (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed
+ && reg == HARD_FRAME_POINTER_REGNUM)
+ || (HARD_FRAME_POINTER_REGNUM && frame_pointer_needed
+ && reg == FRAME_POINTER_REGNUM))
continue;
COPY_HARD_REG_SET (this_unavailable, unavailable);
diff --git a/gcc/reload.c b/gcc/reload.c
index 1dc04bf..4bc996f 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -5176,9 +5176,8 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
if ((regno_ok_for_base_p (REGNO (operand), mode, as, inner_code,
GET_CODE (addend))
|| operand == frame_pointer_rtx
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- || operand == hard_frame_pointer_rtx
-#endif
+ || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
+ && operand == hard_frame_pointer_rtx)
|| (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
&& operand == arg_pointer_rtx)
|| operand == stack_pointer_rtx)
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index be5d1d1..3f7d78b 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -1194,11 +1194,10 @@ mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
frame pointer, or we could not discover its class. */
if (fixed_regs[regno]
|| global_regs[regno]
-#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
- || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
-#else
- || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
-#endif
+ || (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed
+ && regno == HARD_FRAME_POINTER_REGNUM)
+ || (HARD_FRAME_POINTER_REGNUM && frame_pointer_needed
+ && regno == FRAME_POINTER_REGNUM)
|| (reload_completed && cl == NO_REGS))
{
SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 4/7] use #if for HARD_FRAME_POINTER_IS_FRAME_POINTER less
2015-07-06 12:12 ` [PATCH 4/7] use #if for HARD_FRAME_POINTER_IS_FRAME_POINTER less tbsaunde+gcc
@ 2015-07-06 14:46 ` Segher Boessenkool
0 siblings, 0 replies; 11+ messages in thread
From: Segher Boessenkool @ 2015-07-06 14:46 UTC (permalink / raw)
To: tbsaunde+gcc; +Cc: gcc-patches
On Mon, Jul 06, 2015 at 08:11:27AM -0400, tbsaunde+gcc@tbsaunde.org wrote:
> From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
>
> gcc/ChangeLog:
>
> 2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
>
> * combine.c (can_combine_def_p): Don't check the value of
> * HARD_FRAME_POINTER_IS_FRAME_POINTER with the preprocessor.
^ stray asterisk
> @@ -2227,9 +2226,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
> && REG_P (subdest)
> && reg_referenced_p (subdest, PATTERN (i3))
> && REGNO (subdest) != FRAME_POINTER_REGNUM
> -#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
> - && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
> -#endif
> + && (HARD_FRAME_POINTER_IS_FRAME_POINTER || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
That line is a bit long ;-)
Segher
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6/7] reduce conditional compilation based on AUTO_INC_DEC
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 4/7] use #if for HARD_FRAME_POINTER_IS_FRAME_POINTER less tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 1/7] reduce conditional compilation for LOAD_EXTEND_OP tbsaunde+gcc
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* auto-inc-dec.c (pass_inc_dec::execute): Don't check the value
of AUTO_INC_DEC with the preprocessor.
* combine.c (combine_instructions): Likewise.
(can_combine_p): Likewise.
(try_combine): Likewise.
* emit-rtl.c (try_split): Likewise.
* loop-invariant.c (calculate_loop_reg_pressure): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* lra.c (update_inc_notes): Likewise.
* recog.c (asm_operand_ok): Likewise.
(constrain_operands): Likewise.
* regrename.c (scan_rtx_address): Likewise.
* reload.c (update_auto_inc_notes): Likewise.
(reg_inc_found_and_valid_p): Likewise.
* reload1.c (reload): Likewise.
(emit_input_reload_insns): Likewise.
(delete_output_reload): Likewise.
* sched-deps.c (init_insn_reg_pressure_info): Likewise.
* valtrack.c (cleanup_auto_inc_dec): Likewise.
---
gcc/auto-inc-dec.c | 16 +++++-------
gcc/combine.c | 73 ++++++++++++++++++++++++----------------------------
gcc/emit-rtl.c | 7 +++--
gcc/loop-invariant.c | 10 +++----
gcc/lower-subreg.c | 30 ++++++++++-----------
gcc/lra.c | 8 +++---
gcc/recog.c | 13 +++-------
gcc/regrename.c | 4 +--
gcc/reload.c | 16 +++++-------
gcc/reload1.c | 20 +++++---------
gcc/sched-deps.c | 9 +++----
gcc/valtrack.c | 8 +++---
12 files changed, 89 insertions(+), 125 deletions(-)
diff --git a/gcc/auto-inc-dec.c b/gcc/auto-inc-dec.c
index dd183ee..831622b 100644
--- a/gcc/auto-inc-dec.c
+++ b/gcc/auto-inc-dec.c
@@ -123,7 +123,6 @@ along with GCC; see the file COPYING3. If not see
before the ref or +c if the increment was after the ref, then if we
can do the combination but switch the pre/post bit. */
-#if AUTO_INC_DEC
enum form
{
@@ -1448,8 +1447,6 @@ merge_in_block (int max_reg, basic_block bb)
}
}
-#endif
-
/* Discover auto-inc auto-dec instructions. */
namespace {
@@ -1477,11 +1474,10 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
-#if AUTO_INC_DEC
+ if (!AUTO_INC_DEC)
+ return false;
+
return (optimize > 0 && flag_auto_inc_dec);
-#else
- return false;
-#endif
}
@@ -1492,7 +1488,9 @@ public:
unsigned int
pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED)
{
-#if AUTO_INC_DEC
+ if (!AUTO_INC_DEC)
+ return 0;
+
basic_block bb;
int max_reg = max_reg_num ();
@@ -1515,7 +1513,7 @@ pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED)
free (reg_next_def);
mem_tmp = NULL;
-#endif
+
return 0;
}
diff --git a/gcc/combine.c b/gcc/combine.c
index 346bdff..96cc3cd 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1204,9 +1204,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
FOR_BB_INSNS (this_basic_block, insn)
if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
{
-#if AUTO_INC_DEC
rtx links;
-#endif
subst_low_luid = DF_INSN_LUID (insn);
subst_insn = insn;
@@ -1215,12 +1213,11 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
insn);
record_dead_and_set_regs (insn);
-#if AUTO_INC_DEC
- for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
- if (REG_NOTE_KIND (links) == REG_INC)
- set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
- insn);
-#endif
+ if (AUTO_INC_DEC)
+ for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
+ if (REG_NOTE_KIND (links) == REG_INC)
+ set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
+ insn);
/* Record the current insn_rtx_cost of this instruction. */
if (NONJUMP_INSN_P (insn))
@@ -1798,9 +1795,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
const_rtx set = 0;
rtx src, dest;
rtx_insn *p;
-#if AUTO_INC_DEC
rtx link;
-#endif
bool all_adjacent = true;
int (*is_volatile_p) (const_rtx);
@@ -2079,22 +2074,21 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
Also insist that I3 not be a jump; if it were one
and the incremented register were spilled, we would lose. */
-#if AUTO_INC_DEC
- for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
- if (REG_NOTE_KIND (link) == REG_INC
- && (JUMP_P (i3)
- || reg_used_between_p (XEXP (link, 0), insn, i3)
- || (pred != NULL_RTX
- && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
- || (pred2 != NULL_RTX
- && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
- || (succ != NULL_RTX
- && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
- || (succ2 != NULL_RTX
- && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
- || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
- return 0;
-#endif
+ if (AUTO_INC_DEC)
+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
+ if (REG_NOTE_KIND (link) == REG_INC
+ && (JUMP_P (i3)
+ || reg_used_between_p (XEXP (link, 0), insn, i3)
+ || (pred != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
+ || (pred2 != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
+ || (succ != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
+ || (succ2 != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
+ || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
+ return 0;
/* Don't combine an insn that follows a CC0-setting insn.
An insn that uses CC0 must not be separated from the one that sets it.
@@ -3045,20 +3039,19 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
|| GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
/* It's not the exception. */
#endif
-#if AUTO_INC_DEC
- {
- rtx link;
- for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
- if (REG_NOTE_KIND (link) == REG_INC
- && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
- || (i1 != 0
- && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
- {
- undo_all ();
- return 0;
- }
- }
-#endif
+ if (AUTO_INC_DEC)
+ {
+ rtx link;
+ for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
+ if (REG_NOTE_KIND (link) == REG_INC
+ && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
+ || (i1 != 0
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
+ {
+ undo_all ();
+ return 0;
+ }
+ }
/* See if the SETs in I1 or I2 need to be kept around in the merged
instruction: whenever the value set there is still needed past I3.
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index eb44066..12984299 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -3594,7 +3594,6 @@ prev_cc0_setter (rtx_insn *insn)
return insn;
}
-#if AUTO_INC_DEC
/* Find a RTX_AUTOINC class rtx which matches DATA. */
static int
@@ -3610,7 +3609,6 @@ find_auto_inc (const_rtx x, const_rtx reg)
}
return false;
}
-#endif
/* Increment the label uses for all labels present in rtx. */
@@ -3782,8 +3780,10 @@ try_split (rtx pat, rtx_insn *trial, int last)
}
break;
-#if AUTO_INC_DEC
case REG_INC:
+ if (!AUTO_INC_DEC)
+ break;
+
for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
{
rtx reg = XEXP (note, 0);
@@ -3792,7 +3792,6 @@ try_split (rtx pat, rtx_insn *trial, int last)
add_reg_note (insn, REG_INC, reg);
}
break;
-#endif
case REG_ARGS_SIZE:
fixup_args_size_notes (NULL, insn_last, INTVAL (XEXP (note, 0)));
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index 1285c66..d6c2c04 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1998,11 +1998,11 @@ calculate_loop_reg_pressure (void)
note_stores (PATTERN (insn), mark_reg_store, NULL);
-#if AUTO_INC_DEC
- for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
- if (REG_NOTE_KIND (link) == REG_INC)
- mark_reg_store (XEXP (link, 0), NULL_RTX, NULL);
-#endif
+ if (AUTO_INC_DEC)
+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
+ if (REG_NOTE_KIND (link) == REG_INC)
+ mark_reg_store (XEXP (link, 0), NULL_RTX, NULL);
+
while (n_regs_set-- > 0)
{
rtx note = find_regno_note (insn, REG_UNUSED,
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index a57ce43..edcf73d 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -948,19 +948,19 @@ resolve_simple_move (rtx set, rtx_insn *insn)
reg = gen_reg_rtx (orig_mode);
-#if AUTO_INC_DEC
- {
- rtx move = emit_move_insn (reg, src);
- if (MEM_P (src))
- {
- rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
- if (note)
- add_reg_note (move, REG_INC, XEXP (note, 0));
- }
- }
-#else
- emit_move_insn (reg, src);
-#endif
+ if (AUTO_INC_DEC)
+ {
+ rtx move = emit_move_insn (reg, src);
+ if (MEM_P (src))
+ {
+ rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
+ if (note)
+ add_reg_note (move, REG_INC, XEXP (note, 0));
+ }
+ }
+ else
+ emit_move_insn (reg, src);
+
src = reg;
}
@@ -1051,15 +1051,13 @@ resolve_simple_move (rtx set, rtx_insn *insn)
mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0);
minsn = emit_move_insn (real_dest, mdest);
-#if AUTO_INC_DEC
- if (MEM_P (real_dest)
+ if (AUTO_INC_DEC && MEM_P (real_dest)
&& !(resolve_reg_p (real_dest) || resolve_subreg_p (real_dest)))
{
rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
if (note)
add_reg_note (minsn, REG_INC, XEXP (note, 0));
}
-#endif
smove = single_set (minsn);
gcc_assert (smove != NULL_RTX);
diff --git a/gcc/lra.c b/gcc/lra.c
index 0bf822f..7a22996 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -2093,7 +2093,6 @@ has_nonexceptional_receiver (void)
return false;
}
-#if AUTO_INC_DEC
/* Process recursively X of INSN and add REG_INC notes if necessary. */
static void
@@ -2121,7 +2120,6 @@ add_auto_inc_notes (rtx_insn *insn, rtx x)
}
}
-#endif
/* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
We change pseudos by hard registers without notification of DF and
@@ -2148,9 +2146,9 @@ update_inc_notes (void)
else
pnote = &XEXP (*pnote, 1);
}
-#if AUTO_INC_DEC
- add_auto_inc_notes (insn, PATTERN (insn));
-#endif
+
+ if (AUTO_INC_DEC)
+ add_auto_inc_notes (insn, PATTERN (insn));
}
}
diff --git a/gcc/recog.c b/gcc/recog.c
index 2e8be6a..0d40da3 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1720,9 +1720,7 @@ int
asm_operand_ok (rtx op, const char *constraint, const char **constraints)
{
int result = 0;
-#if AUTO_INC_DEC
bool incdec_ok = false;
-#endif
/* Use constrain_operands after reload. */
gcc_assert (!reload_completed);
@@ -1790,7 +1788,6 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
result = 1;
break;
-#if AUTO_INC_DEC
case '<':
case '>':
/* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
@@ -1800,7 +1797,6 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
Match any memory and hope things are resolved after reload. */
incdec_ok = true;
-#endif
default:
cn = lookup_constraint (constraint);
switch (get_constraint_type (cn))
@@ -1844,9 +1840,8 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
return 0;
}
-#if AUTO_INC_DEC
/* For operands without < or > constraints reject side-effects. */
- if (!incdec_ok && result && MEM_P (op))
+ if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
switch (GET_CODE (XEXP (op, 0)))
{
case PRE_INC:
@@ -1859,7 +1854,6 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
default:
break;
}
-#endif
return result;
}
@@ -2822,9 +2816,8 @@ constrain_operands (int strict, alternative_mask alternatives)
= recog_data.operand[funny_match[funny_match_index].this_op];
}
-#if AUTO_INC_DEC
/* For operands without < or > constraints reject side-effects. */
- if (recog_data.is_asm)
+ if (AUTO_INC_DEC && recog_data.is_asm)
{
for (opno = 0; opno < recog_data.n_operands; opno++)
if (MEM_P (recog_data.operand[opno]))
@@ -2845,7 +2838,7 @@ constrain_operands (int strict, alternative_mask alternatives)
break;
}
}
-#endif
+
return 1;
}
}
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 0fce77e..f10ea09 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1312,11 +1312,11 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
case PRE_INC:
case PRE_DEC:
case PRE_MODIFY:
-#if !AUTO_INC_DEC
/* If the target doesn't claim to handle autoinc, this must be
something special, like a stack push. Kill this chain. */
+ if (!AUTO_INC_DEC)
action = mark_all_read;
-#endif
+
break;
case MEM:
diff --git a/gcc/reload.c b/gcc/reload.c
index 3323816..0fdf97e 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -5454,14 +5454,13 @@ static void
update_auto_inc_notes (rtx_insn *insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED,
int reloadnum ATTRIBUTE_UNUSED)
{
-#if AUTO_INC_DEC
- rtx link;
+ if (!AUTO_INC_DEC)
+ return;
- for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
+ for (rtx link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_INC
&& (int) REGNO (XEXP (link, 0)) == regno)
push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
-#endif
}
\f
/* Record the pseudo registers we must reload into hard registers in a
@@ -7175,13 +7174,15 @@ find_inc_amount (rtx x, rtx inced)
/* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
REG_INC note in insn INSN. REGNO must refer to a hard register. */
-#if AUTO_INC_DEC
static int
reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
rtx insn)
{
rtx link;
+ if (!AUTO_INC_DEC)
+ return 0;
+
gcc_assert (insn);
if (! INSN_P (insn))
@@ -7196,11 +7197,6 @@ reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
}
return 0;
}
-#else
-
-#define reg_inc_found_and_valid_p(regno,endregno,insn) 0
-
-#endif
/* Return 1 if register REGNO is the subject of a clobber in insn INSN.
If SETS is 1, also consider SETs. If SETS is 2, enable checking
diff --git a/gcc/reload1.c b/gcc/reload1.c
index f05596f..e80ebf9 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -424,9 +424,7 @@ static void delete_output_reload (rtx_insn *, int, int, rtx);
static void delete_address_reloads (rtx_insn *, rtx_insn *);
static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
static void inc_for_reload (rtx, rtx, rtx, int);
-#if AUTO_INC_DEC
static void add_auto_inc_notes (rtx_insn *, rtx);
-#endif
static void substitute (rtx *, const_rtx, rtx);
static bool gen_reload_chain_without_interm_reg_p (int, int);
static int reloads_conflict (int, int);
@@ -1257,9 +1255,8 @@ reload (rtx_insn *first, int global)
pnote = &XEXP (*pnote, 1);
}
-#if AUTO_INC_DEC
- add_auto_inc_notes (insn, PATTERN (insn));
-#endif
+ if (AUTO_INC_DEC)
+ add_auto_inc_notes (insn, PATTERN (insn));
/* Simplify (subreg (reg)) if it appears as an operand. */
cleanup_subreg_operands (insn);
@@ -7401,10 +7398,7 @@ emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
is ill-formed and we must reject this optimization. */
extract_insn (temp);
if (constrain_operands (1, get_enabled_alternatives (temp))
-#if AUTO_INC_DEC
- && ! find_reg_note (temp, REG_INC, reloadreg)
-#endif
- )
+ && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
{
/* If the previous insn is an output reload, the source is
a reload register, and its spill_reg_store entry will
@@ -8874,10 +8868,10 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
continue;
if (MEM_P (reg2) || reload_override_in[k])
reg2 = rld[k].in_reg;
-#if AUTO_INC_DEC
- if (rld[k].out && ! rld[k].out_reg)
+
+ if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
-#endif
+
while (GET_CODE (reg2) == SUBREG)
reg2 = SUBREG_REG (reg2);
if (rtx_equal_p (reg2, reg))
@@ -9270,7 +9264,6 @@ inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
}
}
\f
-#if AUTO_INC_DEC
static void
add_auto_inc_notes (rtx_insn *insn, rtx x)
{
@@ -9295,4 +9288,3 @@ add_auto_inc_notes (rtx_insn *insn, rtx x)
add_auto_inc_notes (insn, XVECEXP (x, i, j));
}
}
-#endif
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index a2ab8e5..96a4dc4 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2228,11 +2228,10 @@ init_insn_reg_pressure_info (rtx_insn *insn)
note_stores (PATTERN (insn), mark_insn_reg_store, insn);
-#if AUTO_INC_DEC
- for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
- if (REG_NOTE_KIND (link) == REG_INC)
- mark_insn_reg_store (XEXP (link, 0), NULL_RTX, insn);
-#endif
+ if (AUTO_INC_DEC)
+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
+ if (REG_NOTE_KIND (link) == REG_INC)
+ mark_insn_reg_store (XEXP (link, 0), NULL_RTX, insn);
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD)
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 8646a63..e0d17f9 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -57,7 +57,9 @@ static rtx
cleanup_auto_inc_dec (rtx src, machine_mode mem_mode ATTRIBUTE_UNUSED)
{
rtx x = src;
-#if AUTO_INC_DEC
+ if (!AUTO_INC_DEC)
+ return copy_rtx (x);
+
const RTX_CODE code = GET_CODE (x);
int i;
const char *fmt;
@@ -140,10 +142,6 @@ cleanup_auto_inc_dec (rtx src, machine_mode mem_mode ATTRIBUTE_UNUSED)
= cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
}
-#else /* !AUTO_INC_DEC */
- x = copy_rtx (x);
-#endif /* !AUTO_INC_DEC */
-
return x;
}
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/7] reduce conditional compilation for LOAD_EXTEND_OP
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 4/7] use #if for HARD_FRAME_POINTER_IS_FRAME_POINTER less tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 6/7] reduce conditional compilation based on AUTO_INC_DEC tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 7/7] always define WORD_REGISTER_OPERATIONS tbsaunde+gcc
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
Provide a default in files where that is possible, so that everything
else there can be unconditionally compiled. However rtlanal.c and
reload.c do tricky things that break providing a global default, so we
can't do that yet.
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (try_combine): Don't check if LOAD_EXTEND_OP is
defined.
(simplify_set): Likewise.
* cse.c (cse_insn): Likewise.
* fold-const.c (fold_single_bit_test): Likewise.
(fold_unary_loc): Likewise.
* postreload.c (reload_cse_simplify_set): Likewise.
(reload_cse_simplify_operands): Likewise.
---
gcc/combine.c | 8 ++++----
gcc/cse.c | 6 ++++--
gcc/fold-const.c | 10 ++++------
gcc/postreload.c | 18 ++++++------------
4 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index 8eaae7c..8b1e9f4 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -120,6 +120,10 @@ along with GCC; see the file COPYING3. If not see
#include "obstack.h"
#include "rtl-iter.h"
+#ifndef LOAD_EXTEND_OP
+#define LOAD_EXTEND_OP(M) UNKNOWN
+#endif
+
/* Number of attempts to combine instructions in this function. */
static int combine_attempts;
@@ -3751,7 +3755,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
be written as a ZERO_EXTEND. */
if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
{
-#ifdef LOAD_EXTEND_OP
/* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
what it really is. */
if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
@@ -3759,7 +3762,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
SUBREG_REG (*split)));
else
-#endif
SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
SUBREG_REG (*split)));
}
@@ -6779,7 +6781,6 @@ simplify_set (rtx x)
}
}
-#ifdef LOAD_EXTEND_OP
/* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
would require a paradoxical subreg. Replace the subreg with a
zero_extend to avoid the reload that would otherwise be required. */
@@ -6797,7 +6798,6 @@ simplify_set (rtx x)
src = SET_SRC (x);
}
-#endif
/* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
are comparing an item known to be 0 or -1 against 0, use a logical
diff --git a/gcc/cse.c b/gcc/cse.c
index e01240c..b286417 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -58,6 +58,10 @@ along with GCC; see the file COPYING3. If not see
#include "dbgcnt.h"
#include "rtl-iter.h"
+#ifndef LOAD_EXTEND_OP
+#define LOAD_EXTEND_OP(M) UNKNOWN
+#endif
+
/* The basic idea of common subexpression elimination is to go
through the code, keeping a record of expressions that would
have the same value at the current scan point, and replacing
@@ -4873,7 +4877,6 @@ cse_insn (rtx_insn *insn)
}
}
-#ifdef LOAD_EXTEND_OP
/* See if a MEM has already been loaded with a widening operation;
if it has, we can use a subreg of that. Many CISC machines
also have such operations, but this is only likely to be
@@ -4919,7 +4922,6 @@ cse_insn (rtx_insn *insn)
break;
}
}
-#endif /* LOAD_EXTEND_OP */
/* Try to express the constant using a register+offset expression
derived from a constant anchor. */
diff --git a/gcc/fold-const.c b/gcc/fold-const.c
index 5da6ed3..c8a0520 100644
--- a/gcc/fold-const.c
+++ b/gcc/fold-const.c
@@ -84,6 +84,10 @@ along with GCC; see the file COPYING3. If not see
#include "generic-match.h"
#include "optabs.h"
+#ifndef LOAD_EXTEND_OP
+#define LOAD_EXTEND_OP(M) UNKNOWN
+#endif
+
/* Nonzero if we are folding constants inside an initializer; zero
otherwise. */
int folding_initializer = 0;
@@ -6850,12 +6854,8 @@ fold_single_bit_test (location_t loc, enum tree_code code,
/* If we are going to be able to omit the AND below, we must do our
operations as unsigned. If we must use the AND, we have a choice.
Normally unsigned is faster, but for some machines signed is. */
-#ifdef LOAD_EXTEND_OP
ops_unsigned = (LOAD_EXTEND_OP (operand_mode) == SIGN_EXTEND
&& !flag_syntax_only) ? 0 : 1;
-#else
- ops_unsigned = 1;
-#endif
signed_type = lang_hooks.types.type_for_mode (operand_mode, 0);
unsigned_type = lang_hooks.types.type_for_mode (operand_mode, 1);
@@ -8019,7 +8019,6 @@ fold_unary_loc (location_t loc, enum tree_code code, tree type, tree op0)
cst &= HOST_WIDE_INT_M1U
<< (TYPE_PRECISION (TREE_TYPE (and1)) - 1);
change = (cst == 0);
-#ifdef LOAD_EXTEND_OP
if (change
&& !flag_syntax_only
&& (LOAD_EXTEND_OP (TYPE_MODE (TREE_TYPE (and0)))
@@ -8029,7 +8028,6 @@ fold_unary_loc (location_t loc, enum tree_code code, tree type, tree op0)
and0 = fold_convert_loc (loc, uns, and0);
and1 = fold_convert_loc (loc, uns, and1);
}
-#endif
}
if (change)
{
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 704428a..1fec0b0 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -61,6 +61,10 @@ along with GCC; see the file COPYING3. If not see
#include "df.h"
#include "dbgcnt.h"
+#ifndef LOAD_EXTEND_OP
+#define LOAD_EXTEND_OP(M) UNKNOWN
+#endif
+
static int reload_cse_noop_set_p (rtx);
static bool reload_cse_simplify (rtx_insn *, rtx);
static void reload_cse_regs_1 (void);
@@ -261,9 +265,7 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
int old_cost;
cselib_val *val;
struct elt_loc_list *l;
-#ifdef LOAD_EXTEND_OP
enum rtx_code extend_op = UNKNOWN;
-#endif
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
dreg = true_regnum (SET_DEST (set));
@@ -276,7 +278,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
dclass = REGNO_REG_CLASS (dreg);
-#ifdef LOAD_EXTEND_OP
/* When replacing a memory with a register, we need to honor assumptions
that combine made wrt the contents of sign bits. We'll do this by
generating an extend instruction instead of a reg->reg copy. Thus
@@ -286,7 +287,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
&& (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
&& !REG_P (SET_DEST (set)))
return 0;
-#endif
val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
if (! val)
@@ -308,7 +308,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
{
-#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
wide_int result;
@@ -333,19 +332,17 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
}
this_rtx = immed_wide_int_const (result, word_mode);
}
-#endif
+
this_cost = set_src_cost (this_rtx, speed);
}
else if (REG_P (this_rtx))
{
-#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
this_cost = set_src_cost (this_rtx, speed);
}
else
-#endif
this_cost = register_move_cost (GET_MODE (this_rtx),
REGNO_REG_CLASS (REGNO (this_rtx)),
dclass);
@@ -360,7 +357,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
&& REG_P (this_rtx)
&& !REG_P (SET_SRC (set))))
{
-#ifdef LOAD_EXTEND_OP
if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
&& extend_op != UNKNOWN
#ifdef CANNOT_CHANGE_MODE_CLASS
@@ -374,7 +370,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
validate_change (insn, &SET_DEST (set), wide_dest, 1);
}
-#endif
validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
old_cost = this_cost, did_change = 1;
@@ -446,7 +441,6 @@ reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
continue;
op = recog_data.operand[i];
-#ifdef LOAD_EXTEND_OP
if (MEM_P (op)
&& GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
&& LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
@@ -497,7 +491,7 @@ reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
safe to optimize, but is it worth the trouble? */
continue;
}
-#endif /* LOAD_EXTEND_OP */
+
if (side_effects_p (op))
continue;
v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 7/7] always define WORD_REGISTER_OPERATIONS
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
` (2 preceding siblings ...)
2015-07-06 12:12 ` [PATCH 1/7] reduce conditional compilation for LOAD_EXTEND_OP tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 14:04 ` Segher Boessenkool
2015-07-06 12:12 ` [PATCH 3/7] always define SHORT_IMMEDIATES_SIGN_EXTEND tbsaunde+gcc
` (2 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
* config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
* config/arc/arc.h: Likewise.
* config/arm/arm.h: Likewise.
* config/bfin/bfin.h: Likewise.
* config/epiphany/epiphany.h: Likewise.
* config/frv/frv.h: Likewise.
* config/ia64/ia64.h: Likewise.
* config/iq2000/iq2000.h: Likewise.
* config/lm32/lm32.h: Likewise.
* config/m32r/m32r.h: Likewise.
* config/mcore/mcore.h: Likewise.
* config/mep/mep.h: Likewise.
* config/microblaze/microblaze.h: Likewise.
* config/mips/mips.h: Likewise.
* config/mmix/mmix.h:
* config/mn10300/mn10300.h:
* config/nds32/nds32.h:
* config/nios2/nios2.h:
* config/pa/pa.h:
* config/rl78/rl78.h:
* config/sh/sh.h:
* config/sparc/sparc.h:
* config/stormy16/stormy16.h (enum reg_class):
* config/tilegx/tilegx.h:
* config/tilepro/tilepro.h:
* config/v850/v850.h:
* config/xtensa/xtensa.h:
* doc/tm.texi: Regenerate.
* doc/tm.texi.in: Adjust.
* combine.c (simplify_set): Likewise.
(simplify_comparison): Likewise.
* expr.c (store_constructor): Likewise.
* internal-fn.c (expand_arith_overflow): Likewise.
* reload.c (push_reload): Likewise.
(find_reloads): Likewise.
(find_reloads_subreg_address): Likewise.
* reload1.c (eliminate_regs_1): Likewise.
* rtlanal.c (nonzero_bits1): Likewise.
(num_sign_bit_copies1): Likewise.
* simplify-rtx.c (simplify_truncation): Likewise.
---
gcc/combine.c | 14 ++++++--------
gcc/config/alpha/alpha.h | 2 +-
gcc/config/arc/arc.h | 2 +-
gcc/config/arm/arm.h | 2 +-
gcc/config/bfin/bfin.h | 2 +-
gcc/config/epiphany/epiphany.h | 2 +-
gcc/config/frv/frv.h | 2 +-
gcc/config/ia64/ia64.h | 2 +-
gcc/config/iq2000/iq2000.h | 2 +-
gcc/config/lm32/lm32.h | 2 +-
gcc/config/m32r/m32r.h | 2 +-
gcc/config/mcore/mcore.h | 4 ++--
gcc/config/mep/mep.h | 2 +-
gcc/config/microblaze/microblaze.h | 2 +-
gcc/config/mips/mips.h | 2 +-
gcc/config/mmix/mmix.h | 2 +-
gcc/config/mn10300/mn10300.h | 2 +-
gcc/config/nds32/nds32.h | 2 +-
gcc/config/nios2/nios2.h | 2 +-
gcc/config/pa/pa.h | 2 +-
gcc/config/rl78/rl78.h | 2 +-
gcc/config/sh/sh.h | 2 +-
gcc/config/sparc/sparc.h | 2 +-
gcc/config/stormy16/stormy16.h | 2 +-
gcc/config/tilegx/tilegx.h | 2 +-
gcc/config/tilepro/tilepro.h | 2 +-
gcc/config/v850/v850.h | 2 +-
gcc/config/xtensa/xtensa.h | 2 +-
gcc/defaults.h | 4 ++++
gcc/doc/tm.texi | 2 +-
gcc/doc/tm.texi.in | 2 +-
gcc/expr.c | 6 +-----
gcc/internal-fn.c | 11 +++++------
gcc/reload.c | 19 ++++++++-----------
gcc/reload1.c | 2 +-
gcc/rtlanal.c | 18 +++++++-----------
gcc/simplify-rtx.c | 4 +---
37 files changed, 63 insertions(+), 75 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index 96cc3cd..0b36245 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -6719,10 +6719,9 @@ simplify_set (rtx x)
/ UNITS_PER_WORD)
== ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
+ (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
-#ifndef WORD_REGISTER_OPERATIONS
- && (GET_MODE_SIZE (GET_MODE (src))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
-#endif
+ && (WORD_REGISTER_OPERATIONS
+ || (GET_MODE_SIZE (GET_MODE (src))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
#ifdef CANNOT_CHANGE_MODE_CLASS
&& ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
&& REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
@@ -11417,7 +11416,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
/* Try a few ways of applying the same transformation to both operands. */
while (1)
{
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
/* The test below this one won't handle SIGN_EXTENDs on these machines,
so check specially. */
if (code != GTU && code != GEU && code != LTU && code != LEU
@@ -12072,10 +12071,9 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
they no longer have defined values and the meaning of
the code has been changed. */
&& (0
-#ifdef WORD_REGISTER_OPERATIONS
- || (mode_width > GET_MODE_PRECISION (tmode)
+ || (!WORD_REGISTER_OPERATIONS
+ && mode_width > GET_MODE_PRECISION (tmode)
&& mode_width <= BITS_PER_WORD)
-#endif
|| (mode_width <= GET_MODE_PRECISION (tmode)
&& subreg_lowpart_p (XEXP (op0, 0))))
&& CONST_INT_P (XEXP (op0, 1))
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index c39f103..3fb58b1 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -888,7 +888,7 @@ do { \
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 4fdd654..d98cce1 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1540,7 +1540,7 @@ extern int arc_return_address_regs[4];
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 373dc85..836e517 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1904,7 +1904,7 @@ enum arm_auto_incmodes
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index b0d017e..26ba7c2 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -982,7 +982,7 @@ typedef struct {
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified.
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
*/
/* Evaluates to true if A and B are mac flags that can be used
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 5515edb..62a3d9d 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -845,7 +845,7 @@ do \
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index a96f201b..b0d66fd 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1882,7 +1882,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE)
/* Define this macro if operations between registers with integral mode smaller
than a word are always performed on the entire register. Most RISC machines
have this property and most CISC machines do not. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define this macro to be a C expression indicating when insns that read
memory in MODE, an integral mode narrower than a word, set the bits outside
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index 943faf9..4b62423 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -1631,7 +1631,7 @@ do { \
/* Define this macro if operations between registers with integral mode smaller
than a word are always performed on the entire register. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define this macro to be a C expression indicating when insns that read
memory in MODE, an integral mode narrower than a word, set the bits outside
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 14a68ce..73b1205 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -541,7 +541,7 @@ while (0)
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index 9872860..986383f 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -521,7 +521,7 @@ do { \
#define CASE_VECTOR_MODE Pmode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 2163de4..fa06135 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -1004,7 +1004,7 @@ L2: .word STATIC
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index 0aa9680..999d536 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -639,7 +639,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
@@ -673,7 +673,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
and another. All register moves are cheap. */
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Assembler output control. */
#define ASM_COMMENT_START "\t//"
diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h
index 8fee273..f7322cb7 100644
--- a/gcc/config/mep/mep.h
+++ b/gcc/config/mep/mep.h
@@ -762,7 +762,7 @@ typedef struct
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
#define SHORT_IMMEDIATES_SIGN_EXTEND 1
diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
index c832fa0..482c4a2 100644
--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
@@ -235,7 +235,7 @@ extern enum pipeline_type microblaze_pipe;
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
&& (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 33469be..ef5260a 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1598,7 +1598,7 @@ FP_ASM_SPEC "\
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* When in 64-bit mode, move insns will sign extend SImode and CCmode
moves. All other references are zero extended. */
diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h
index 61ae4d6..d15d90e 100644
--- a/gcc/config/mmix/mmix.h
+++ b/gcc/config/mmix/mmix.h
@@ -793,7 +793,7 @@ typedef struct { int regs; int lib; } CUMULATIVE_ARGS;
#define CASE_VECTOR_MODE DImode
#define CASE_VECTOR_PC_RELATIVE 0
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* We have a choice, which makes this yet another parameter to tweak. The
gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index e5fa70b..dbedb18 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -699,7 +699,7 @@ do { \
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index dcecea7..126b5861 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -1001,7 +1001,7 @@ enum reg_class
/* Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* A C expression indicating when insns that read memory in mem_mode,
an integral mode narrower than a word, set the bits outside of mem_mode
diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h
index 45eb70b..5856d7d 100644
--- a/gcc/config/nios2/nios2.h
+++ b/gcc/config/nios2/nios2.h
@@ -497,6 +497,6 @@ do { \
#define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#endif /* GCC_NIOS2_H */
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 4259a07..d7daabf 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1011,7 +1011,7 @@ do { \
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h
index 066b0d1..6c72fac 100644
--- a/gcc/config/rl78/rl78.h
+++ b/gcc/config/rl78/rl78.h
@@ -144,7 +144,7 @@
#define POINTERS_EXTEND_UNSIGNED 1
#define FUNCTION_MODE HImode
#define CASE_VECTOR_MODE Pmode
-#define WORD_REGISTER_OPERATIONS 0
+#define WORD_REGISTER_OPERATIONS 1
#define HAS_LONG_COND_BRANCH 0
#define HAS_LONG_UNCOND_BRANCH 0
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index c4947a6..7aa489d 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1813,7 +1813,7 @@ struct sh_args {
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 72dd18b..2cbe0d9 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1460,7 +1460,7 @@ do { \
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h
index 38a2a06..ef787fd 100644
--- a/gcc/config/stormy16/stormy16.h
+++ b/gcc/config/stormy16/stormy16.h
@@ -487,7 +487,7 @@ enum reg_class
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h
index 7c3995a..ac134b9 100644
--- a/gcc/config/tilegx/tilegx.h
+++ b/gcc/config/tilegx/tilegx.h
@@ -367,7 +367,7 @@ enum reg_class
#define CLEAR_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
#define SET_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h
index 970135a..a6d8c4e 100644
--- a/gcc/config/tilepro/tilepro.h
+++ b/gcc/config/tilepro/tilepro.h
@@ -331,7 +331,7 @@ enum reg_class
#define CLEAR_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
#define SET_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h
index e40fd87..45ff1d5 100644
--- a/gcc/config/v850/v850.h
+++ b/gcc/config/v850/v850.h
@@ -864,7 +864,7 @@ typedef enum
#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
ASM_OUTPUT_ALIGN ((FILE), (TARGET_BIG_SWITCH ? 2 : 1));
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Byte and short loads sign extend the value to a word. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index fb8702c..ebc8792 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -197,7 +197,7 @@ extern unsigned xtensa_current_frame_size;
/* Operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Xtensa loads are zero-extended by default. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 9dc59d2..b1208e9 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1269,6 +1269,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define SHORT_IMMEDIATES_SIGN_EXTEND 0
#endif
+#ifndef WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 0
+#endif
+
#ifdef GCC_INSN_FLAGS_H
/* Dependent default target macro definitions
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 620fc2a..cedf8ee 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10377,7 +10377,7 @@ five otherwise. This is best for most machines.
@end deftypefn
@defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Most RISC machines have this property and most CISC machines do not.
@end defmac
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 59aa589..47550cc 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7501,7 +7501,7 @@ is in effect.
@hook TARGET_CASE_VALUES_THRESHOLD
@defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Most RISC machines have this property and most CISC machines do not.
@end defmac
diff --git a/gcc/expr.c b/gcc/expr.c
index 5c0df44..95a168e 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5999,9 +5999,7 @@ static void
store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
{
tree type = TREE_TYPE (exp);
-#ifdef WORD_REGISTER_OPERATIONS
HOST_WIDE_INT exp_size = int_size_in_bytes (type);
-#endif
switch (TREE_CODE (type))
{
@@ -6114,13 +6112,12 @@ store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
highest_pow2_factor (offset));
}
-#ifdef WORD_REGISTER_OPERATIONS
/* If this initializes a field that is smaller than a
word, at the start of a word, try to widen it to a full
word. This special case allows us to output C++ member
function initializations in a form that the optimizers
can understand. */
- if (REG_P (target)
+ if (WORD_REGISTER_OPERATIONS && REG_P (target)
&& bitsize < BITS_PER_WORD
&& bitpos % BITS_PER_WORD == 0
&& GET_MODE_CLASS (mode) == MODE_INT
@@ -6145,7 +6142,6 @@ store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
bitsize = BITS_PER_WORD;
mode = word_mode;
}
-#endif
if (MEM_P (to_rtx) && !MEM_KEEP_ALIAS_SET_P (to_rtx)
&& DECL_NONADDRESSABLE_P (field))
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index c398c12..1ead83f 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -1736,15 +1736,14 @@ expand_arith_overflow (enum tree_code code, gimple stmt)
return;
}
-#ifdef WORD_REGISTER_OPERATIONS
/* For sub-word operations, if target doesn't have them, start
with precres widening right away, otherwise do it only
if the most simple cases can't be used. */
- if (orig_precres == precres && precres < BITS_PER_WORD)
+ if (WORD_REGISTER_OPERATIONS && orig_precres == precres
+ && precres < BITS_PER_WORD)
;
- else
-#endif
- if ((uns0_p && uns1_p && unsr_p && prec0 <= precres && prec1 <= precres)
+ else if ((uns0_p && uns1_p && unsr_p && prec0 <= precres
+ && prec1 <= precres)
|| ((!uns0_p || !uns1_p) && !unsr_p
&& prec0 + uns0_p <= precres
&& prec1 + uns1_p <= precres))
@@ -1773,7 +1772,7 @@ expand_arith_overflow (enum tree_code code, gimple stmt)
/* For sub-word operations, retry with a wider type first. */
if (orig_precres == precres && precop <= BITS_PER_WORD)
{
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
int p = BITS_PER_WORD;
#else
int p = precop;
diff --git a/gcc/reload.c b/gcc/reload.c
index 0fdf97e..32d7a6a 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -1093,7 +1093,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
&& INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
&& LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
#endif
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
|| ((GET_MODE_PRECISION (inmode)
< GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in))))
&& ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
@@ -1131,8 +1131,8 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#endif
inloc = &SUBREG_REG (in);
in = *inloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
- if (MEM_P (in))
+#if ! defined (LOAD_EXTEND_OP)
+ if (!WORD_REGISTER_OPERATIONS && MEM_P (in))
/* This is supposed to happen only for paradoxical subregs made by
combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
@@ -1193,7 +1193,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
|| MEM_P (SUBREG_REG (out)))
&& ((GET_MODE_PRECISION (outmode)
> GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
|| ((GET_MODE_PRECISION (outmode)
< GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
&& ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
@@ -1227,11 +1227,9 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#endif
outloc = &SUBREG_REG (out);
out = *outloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
- gcc_assert (!MEM_P (out)
+ gcc_assert (WORD_REGISTER_OPERATIONS || !MEM_P (out)
|| GET_MODE_SIZE (GET_MODE (out))
<= GET_MODE_SIZE (outmode));
-#endif
outmode = GET_MODE (out);
}
@@ -3159,7 +3157,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
|| ((MEM_P (operand)
|| (REG_P (operand)
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER))
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
&& (((GET_MODE_BITSIZE (GET_MODE (operand))
< BIGGEST_ALIGNMENT)
&& (GET_MODE_SIZE (operand_mode[i])
@@ -6167,12 +6165,11 @@ find_reloads_subreg_address (rtx x, int opnum, enum reload_type type,
if (paradoxical_subreg_p (x))
return NULL;
-#ifdef WORD_REGISTER_OPERATIONS
- if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
+ if (WORD_REGISTER_OPERATIONS
+ && GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
&& ((GET_MODE_SIZE (outer_mode) - 1) / UNITS_PER_WORD
== (GET_MODE_SIZE (inner_mode) - 1) / UNITS_PER_WORD))
return NULL;
-#endif
/* Since we don't attempt to handle paradoxical subregs, we can just
call into simplify_subreg, which will handle all remaining checks
diff --git a/gcc/reload1.c b/gcc/reload1.c
index e80ebf9..c673abc 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2866,7 +2866,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
if (MEM_P (new_rtx)
&& ((x_size < new_size
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
/* On these machines, combine can create rtl of the form
(set (subreg:m1 (reg:m2 R) 0) ...)
where m1 < m2, and expects something interesting to
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 2071b6b..a203918 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4034,7 +4034,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
just return the mode mask. Those tests will then be false. */
return nonzero;
-#ifndef WORD_REGISTER_OPERATIONS
/* If MODE is wider than X, but both are a single word for both the host
and target machines, we can compute this from which bits of the
object might be nonzero in its own mode, taking into account the fact
@@ -4042,7 +4041,8 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
causes the high-order bits to become undefined. So they are
not known to be zero. */
- if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
+ if (!WORD_REGISTER_OPERATIONS && GET_MODE (x) != VOIDmode
+ && GET_MODE (x) != mode
&& GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD
&& GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
&& GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x)))
@@ -4052,7 +4052,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
return nonzero;
}
-#endif
code = GET_CODE (x);
switch (code)
@@ -4324,7 +4323,7 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
-#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
+#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
@@ -4544,12 +4543,12 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x)))
{
-#ifndef WORD_REGISTER_OPERATIONS
/* If this machine does not do all register operations on the entire
register and MODE is wider than the mode of X, we can say nothing
at all about the high-order bits. */
- return 1;
-#else
+ if (!WORD_REGISTER_OPERATIONS)
+ return 1;
+
/* Likewise on machines that do, if the mode of the object is smaller
than a word and loads of that size don't sign extend, we can say
nothing about the high order bits. */
@@ -4559,7 +4558,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
#endif
)
return 1;
-#endif
}
switch (code)
@@ -4638,7 +4636,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
- bitwidth)));
}
-#ifdef WORD_REGISTER_OPERATIONS
#ifdef LOAD_EXTEND_OP
/* For paradoxical SUBREGs on machines where all register operations
affect the entire register, just look inside. Note that we are
@@ -4650,13 +4647,12 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
then we lose all sign bit copies that existed before the store
to the stack. */
- if (paradoxical_subreg_p (x)
+ if (WORD_REGISTER_OPERATIONS && paradoxical_subreg_p (x)
&& LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
&& MEM_P (SUBREG_REG (x)))
return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
#endif
-#endif
break;
case SIGN_EXTRACT:
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index ca8310d..b6aa4bc 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -677,9 +677,7 @@ simplify_truncation (machine_mode mode, rtx op,
the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
(op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
if (1
-#ifdef WORD_REGISTER_OPERATIONS
- && precision >= BITS_PER_WORD
-#endif
+ && (!WORD_REGISTER_OPERATIONS || precision >= BITS_PER_WORD)
&& (GET_CODE (op) == PLUS
|| GET_CODE (op) == MINUS
|| GET_CODE (op) == MULT))
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 7/7] always define WORD_REGISTER_OPERATIONS
2015-07-06 12:12 ` [PATCH 7/7] always define WORD_REGISTER_OPERATIONS tbsaunde+gcc
@ 2015-07-06 14:04 ` Segher Boessenkool
0 siblings, 0 replies; 11+ messages in thread
From: Segher Boessenkool @ 2015-07-06 14:04 UTC (permalink / raw)
To: tbsaunde+gcc; +Cc: gcc-patches
Hi Trevor,
On Mon, Jul 06, 2015 at 08:11:30AM -0400, tbsaunde+gcc@tbsaunde.org wrote:
> * defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
> * config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
> * config/arc/arc.h: Likewise.
> * config/arm/arm.h: Likewise.
> * config/bfin/bfin.h: Likewise.
> * config/epiphany/epiphany.h: Likewise.
> * config/frv/frv.h: Likewise.
> * config/ia64/ia64.h: Likewise.
> * config/iq2000/iq2000.h: Likewise.
> * config/lm32/lm32.h: Likewise.
> * config/m32r/m32r.h: Likewise.
> * config/mcore/mcore.h: Likewise.
> * config/mep/mep.h: Likewise.
> * config/microblaze/microblaze.h: Likewise.
> * config/mips/mips.h: Likewise.
> * config/mmix/mmix.h:
> * config/mn10300/mn10300.h:
> * config/nds32/nds32.h:
> * config/nios2/nios2.h:
> * config/pa/pa.h:
> * config/rl78/rl78.h:
> * config/sh/sh.h:
> * config/sparc/sparc.h:
> * config/stormy16/stormy16.h (enum reg_class):
> * config/tilegx/tilegx.h:
> * config/tilepro/tilepro.h:
> * config/v850/v850.h:
> * config/xtensa/xtensa.h:
> * doc/tm.texi: Regenerate.
Something went wrong here ;-)
> @@ -12072,10 +12071,9 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
> they no longer have defined values and the meaning of
> the code has been changed. */
> && (0
> -#ifdef WORD_REGISTER_OPERATIONS
> - || (mode_width > GET_MODE_PRECISION (tmode)
> + || (!WORD_REGISTER_OPERATIONS
> + && mode_width > GET_MODE_PRECISION (tmode)
> && mode_width <= BITS_PER_WORD)
> -#endif
> || (mode_width <= GET_MODE_PRECISION (tmode)
> && subreg_lowpart_p (XEXP (op0, 0))))
> && CONST_INT_P (XEXP (op0, 1))
Please get rid of that "0 ||" now.
I think the ! is wrong here?
The rest of the combine changes look good.
> @@ -6114,13 +6112,12 @@ store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
> highest_pow2_factor (offset));
> }
>
> -#ifdef WORD_REGISTER_OPERATIONS
> /* If this initializes a field that is smaller than a
> word, at the start of a word, try to widen it to a full
> word. This special case allows us to output C++ member
> function initializations in a form that the optimizers
> can understand. */
> - if (REG_P (target)
> + if (WORD_REGISTER_OPERATIONS && REG_P (target)
> && bitsize < BITS_PER_WORD
> && bitpos % BITS_PER_WORD == 0
> && GET_MODE_CLASS (mode) == MODE_INT
Put that first && on a new line as well? Similar many times more.
Segher
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/7] always define SHORT_IMMEDIATES_SIGN_EXTEND
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
` (3 preceding siblings ...)
2015-07-06 12:12 ` [PATCH 7/7] always define WORD_REGISTER_OPERATIONS tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 2/7] remove #if for HAVE_cc0 in combine.c tbsaunde+gcc
2015-07-06 12:12 ` [PATCH 5/7] always define AUTO_INC_DEC tbsaunde+gcc
6 siblings, 0 replies; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (update_rsp_from_reg_equal): Don't check if
SHORT_IMMEDIATES_SIGN_EXTEND is defined.
(reg_nonzero_bits_for_combine): Likewise.
* config/alpha/alpha.h: Define SHORT_IMMEDIATES_SIGN_EXTEND to
1.
* config/frv/frv.h: Likewise.
* config/lm32/lm32.h: Likewise.
* config/mep/mep.h: Likewise.
* config/mips/mips.h: Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/sh/sh.h: Likewise.
* config/tilegx/tilegx.h (enum reg_class): Likewise.
* config/tilepro/tilepro.h: Likewise.
* defaults.h: Add default for SHORT_IMMEDIATES_SIGN_EXTEND.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in: Adjust.
* rtlanal.c (nonzero_bits1): Likewise.
---
gcc/combine.c | 21 ++++++++++-----------
gcc/config/alpha/alpha.h | 2 +-
gcc/config/frv/frv.h | 2 +-
gcc/config/lm32/lm32.h | 2 +-
gcc/config/mep/mep.h | 2 +-
gcc/config/mips/mips.h | 2 +-
gcc/config/rs6000/rs6000.h | 2 +-
gcc/config/sh/sh.h | 2 +-
gcc/config/tilegx/tilegx.h | 2 +-
gcc/config/tilepro/tilepro.h | 2 +-
gcc/defaults.h | 4 ++++
gcc/doc/tm.texi | 2 +-
gcc/doc/tm.texi.in | 2 +-
gcc/rtlanal.c | 4 +---
14 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index a02e755..6935934 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1630,7 +1630,6 @@ setup_incoming_promotions (rtx_insn *first)
}
}
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
/* If MODE has a precision lower than PREC and SRC is a non-negative constant
that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
because some machines (maybe most) will actually do the sign-extension and
@@ -1650,7 +1649,6 @@ sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
return src;
}
-#endif
/* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
and SET. */
@@ -1667,11 +1665,12 @@ update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
if (reg_equal_note)
reg_equal = XEXP (reg_equal_note, 0);
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
- src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
- if (reg_equal)
- reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
-#endif
+ if (SHORT_IMMEDIATES_SIGN_EXTEND)
+ {
+ src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
+ if (reg_equal)
+ reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
+ }
/* Don't call nonzero_bits if it cannot change anything. */
if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
@@ -9818,10 +9817,10 @@ reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode,
if (tem)
{
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
- tem = sign_extend_short_imm (tem, GET_MODE (x),
- GET_MODE_PRECISION (mode));
-#endif
+ if (SHORT_IMMEDIATES_SIGN_EXTEND)
+ tem = sign_extend_short_imm (tem, GET_MODE (x),
+ GET_MODE_PRECISION (mode));
+
return tem;
}
else if (nonzero_sign_valid && rsp->nonzero_bits)
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 8d2ab23..c39f103 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -897,7 +897,7 @@ do { \
#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
/* Define if loading short immediate values into registers sign extends. */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
is done just by pretending it is already truncated. */
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 2d4cbdd..a96f201b 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1899,7 +1899,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE)
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Define if loading short immediate values into registers sign extends. */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
/* The maximum number of bytes that a single instruction can move quickly from
memory to memory. */
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index d284703..9872860 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -525,7 +525,7 @@ do { \
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
#define MOVE_MAX UNITS_PER_WORD
#define MAX_MOVE_MAX 4
diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h
index 861189d..8fee273 100644
--- a/gcc/config/mep/mep.h
+++ b/gcc/config/mep/mep.h
@@ -765,7 +765,7 @@ typedef struct
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
#define MOVE_MAX 4
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index bceef31..33469be 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1626,7 +1626,7 @@ FP_ASM_SPEC "\
#define POINTERS_EXTEND_UNSIGNED false
/* Define if loading short immediate values into registers sign extends. */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
/* The [d]clz instructions have the natural values at 0. */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ef8ff38..3bd2048 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2046,7 +2046,7 @@ do { \
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define if loading short immediate values into registers sign extends. */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
\f
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
is done just by pretending it is already truncated. */
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 3078880..c4947a6 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1827,7 +1827,7 @@ struct sh_args {
: (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
/* Define if loading short immediate values into registers sign extends. */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h
index 5fa10b3..7c3995a 100644
--- a/gcc/config/tilegx/tilegx.h
+++ b/gcc/config/tilegx/tilegx.h
@@ -386,7 +386,7 @@ enum reg_class
#define SHIFT_COUNT_TRUNCATED 0
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
/* We represent all SI values as sign-extended DI values in
registers. */
diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h
index f2b7b16..970135a 100644
--- a/gcc/config/tilepro/tilepro.h
+++ b/gcc/config/tilepro/tilepro.h
@@ -346,7 +346,7 @@ enum reg_class
#define SHIFT_COUNT_TRUNCATED 1
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
diff --git a/gcc/defaults.h b/gcc/defaults.h
index ea10eb9..9dc59d2 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1265,6 +1265,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_SUPPORTS_WIDE_INT 0
#endif
+#ifndef SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 0
+#endif
+
#ifdef GCC_INSN_FLAGS_H
/* Dependent default target macro definitions
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index a16cd92..620fc2a 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10410,7 +10410,7 @@ is larger then @var{mem_mode} but still smaller than @code{word_mode}.
@end defmac
@defmac SHORT_IMMEDIATES_SIGN_EXTEND
-Define this macro if loading short immediate values into registers sign
+Define this macro to 1 if loading short immediate values into registers sign
extends.
@end defmac
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 93fb41c..59aa589 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7534,7 +7534,7 @@ is larger then @var{mem_mode} but still smaller than @code{word_mode}.
@end defmac
@defmac SHORT_IMMEDIATES_SIGN_EXTEND
-Define this macro if loading short immediate values into registers sign
+Define this macro to 1 if loading short immediate values into registers sign
extends.
@end defmac
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 86b3b62..2071b6b 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4108,14 +4108,12 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
}
case CONST_INT:
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
/* If X is negative in MODE, sign-extend the value. */
- if (INTVAL (x) > 0
+ if (SHORT_IMMEDIATES_SIGN_EXTEND && INTVAL (x) > 0
&& mode_width < BITS_PER_WORD
&& (UINTVAL (x) & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
!= 0)
return UINTVAL (x) | (HOST_WIDE_INT_M1U << mode_width);
-#endif
return UINTVAL (x);
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 2/7] remove #if for HAVE_cc0 in combine.c
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
` (4 preceding siblings ...)
2015-07-06 12:12 ` [PATCH 3/7] always define SHORT_IMMEDIATES_SIGN_EXTEND tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
2015-07-06 14:37 ` Segher Boessenkool
2015-07-06 12:12 ` [PATCH 5/7] always define AUTO_INC_DEC tbsaunde+gcc
6 siblings, 1 reply; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (do_SUBST_MODE): Don't check the value of HAVE_cc0
with the preprocessor.
(combine_instructions): Likewise.
(try_combine): Likewise.
(subst): Likewise.
(distribute_notes): Likewise.
---
gcc/combine.c | 59 ++++++++++++++++++++++++-----------------------------------
1 file changed, 24 insertions(+), 35 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index 8b1e9f4..a02e755 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -825,7 +825,6 @@ do_SUBST_MODE (rtx *into, machine_mode newval)
#define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
-#if !HAVE_cc0
/* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
static void
@@ -851,7 +850,6 @@ do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
}
#define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
-#endif
\f
/* Subroutine of try_combine. Determine whether the replacement patterns
NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
@@ -1142,9 +1140,7 @@ static int
combine_instructions (rtx_insn *f, unsigned int nregs)
{
rtx_insn *insn, *next;
-#if HAVE_cc0
rtx_insn *prev;
-#endif
struct insn_link *links, *nextlinks;
rtx_insn *first;
basic_block last_bb;
@@ -1319,7 +1315,6 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
}
}
-#if HAVE_cc0
/* Try to combine a jump insn that uses CC0
with a preceding insn that sets CC0, and maybe with its
logical predecessor as well.
@@ -1327,7 +1322,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
We need this special code because data flow connections
via CC0 do not get entered in LOG_LINKS. */
- if (JUMP_P (insn)
+ if (HAVE_cc0 && JUMP_P (insn)
&& (prev = prev_nonnote_insn (insn)) != 0
&& NONJUMP_INSN_P (prev)
&& sets_cc0_p (PATTERN (prev)))
@@ -1345,7 +1340,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
}
/* Do the same for an insn that explicitly references CC0. */
- if (NONJUMP_INSN_P (insn)
+ if (HAVE_cc0 && NONJUMP_INSN_P (insn)
&& (prev = prev_nonnote_insn (insn)) != 0
&& NONJUMP_INSN_P (prev)
&& sets_cc0_p (PATTERN (prev))
@@ -1367,18 +1362,20 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
/* Finally, see if any of the insns that this insn links to
explicitly references CC0. If so, try this insn, that insn,
and its predecessor if it sets CC0. */
- FOR_EACH_LOG_LINK (links, insn)
- if (NONJUMP_INSN_P (links->insn)
- && GET_CODE (PATTERN (links->insn)) == SET
- && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
- && (prev = prev_nonnote_insn (links->insn)) != 0
- && NONJUMP_INSN_P (prev)
- && sets_cc0_p (PATTERN (prev))
- && (next = try_combine (insn, links->insn,
- prev, NULL, &new_direct_jump_p,
- last_combined_insn)) != 0)
- goto retry;
-#endif
+ if (HAVE_cc0)
+ {
+ FOR_EACH_LOG_LINK (links, insn)
+ if (NONJUMP_INSN_P (links->insn)
+ && GET_CODE (PATTERN (links->insn)) == SET
+ && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
+ && (prev = prev_nonnote_insn (links->insn)) != 0
+ && NONJUMP_INSN_P (prev)
+ && sets_cc0_p (PATTERN (prev))
+ && (next = try_combine (insn, links->insn,
+ prev, NULL, &new_direct_jump_p,
+ last_combined_insn)) != 0)
+ goto retry;
+ }
/* Try combining an insn with two different insns whose results it
uses. */
@@ -2546,7 +2543,6 @@ is_parallel_of_n_reg_sets (rtx pat, int n)
return true;
}
-#if !HAVE_cc0
/* Return whether INSN, a PARALLEL of N register SETs (and maybe some
CLOBBERs), can be split into individual SETs in that order, without
changing semantics. */
@@ -2573,7 +2569,6 @@ can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
return true;
}
-#endif
/* Try to combine the insns I0, I1 and I2 into I3.
Here I0, I1 and I2 appear earlier than I3.
@@ -2920,7 +2915,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
}
}
-#if !HAVE_cc0
/* If we have no I1 and I2 looks like:
(parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
(set Y OP)])
@@ -2934,7 +2928,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
This undoes a previous combination and allows us to match a branch-and-
decrement insn. */
- if (i1 == 0
+ if (!HAVE_cc0 && i1 == 0
&& is_parallel_of_n_reg_sets (PATTERN (i2), 2)
&& (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
== MODE_CC)
@@ -2966,7 +2960,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
/* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
make those two SETs separate I1 and I2 insns, and make an I0 that is
the original I1. */
- if (i0 == 0
+ if (!HAVE_cc0 && i0 == 0
&& is_parallel_of_n_reg_sets (PATTERN (i2), 2)
&& can_split_parallel_of_n_reg_sets (i2, 2)
&& !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
@@ -2987,7 +2981,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
}
-#endif
/* Verify that I2 and I1 are valid for combining. */
if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src)
@@ -5382,10 +5375,8 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
&& ! (code == SUBREG
&& MODES_TIEABLE_P (GET_MODE (x),
GET_MODE (SUBREG_REG (to))))
-#if HAVE_cc0
- && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
-#endif
- )
+ && (!HAVE_cc0 || (! (code == SET && i == 1
+ && XEXP (x, 0) == cc0_rtx))))
return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
if (code == SUBREG
@@ -13938,12 +13929,10 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
if (set != 0 && ! side_effects_p (SET_SRC (set))
&& rtx_equal_p (XEXP (note, 0), inner_dest)
-#if HAVE_cc0
- && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
- || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
- && sets_cc0_p (PATTERN (cc0_setter)) > 0))
-#endif
- )
+ && (!HAVE_cc0
+ || (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
+ || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
+ && sets_cc0_p (PATTERN (cc0_setter)) > 0))))
{
/* Move the notes and links of TEM_INSN elsewhere.
This might delete other dead insns recursively.
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/7] remove #if for HAVE_cc0 in combine.c
2015-07-06 12:12 ` [PATCH 2/7] remove #if for HAVE_cc0 in combine.c tbsaunde+gcc
@ 2015-07-06 14:37 ` Segher Boessenkool
0 siblings, 0 replies; 11+ messages in thread
From: Segher Boessenkool @ 2015-07-06 14:37 UTC (permalink / raw)
To: tbsaunde+gcc; +Cc: gcc-patches
On Mon, Jul 06, 2015 at 08:11:25AM -0400, tbsaunde+gcc@tbsaunde.org wrote:
> @@ -1327,7 +1322,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
> We need this special code because data flow connections
> via CC0 do not get entered in LOG_LINKS. */
>
> - if (JUMP_P (insn)
> + if (HAVE_cc0 && JUMP_P (insn)
> && (prev = prev_nonnote_insn (insn)) != 0
> && NONJUMP_INSN_P (prev)
> && sets_cc0_p (PATTERN (prev)))
As before (in 6/6), please respect formatting rules.
> @@ -5382,10 +5375,8 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
> && ! (code == SUBREG
> && MODES_TIEABLE_P (GET_MODE (x),
> GET_MODE (SUBREG_REG (to))))
> -#if HAVE_cc0
> - && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
> -#endif
> - )
> + && (!HAVE_cc0 || (! (code == SET && i == 1
> + && XEXP (x, 0) == cc0_rtx))))
Esp. for things like this :-)
> -#if HAVE_cc0
> - && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
> - || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
> - && sets_cc0_p (PATTERN (cc0_setter)) > 0))
> -#endif
> - )
> + && (!HAVE_cc0
> + || (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
> + || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
> + && sets_cc0_p (PATTERN (cc0_setter)) > 0))))
Line too long now. This really wants a rewrite anyway, assignment in
conditionals, ewww. And it will only look worse if you just wrap the
lines.
But please fix the other formatting problems.
Segher
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 5/7] always define AUTO_INC_DEC
2015-07-06 12:11 [PATCH 0/7] more ifdef removal tbsaunde+gcc
` (5 preceding siblings ...)
2015-07-06 12:12 ` [PATCH 2/7] remove #if for HAVE_cc0 in combine.c tbsaunde+gcc
@ 2015-07-06 12:12 ` tbsaunde+gcc
6 siblings, 0 replies; 11+ messages in thread
From: tbsaunde+gcc @ 2015-07-06 12:12 UTC (permalink / raw)
To: gcc-patches
From: Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
gcc/ChangeLog:
2015-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* rtl.h: Always define AUTO_INC_DEC.
* auto-inc-dec.c (pass_inc_dec::execute): Adjust.
* combine.c (combine_instructions): Likewise.
(can_combine_p): Likewise.
(try_combine): Likewise.
* emit-rtl.c (try_split): Likewise.
* loop-invariant.c (calculate_loop_reg_pressure): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* lra.c (update_inc_notes): Likewise.
* recog.c (asm_operand_ok): Likewise.
(constrain_operands): Likewise.
* regrename.c (scan_rtx_address): Likewise.
* reload.c (update_auto_inc_notes): Likewise.
(find_equiv_reg): Likewise.
* reload1.c (reload): Likewise.
(reload_as_needed): Likewise.
(choose_reload_regs): Likewise.
(emit_input_reload_insns): Likewise.
(delete_output_reload): Likewise.
* sched-deps.c (init_insn_reg_pressure_info): Likewise.
* valtrack.c (cleanup_auto_inc_dec): Likewise.
---
gcc/auto-inc-dec.c | 6 +++---
gcc/combine.c | 10 +++++-----
gcc/emit-rtl.c | 4 ++--
gcc/loop-invariant.c | 2 +-
gcc/lower-subreg.c | 4 ++--
gcc/lra.c | 4 ++--
gcc/recog.c | 8 ++++----
gcc/regrename.c | 2 +-
gcc/reload.c | 6 +++---
gcc/reload1.c | 18 +++++++++---------
gcc/rtl.h | 6 ++++--
gcc/sched-deps.c | 2 +-
gcc/valtrack.c | 2 +-
13 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/gcc/auto-inc-dec.c b/gcc/auto-inc-dec.c
index df52229..dd183ee 100644
--- a/gcc/auto-inc-dec.c
+++ b/gcc/auto-inc-dec.c
@@ -123,7 +123,7 @@ along with GCC; see the file COPYING3. If not see
before the ref or +c if the increment was after the ref, then if we
can do the combination but switch the pre/post bit. */
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
enum form
{
@@ -1477,7 +1477,7 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
return (optimize > 0 && flag_auto_inc_dec);
#else
return false;
@@ -1492,7 +1492,7 @@ public:
unsigned int
pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED)
{
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
basic_block bb;
int max_reg = max_reg_num ();
diff --git a/gcc/combine.c b/gcc/combine.c
index da5c335..346bdff 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1204,7 +1204,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
FOR_BB_INSNS (this_basic_block, insn)
if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
{
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
rtx links;
#endif
@@ -1215,7 +1215,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
insn);
record_dead_and_set_regs (insn);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
if (REG_NOTE_KIND (links) == REG_INC)
set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
@@ -1798,7 +1798,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
const_rtx set = 0;
rtx src, dest;
rtx_insn *p;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
rtx link;
#endif
bool all_adjacent = true;
@@ -2079,7 +2079,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
Also insist that I3 not be a jump; if it were one
and the incremented register were spilled, we would lose. */
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_INC
&& (JUMP_P (i3)
@@ -3045,7 +3045,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
|| GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
/* It's not the exception. */
#endif
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
{
rtx link;
for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index 80c0adb..eb44066 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -3594,7 +3594,7 @@ prev_cc0_setter (rtx_insn *insn)
return insn;
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* Find a RTX_AUTOINC class rtx which matches DATA. */
static int
@@ -3782,7 +3782,7 @@ try_split (rtx pat, rtx_insn *trial, int last)
}
break;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
case REG_INC:
for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
{
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index d3a7439..1285c66 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1998,7 +1998,7 @@ calculate_loop_reg_pressure (void)
note_stores (PATTERN (insn), mark_reg_store, NULL);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_INC)
mark_reg_store (XEXP (link, 0), NULL_RTX, NULL);
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index bacb65f..a57ce43 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -948,7 +948,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
reg = gen_reg_rtx (orig_mode);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
{
rtx move = emit_move_insn (reg, src);
if (MEM_P (src))
@@ -1051,7 +1051,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0);
minsn = emit_move_insn (real_dest, mdest);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
if (MEM_P (real_dest)
&& !(resolve_reg_p (real_dest) || resolve_subreg_p (real_dest)))
{
diff --git a/gcc/lra.c b/gcc/lra.c
index bdd8e3c..0bf822f 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -2093,7 +2093,7 @@ has_nonexceptional_receiver (void)
return false;
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* Process recursively X of INSN and add REG_INC notes if necessary. */
static void
@@ -2148,7 +2148,7 @@ update_inc_notes (void)
else
pnote = &XEXP (*pnote, 1);
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
add_auto_inc_notes (insn, PATTERN (insn));
#endif
}
diff --git a/gcc/recog.c b/gcc/recog.c
index 3fbfe07..2e8be6a 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1720,7 +1720,7 @@ int
asm_operand_ok (rtx op, const char *constraint, const char **constraints)
{
int result = 0;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
bool incdec_ok = false;
#endif
@@ -1790,7 +1790,7 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
result = 1;
break;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
case '<':
case '>':
/* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
@@ -1844,7 +1844,7 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
return 0;
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* For operands without < or > constraints reject side-effects. */
if (!incdec_ok && result && MEM_P (op))
switch (GET_CODE (XEXP (op, 0)))
@@ -2822,7 +2822,7 @@ constrain_operands (int strict, alternative_mask alternatives)
= recog_data.operand[funny_match[funny_match_index].this_op];
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* For operands without < or > constraints reject side-effects. */
if (recog_data.is_asm)
{
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 2e08669..0fce77e 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1312,7 +1312,7 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
case PRE_INC:
case PRE_DEC:
case PRE_MODIFY:
-#ifndef AUTO_INC_DEC
+#if !AUTO_INC_DEC
/* If the target doesn't claim to handle autoinc, this must be
something special, like a stack push. Kill this chain. */
action = mark_all_read;
diff --git a/gcc/reload.c b/gcc/reload.c
index 4bc996f..3323816 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -5454,7 +5454,7 @@ static void
update_auto_inc_notes (rtx_insn *insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED,
int reloadnum ATTRIBUTE_UNUSED)
{
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
rtx link;
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
@@ -7088,7 +7088,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
}
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* If this insn auto-increments or auto-decrements
either regno or valueno, return 0 now.
If GOAL is a memory ref and its address is not constant,
@@ -7175,7 +7175,7 @@ find_inc_amount (rtx x, rtx inced)
/* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
REG_INC note in insn INSN. REGNO must refer to a hard register. */
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
static int
reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
rtx insn)
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 57837a1..f05596f 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -424,7 +424,7 @@ static void delete_output_reload (rtx_insn *, int, int, rtx);
static void delete_address_reloads (rtx_insn *, rtx_insn *);
static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
static void inc_for_reload (rtx, rtx, rtx, int);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
static void add_auto_inc_notes (rtx_insn *, rtx);
#endif
static void substitute (rtx *, const_rtx, rtx);
@@ -1257,7 +1257,7 @@ reload (rtx_insn *first, int global)
pnote = &XEXP (*pnote, 1);
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
add_auto_inc_notes (insn, PATTERN (insn));
#endif
@@ -4585,7 +4585,7 @@ static void
reload_as_needed (int live_known)
{
struct insn_chain *chain;
-#if defined (AUTO_INC_DEC)
+#if AUTO_INC_DEC
int i;
#endif
rtx_note *marker;
@@ -4608,7 +4608,7 @@ reload_as_needed (int live_known)
rtx_insn *prev = 0;
rtx_insn *insn = chain->insn;
rtx_insn *old_next = NEXT_INSN (insn);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
rtx_insn *old_prev = PREV_INSN (insn);
#endif
@@ -4753,7 +4753,7 @@ reload_as_needed (int live_known)
if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
note_stores (PATTERN (x), forget_old_reloads_1, NULL);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
/* Likewise for regs altered by auto-increment in this insn.
REG_INC notes have been changed by reloading:
find_reloads_address_1 records substitutions for them,
@@ -6610,7 +6610,7 @@ choose_reload_regs (struct insn_chain *chain)
}
mode = GET_MODE (rld[r].in_reg);
}
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
&& REG_P (XEXP (rld[r].in_reg, 0)))
{
@@ -7401,7 +7401,7 @@ emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
is ill-formed and we must reject this optimization. */
extract_insn (temp);
if (constrain_operands (1, get_enabled_alternatives (temp))
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
&& ! find_reg_note (temp, REG_INC, reloadreg)
#endif
)
@@ -8874,7 +8874,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
continue;
if (MEM_P (reg2) || reload_override_in[k])
reg2 = rld[k].in_reg;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
if (rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
#endif
@@ -9270,7 +9270,7 @@ inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
}
}
\f
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
static void
add_auto_inc_notes (rtx_insn *insn, rtx x)
{
diff --git a/gcc/rtl.h b/gcc/rtl.h
index d74c20f..3b9546a 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -2555,13 +2555,15 @@ do { \
|| defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT) \
|| defined (HAVE_PRE_MODIFY_DISP) || defined (HAVE_POST_MODIFY_DISP) \
|| defined (HAVE_PRE_MODIFY_REG) || defined (HAVE_POST_MODIFY_REG))
-#define AUTO_INC_DEC
+#define AUTO_INC_DEC 1
+#else
+#define AUTO_INC_DEC 0
#endif
/* Define a macro to look for REG_INC notes,
but save time on machines where they never exist. */
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
#define FIND_REG_INC_NOTE(INSN, REG) \
((REG) != NULL_RTX && REG_P ((REG)) \
? find_regno_note ((INSN), REG_INC, REGNO (REG)) \
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index b62dc00..a2ab8e5 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2228,7 +2228,7 @@ init_insn_reg_pressure_info (rtx_insn *insn)
note_stores (PATTERN (insn), mark_insn_reg_store, insn);
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_INC)
mark_insn_reg_store (XEXP (link, 0), NULL_RTX, insn);
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 80a0043..8646a63 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -57,7 +57,7 @@ static rtx
cleanup_auto_inc_dec (rtx src, machine_mode mem_mode ATTRIBUTE_UNUSED)
{
rtx x = src;
-#ifdef AUTO_INC_DEC
+#if AUTO_INC_DEC
const RTX_CODE code = GET_CODE (x);
int i;
const char *fmt;
--
2.4.0
^ permalink raw reply [flat|nested] 11+ messages in thread