From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8516 invoked by alias); 25 Sep 2015 07:59:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 8504 invoked by uid 89); 25 Sep 2015 07:59:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Sep 2015 07:59:43 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-33-6xj0SJurSJCVAXC5x8uf3g-1; Fri, 25 Sep 2015 08:59:38 +0100 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 25 Sep 2015 08:59:38 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, richard.earnshaw@arm.com, kyrtka01@arm.com, ramana.radhakrishnan@arm.com Subject: [Patch 0/2 ARM/AArch64] Add a new Cortex-A53 scheduling model Date: Fri, 25 Sep 2015 08:20:00 -0000 Message-Id: <1443167973-37806-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 6xj0SJurSJCVAXC5x8uf3g-1 Content-Type: multipart/mixed; boundary="------------2.2.0.1.gd394abb.dirty" X-IsSubscribed: yes X-SW-Source: 2015-09/txt/msg01913.txt.bz2 This is a multi-part message in MIME format. --------------2.2.0.1.gd394abb.dirty Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 1433 Hi, This two patch series updates our scheduling model for the Cortex-A53 processor. Patch 1/2 splits out the "shift_imm" type attribute used by the AArch64 target to give us two types - rotate_imm and shift_imm. Patch 2/2 introduces the new scheduling model. I've bootstrapped and tested the patches in series and individually on both arm-none-linux-gnueabihf and aarch64-none-linux-gnu targets, and I've checked the performance against a set of popular benchmark suites to show a benefit. OK for trunk? Thanks, James --- [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attribute 2015-09-25 James Greenhalgh * config/arm/types.md (type): Add rotate_imm. * config/aarch64/aarch64.md (*ror3_insn): Split out the ROR immediate case. (*rorsi3_insn_uxtw): Likewise. * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm. * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm. [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling model 2015-09-25 James Greenhalgh * config/arm/aarch-common-protos.h (aarch_accumulator_forwarding): New. (aarch_forward_to_shift_is_not_shifted_reg): Likewise. * config/arm/aarch-common.c (aarch_accumulator_forwarding): New. (aarch_forward_to_shift_is_not_shifted_reg): Liekwise. * config/arm/cortex-a53.md: Rewrite.= --------------2.2.0.1.gd394abb.dirty--