From: charles.baylis@linaro.org
To: kyrylo.tkachov@arm.com, Ramana.Radhakrishnan@arm.com,
alan.lawrence@arm.com
Cc: gcc-patches@gcc.gnu.org
Subject: [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages
Date: Wed, 07 Oct 2015 00:00:00 -0000 [thread overview]
Message-ID: <1444175989-24944-1-git-send-email-charles.baylis@linaro.org> (raw)
From: Charles Baylis <charles.baylis@linaro.org>
This patch series fixes up the error messages for single lane vector
load/stores, similarly to AArch64.
make check on arm-linux-gnueabihf/qemu completes with no new regressions.
Changes since the last version:
. removed the duplicate arm_neon_lane_bounds function
. resolved conflicts with other NEON work
. whitespace clean up
Charles Baylis (3):
[ARM] PR63870 Add qualifiers for NEON builtins
[ARM] PR63870 Mark lane indices of vldN/vstN with appropriate
qualifier
[ARM] PR63870 Enable test cases for ARM
gcc/config/arm/arm-builtins.c | 50 ++++++++++++++--------
gcc/config/arm/arm.c | 1 +
gcc/config/arm/arm.h | 3 ++
gcc/config/arm/neon.md | 49 +++++++++++----------
.../advsimd-intrinsics/vld2_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 5 +--
148 files changed, 350 insertions(+), 473 deletions(-)
--
1.9.1
next reply other threads:[~2015-10-07 0:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-07 0:00 charles.baylis [this message]
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
2015-10-12 10:50 ` Alan Lawrence
2015-10-07 0:00 ` [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins charles.baylis
2015-10-12 10:58 ` Alan Lawrence
2015-10-14 22:02 ` Charles Baylis
2015-10-19 16:59 ` Alan Lawrence
2015-10-07 0:01 ` [PATCH 3/3] [ARM] PR63870 Enable test cases charles.baylis
2015-10-09 14:04 ` [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages Charles Baylis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1444175989-24944-1-git-send-email-charles.baylis@linaro.org \
--to=charles.baylis@linaro.org \
--cc=Ramana.Radhakrishnan@arm.com \
--cc=alan.lawrence@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=kyrylo.tkachov@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).