From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1099 invoked by alias); 8 Nov 2015 00:27:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 932 invoked by uid 89); 8 Nov 2015 00:27:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f170.google.com Received: from mail-wi0-f170.google.com (HELO mail-wi0-f170.google.com) (209.85.212.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sun, 08 Nov 2015 00:27:04 +0000 Received: by wikq8 with SMTP id q8so49871488wik.1 for ; Sat, 07 Nov 2015 16:27:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=VKIGgsKuIJvV5ditZf6btfy6a3xmdzW+SjQTUqZPh2E=; b=Mj6gH9XSSZhsllXJwNQ6gGCzUxgougorKWh9Kixu4o4xP0j/E0bGC63VWjqsRmiIlf Xcp7575JGwv4veZisXZV0Y2O24riek17DL9G3SoztdsM2Mj7NF9XQEhvP7IJ/y2x7nYH dQ+OTMWRN5N4f9BTRkBs+M82lFLSww0pA99YNTZamo8atyHPIXETuBpJvdl/Bn4Mr9HQ Bsl9CYj3PClGG7kSQPDgaSH37e+ipBos65TLOJ/+PZhYbJkcQ2i/miwLkZsv4G5Dk5rU 02icMsbnVUzvhHptXUCeueE2iAQclPp9nKpSOTjURbxFeRNdD+2AvRd5nUc/nCGN7jY9 aTJg== X-Gm-Message-State: ALoCoQn9qjekNzELtYg04FNCT1u94AKeJT+9dSaTLmVato4ntaOOPHj4SdiKB/JelTwM+abJkRmG X-Received: by 10.194.105.38 with SMTP id gj6mr21127881wjb.130.1446942421243; Sat, 07 Nov 2015 16:27:01 -0800 (PST) Received: from localhost.localdomain (cpc10-cmbg17-2-0-cust610.5-4.cable.virginm.net. [86.30.42.99]) by smtp.gmail.com with ESMTPSA id e9sm7480979wjw.8.2015.11.07.16.27.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 07 Nov 2015 16:27:00 -0800 (PST) From: charles.baylis@linaro.org To: Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com, alan.lawrence@arm.com Cc: rearnsha@arm.com, gcc-patches@gcc.gnu.org Subject: [PATCH v3 0/4] [ARM] PR63870 vldN_lane/vstN_lane error messages Date: Sun, 08 Nov 2015 00:27:00 -0000 Message-Id: <1446942404-11561-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes X-SW-Source: 2015-11/txt/msg00829.txt.bz2 From: Charles Baylis Previous discussion: https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00657.html This is a minor update to the previous patch set, fixing one coding style issue in the first patch, and adding a fourth patch for which there are two options, described below. [ARM] PR63870 Add qualifiers for NEON builtins [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier [ARM] PR63870 Add test cases These two patches are alternate options. Alan suggested removing the error checks at assembly time, since the user-supplied lane number is always be checked earlier. I thought it might be better to catch this case as an internal error, to guard against future bugs.. If we don't use the internal error, then the assembler will catch use of invalid lane numbers. Not sure which is prefered, so both options are presented. Either one can be applied: [ARM] PR63870 Use internal_error() for invalid lane numbers [ARM] PR63870 Remove error for invalid lane numbers Passes make check for arm-unknown-linux-gnueabihf and armeb-unknown-linux-gnueabihf with no regressions. As mentioned in the last thread, the new *_f16 tests fail on armeb-* due to unrelated problems with half float moves. OK for trunk? I prefer patch 4a, but will commit 4b if that is prefered. gcc/config/arm/arm-builtins.c | 52 +++++++----- gcc/config/arm/arm.c | 1 + gcc/config/arm/arm.h | 3 + gcc/config/arm/neon.md | 97 ++++++++-------------- .../advsimd-intrinsics/vld2_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4_lane_u8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_f16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 5 +- .../advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 5 +- 148 files changed, 358 insertions(+), 515 deletions(-) -- 1.9.1