[PATCH 2/6] [ARC] Fix FPX/FPUDA code gen when compiling for big-endian.

[Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>]

OK to apply?
Claudiu

gcc/
2016-04-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_process_double_reg_moves): Fix for
	big-endian compilation.
	* config/arc/arc.md (addf3): Likewise.
	(subdf3): Likewise.
	(muldf3): Likewise.
---
 gcc/config/arc/arc.c  | 12 ++++++++----
 gcc/config/arc/arc.md | 18 +++++++++---------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d60db50..f4bef3e 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -8647,8 +8647,10 @@ arc_process_double_reg_moves (rtx *operands)
 	{
 	  /* When we have 'mov D, r' or 'mov D, D' then get the target
 	     register pair for use with LR insn.  */
-	  rtx destHigh = simplify_gen_subreg(SImode, dest, DFmode, 4);
-	  rtx destLow  = simplify_gen_subreg(SImode, dest, DFmode, 0);
+	  rtx destHigh = simplify_gen_subreg (SImode, dest, DFmode,
+					     TARGET_BIG_ENDIAN ? 0 : 4);
+	  rtx destLow  = simplify_gen_subreg (SImode, dest, DFmode,
+					     TARGET_BIG_ENDIAN ? 4 : 0);
 
 	  /* Produce the two LR insns to get the high and low parts.  */
 	  emit_insn (gen_rtx_SET (destHigh,
@@ -8665,8 +8667,10 @@ arc_process_double_reg_moves (rtx *operands)
     {
       /* When we have 'mov r, D' or 'mov D, D' and we have access to the
 	 LR insn get the target register pair.  */
-      rtx srcHigh = simplify_gen_subreg(SImode, src, DFmode, 4);
-      rtx srcLow  = simplify_gen_subreg(SImode, src, DFmode, 0);
+      rtx srcHigh = simplify_gen_subreg (SImode, src, DFmode,
+					TARGET_BIG_ENDIAN ? 0 : 4);
+      rtx srcLow  = simplify_gen_subreg (SImode, src, DFmode,
+					TARGET_BIG_ENDIAN ? 4 : 0);
 
       emit_insn (gen_rtx_UNSPEC_VOLATILE (Pmode,
 					  gen_rtvec (3, dest, srcHigh, srcLow),
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 9766547..74530b1 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -5681,9 +5681,9 @@
    {
     if (GET_CODE (operands[2]) == CONST_DOUBLE)
      {
-        rtx high, low, tmp;
-        split_double (operands[2], &low, &high);
-        tmp = force_reg (SImode, high);
+        rtx first, second, tmp;
+        split_double (operands[2], &first, &second);
+        tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
         emit_insn (gen_adddf3_insn (operands[0], operands[1],
                                     operands[2], tmp, const0_rtx));
      }
@@ -5718,10 +5718,10 @@
      if ((GET_CODE (operands[1]) == CONST_DOUBLE)
           || GET_CODE (operands[2]) == CONST_DOUBLE)
       {
-        rtx high, low, tmp;
+        rtx first, second, tmp;
         int const_index = ((GET_CODE (operands[1]) == CONST_DOUBLE) ? 1 : 2);
-        split_double (operands[const_index], &low, &high);
-        tmp = force_reg (SImode, high);
+        split_double (operands[const_index], &first, &second);
+        tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
         emit_insn (gen_subdf3_insn (operands[0], operands[1],
                                     operands[2], tmp, const0_rtx));
       }
@@ -5753,9 +5753,9 @@
     {
      if (GET_CODE (operands[2]) == CONST_DOUBLE)
       {
-        rtx high, low, tmp;
-        split_double (operands[2], &low, &high);
-        tmp = force_reg (SImode, high);
+        rtx first, second, tmp;
+        split_double (operands[2], &first, &second);
+        tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
         emit_insn (gen_muldf3_insn (operands[0], operands[1],
                                     operands[2], tmp, const0_rtx));
       }
-- 
1.9.1