[Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.

Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
new file mode 100644
index 0000000..5f492d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrnd
+#define TEST_MSG "VRND"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
new file mode 100644
index 0000000..629240d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
@@ -0,0 +1,43 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+void FNNAME (INSN) (void)
+{
+  /* vector_res = vrndX (vector), then store the result.  */
+#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
+  VECT_VAR (vector_res, T1, W, N) =					\
+    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
+    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
+		       VECT_VAR (vector_res, T1, W, N))
+
+  /* Two auxliary macros are necessary to expand INSN.  */
+#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
+  TEST_VRND2 (INSN, Q, T1, T2, W, N)
+
+#define TEST_VRND(Q, T1, T2, W, N)		\
+  TEST_VRND1 (INSN, Q, T1, T2, W, N)
+
+  DECL_VARIABLE (vector, float, 32, 2);
+  DECL_VARIABLE (vector, float, 32, 4);
+
+  DECL_VARIABLE (vector_res, float, 32, 2);
+  DECL_VARIABLE (vector_res, float, 32, 4);
+
+  clean_results ();
+
+  VLOAD (vector, buffer, , float, f, 32, 2);
+  VLOAD (vector, buffer, q, float, f, 32, 4);
+
+  TEST_VRND ( , float, f, 32, 2);
+  TEST_VRND (q, float, f, 32, 4);
+
+  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int
+main (void)
+{
+  FNNAME (INSN) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
new file mode 100644
index 0000000..816fd28d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrnda
+#define TEST_MSG "VRNDA"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
new file mode 100644
index 0000000..029880c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrndm
+#define TEST_MSG "VRNDM"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
new file mode 100644
index 0000000..571243c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrndn
+#define TEST_MSG "VRNDN"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
new file mode 100644
index 0000000..ff4771c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrndp
+#define TEST_MSG "VRNDP"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
new file mode 100644
index 0000000..ff2357b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+					       0xc1600000, 0xc1500000 };
+
+#define INSN vrndx
+#define TEST_MSG "VRNDX"
+
+#include "vrndX.inc"
-- 
1.9.1

[Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose.

[Christophe Lyon]

It is useful to have more detailed information in the logs when checking
validation results: instead of repeating the intrinsic name, we now print
its return type too.

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK,
	CHECK_FP, CHECK_CUMULATIVE_SAT): Print which type was checked.

Change-Id: I74759d6a211cf52962f860fe77653a6f6edc1848

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 49fbd84..a2c160c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -81,7 +81,7 @@ extern size_t strlen(const char *);
 	  abort();							\
 	}								\
       }									\
-    fprintf(stderr, "CHECKED %s\n", MSG);				\
+    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
   }
 
 /* Floating-point variant.  */
@@ -110,7 +110,7 @@ extern size_t strlen(const char *);
 	  abort();							\
 	}								\
       }									\
-    fprintf(stderr, "CHECKED %s\n", MSG);				\
+    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
   }
 
 /* Clean buffer with a non-zero pattern to help diagnose buffer
@@ -335,7 +335,8 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
 	      strlen(COMMENT) > 0 ? " " COMMENT : "");			\
       abort();								\
     }									\
-    fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG);		\
+    fprintf(stderr, "CHECKED CUMULATIVE SAT %s %s\n",			\
+	    STR(VECT_TYPE(T, W, N)), MSG);				\
   }
 
 #define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment)		\
-- 
1.9.1

[Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vmul.c: Remove useless #ifdef.
	* gcc.target/aarch64/advsimd-intrinsics/vshl.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.

Change-Id: I1b00b8edc4db6e6457be5bc1f92e8b6e218da644

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
index 0cbb656..63f0d8d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
@@ -37,10 +37,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e,
 VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000,
 					   0xc4ae4ccd, 0xc4a1d999 };
 
-#ifndef INSN_NAME
 #define INSN_NAME vmul
 #define TEST_MSG "VMUL"
-#endif
 
 #define FNNAME1(NAME) exec_ ## NAME
 #define FNNAME(NAME) FNNAME1(NAME)
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
index 821c11e..e8a57a4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
@@ -101,10 +101,8 @@ VECT_VAR_DECL(expected_negative_shift,uint,64,2) [] = { 0x7ffffffffffffff,
 							0x7ffffffffffffff };
 
 
-#ifndef INSN_NAME
 #define INSN_NAME vshl
 #define TEST_MSG "VSHL/VSHLQ"
-#endif
 
 #define FNNAME1(NAME) exec_ ## NAME
 #define FNNAME(NAME) FNNAME1(NAME)
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
index 7f96540..9e74ffb 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -32,10 +32,8 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
 VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
 						  0x0, 0xffffffff };
 
-#ifndef INSN_NAME
 #define INSN_NAME vtst
 #define TEST_MSG "VTST/VTSTQ"
-#endif
 
 /* We can't use the standard ref_v_binary_op.c template because vtst
    has no 64 bits variant, and outputs are always of uint type.  */
-- 
1.9.1

[Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add fp16 tests.

Change-Id: I5fafd1e90baf09588ab9f5444817c74e7d865a20

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
index 5806050..fe41c5f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
@@ -13,6 +13,7 @@ uint32_t   expected_u32  = 0xfffffff1;
 uint64_t   expected_u64  = 0xfffffffffffffff0;
 poly8_t    expected_p8   = 0xf6;
 poly16_t   expected_p16  = 0xfff2;
+hfloat16_t expected_f16  = 0xcb80;
 hfloat32_t expected_f32  = 0xc1700000;
 
 int8_t     expectedq_s8  = 0xff;
@@ -25,6 +26,7 @@ uint32_t   expectedq_u32 = 0xfffffff2;
 uint64_t   expectedq_u64 = 0xfffffffffffffff1;
 poly8_t    expectedq_p8  = 0xfe;
 poly16_t   expectedq_p16 = 0xfff6;
+hfloat16_t expectedq_f16 = 0xca80;
 hfloat32_t expectedq_f32 = 0xc1500000;
 
 int error_found = 0;
@@ -52,6 +54,10 @@ void exec_vget_lane (void)
     uint32_t var_int32;
     float32_t var_float32;
   } var_int32_float32;
+  union {
+    uint16_t var_int16;
+    float16_t var_float16;
+  } var_int16_float16;
 
 #define TEST_VGET_LANE_FP(Q, T1, T2, W, N, L)				   \
   VAR(var, T1, W) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
@@ -81,10 +87,17 @@ void exec_vget_lane (void)
   VAR_DECL(var, uint, 64);
   VAR_DECL(var, poly, 8);
   VAR_DECL(var, poly, 16);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  VAR_DECL(var, float, 16);
+#endif
   VAR_DECL(var, float, 32);
 
   /* Initialize input values.  */
   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  VLOAD(vector, buffer, , float, f, 16, 4);
+  VLOAD(vector, buffer, q, float, f, 16, 8);
+#endif
   VLOAD(vector, buffer, , float, f, 32, 2);
   VLOAD(vector, buffer, q, float, f, 32, 4);
 
@@ -99,6 +112,9 @@ void exec_vget_lane (void)
   TEST_VGET_LANE(, uint, u, 64, 1, 0);
   TEST_VGET_LANE(, poly, p, 8, 8, 6);
   TEST_VGET_LANE(, poly, p, 16, 4, 2);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  TEST_VGET_LANE_FP(, float, f, 16, 4, 1);
+#endif
   TEST_VGET_LANE_FP(, float, f, 32, 2, 1);
 
   TEST_VGET_LANE(q, int, s, 8, 16, 15);
@@ -111,6 +127,9 @@ void exec_vget_lane (void)
   TEST_VGET_LANE(q, uint, u, 64, 2, 1);
   TEST_VGET_LANE(q, poly, p, 8, 16, 14);
   TEST_VGET_LANE(q, poly, p, 16, 8, 6);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  TEST_VGET_LANE_FP(q, float, f, 16, 8, 3);
+#endif
   TEST_VGET_LANE_FP(q, float, f, 32, 4, 3);
 }
 
-- 
1.9.1

[Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update

[Christophe Lyon]

Hi,

A few months ago, we decided it was time to remove neon-testgen.ml
and its generated tests. I did it, just to realize too late that
some intrinsics were not covered anymore, so I reverted the removal.

This patch series performs a little bit of cleanup and adds the
missing tests to cover all what is defined in arm_neon.h for AArch32.

Globally, this consists in adding tests for:
- missing poly8 and poly16 for vreinterpret and vtst
- fp16 tests for vget_lane, vstX_lane and vreinterpret
- armv8 vrnd{,a,m,n,p,x}
- tests for poly64 and poly128 intrinsics

Some intrinsics are not covered in aarch64/advsimd-intrinsics, but in
arm/crypto: vldrq, vstrq, vaes, vsha1, vsha256, vmull_p64,
vmull_high_p64.

Patches 1-4 are cleanup.
Patch 5 adds the missing poly8 and poly16 tests for vreinterpret.
Patch 6 adds the missing tests for vtst_p8 and vtstq_p8.
Patches 7,8, 11 add the missing fp16 tests
Patch 9 adds armv8 vrnd{,a,m,n,p,x} tests
Patch 10 adds tests for poly64 and poly128 operations

I've checked the coverage by building the list of intrinsics tested
via neon-testgen.ml, the list of intrinsics defined in arm_neon.h, and
running the advsimd-intrinsics.exp tests with -save-temps to gather
the list of actually tested intrinsics.

This series partly addresses PR 70369 which I created to keep track
of these missing intrinsics tests: several AArch64 AdvSIMD intrinsics
are still missing tests.

Tested with QEMU on arm* and aarch64*, with no regression, and
several new PASSes.

OK for trunk?

Christophe

Christophe Lyon (11):
  Fix typo in vreinterpret.c test comment.
  We can remove useless #ifdefs from these tests: vmul, vshl and vtst.
  AdvSIMD tests: be more verbose.
  Add forgotten vsliq_n_u64 test.
  Add missing vreinterpretq_p{8,16} tests.
  Add missing vtst_p8 and vtstq_p8 tests.
  Add missing vget_lane fp16 tests.
  Add missing vstX_lane fp16 tests.
  Add missing vrnd{,a,m,n,p,x} tests.
  Add missing tests for intrinsics operating on poly64 and poly128
    types.
  Add missing tests for vreinterpret, operating of fp16 type.

 .../aarch64/advsimd-intrinsics/arm-neon-ref.h      |  13 +-
 .../aarch64/advsimd-intrinsics/compute-ref-data.h  |  16 +
 .../aarch64/advsimd-intrinsics/p64_p128.c          | 691 +++++++++++++++++++++
 .../aarch64/advsimd-intrinsics/vget_lane.c         |  19 +
 .../gcc.target/aarch64/advsimd-intrinsics/vmul.c   |   2 -
 .../aarch64/advsimd-intrinsics/vreinterpret.c      | 255 +++++++-
 .../aarch64/advsimd-intrinsics/vreinterpret_p128.c | 160 +++++
 .../aarch64/advsimd-intrinsics/vreinterpret_p64.c  | 202 ++++++
 .../gcc.target/aarch64/advsimd-intrinsics/vrnd.c   |  16 +
 .../aarch64/advsimd-intrinsics/vrndX.inc           |  43 ++
 .../gcc.target/aarch64/advsimd-intrinsics/vrnda.c  |  16 +
 .../gcc.target/aarch64/advsimd-intrinsics/vrndm.c  |  16 +
 .../gcc.target/aarch64/advsimd-intrinsics/vrndn.c  |  16 +
 .../gcc.target/aarch64/advsimd-intrinsics/vrndp.c  |  16 +
 .../gcc.target/aarch64/advsimd-intrinsics/vrndx.c  |  16 +
 .../gcc.target/aarch64/advsimd-intrinsics/vshl.c   |   2 -
 .../gcc.target/aarch64/advsimd-intrinsics/vsli_n.c |   1 +
 .../aarch64/advsimd-intrinsics/vstX_lane.c         | 105 +++-
 .../gcc.target/aarch64/advsimd-intrinsics/vtst.c   |  20 +-
 19 files changed, 1612 insertions(+), 13 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c

-- 
1.9.1

[Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in comment.

Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 9e45e25..d4e5768 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
 VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
 						    0xfff5fff4, 0xfff7fff6 };
 
-/* Expected results for vreinterpretq_xx_f32.  */
+/* Expected results for vreinterpret_xx_f32.  */
 VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
 						0x0, 0x0, 0x70, 0xc1 };
 VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
-- 
1.9.1

[Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for vsliq_n_u64.

Change-Id: I90bb2b225ffd7bfd54a0827a0264ac20271f54f2

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
index 0285083..e5f78d0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
@@ -169,6 +169,7 @@ void vsli_extra(void)
   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
   CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
 }
-- 
1.9.1

[Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
	for vtst_p8 and vtstq_p8.

Change-Id: Id555a9b3214945506a106e2465b42d38bf76a3a7

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
index 9e74ffb..4c7ee79 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -32,6 +32,14 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
 VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
 						  0x0, 0xffffffff };
 
+/* Expected results with poly input.  */
+VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+					     0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff };
+
 #define INSN_NAME vtst
 #define TEST_MSG "VTST/VTSTQ"
 
@@ -71,12 +79,14 @@ FNNAME (INSN_NAME)
   VDUP(vector2, , uint, u, 8, 8, 15);
   VDUP(vector2, , uint, u, 16, 4, 5);
   VDUP(vector2, , uint, u, 32, 2, 1);
+  VDUP(vector2, , poly, p, 8, 8, 15);
   VDUP(vector2, q, int, s, 8, 16, 15);
   VDUP(vector2, q, int, s, 16, 8, 5);
   VDUP(vector2, q, int, s, 32, 4, 1);
   VDUP(vector2, q, uint, u, 8, 16, 15);
   VDUP(vector2, q, uint, u, 16, 8, 5);
   VDUP(vector2, q, uint, u, 32, 4, 1);
+  VDUP(vector2, q, poly, p, 8, 16, 15);
 
 #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
   MACRO(VAR, , T1, T2, 8, 8);					\
@@ -109,6 +119,14 @@ FNNAME (INSN_NAME)
   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
+
+  /* Now, test the variants with poly8 as input.  */
+#undef CMT
+#define CMT " (poly input)"
+  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
+  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
 }
 
 int main (void)
-- 
1.9.1

[Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result):
	Add poly64x1_t and poly64x2_t cases if supported.
	* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
	(buffer, buffer_pad, buffer_dup, buffer_dup_pad): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: New file.

Change-Id: Ie9bb0c4fd0b8f04fb37668cdb315eaafd06e55c4

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index a2c160c..8664dfc 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -133,6 +133,9 @@ static ARRAY(result, uint, 32, 2);
 static ARRAY(result, uint, 64, 1);
 static ARRAY(result, poly, 8, 8);
 static ARRAY(result, poly, 16, 4);
+#if defined (__ARM_FEATURE_CRYPTO)
+static ARRAY(result, poly, 64, 1);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 static ARRAY(result, float, 16, 4);
 #endif
@@ -147,6 +150,9 @@ static ARRAY(result, uint, 32, 4);
 static ARRAY(result, uint, 64, 2);
 static ARRAY(result, poly, 8, 16);
 static ARRAY(result, poly, 16, 8);
+#if defined (__ARM_FEATURE_CRYPTO)
+static ARRAY(result, poly, 64, 2);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 static ARRAY(result, float, 16, 8);
 #endif
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
index c8d4336..f8c4aef 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
@@ -118,6 +118,10 @@ VECT_VAR_DECL_INIT(buffer, uint, 32, 2);
 PAD(buffer_pad, uint, 32, 2);
 VECT_VAR_DECL_INIT(buffer, uint, 64, 1);
 PAD(buffer_pad, uint, 64, 1);
+#if defined (__ARM_FEATURE_CRYPTO)
+VECT_VAR_DECL_INIT(buffer, poly, 64, 1);
+PAD(buffer_pad, poly, 64, 1);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 VECT_VAR_DECL_INIT(buffer, float, 16, 4);
 PAD(buffer_pad, float, 16, 4);
@@ -144,6 +148,10 @@ VECT_VAR_DECL_INIT(buffer, poly, 8, 16);
 PAD(buffer_pad, poly, 8, 16);
 VECT_VAR_DECL_INIT(buffer, poly, 16, 8);
 PAD(buffer_pad, poly, 16, 8);
+#if defined (__ARM_FEATURE_CRYPTO)
+VECT_VAR_DECL_INIT(buffer, poly, 64, 2);
+PAD(buffer_pad, poly, 64, 2);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 VECT_VAR_DECL_INIT(buffer, float, 16, 8);
 PAD(buffer_pad, float, 16, 8);
@@ -178,6 +186,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 8);
 VECT_VAR_DECL(buffer_dup_pad, poly, 8, 8);
 VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 4);
 VECT_VAR_DECL(buffer_dup_pad, poly, 16, 4);
+#if defined (__ARM_FEATURE_CRYPTO)
+VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 1);
+VECT_VAR_DECL(buffer_dup_pad, poly, 64, 1);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 VECT_VAR_DECL_INIT4(buffer_dup, float, 16, 4);
 VECT_VAR_DECL(buffer_dup_pad, float, 16, 4);
@@ -205,6 +217,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 16);
 VECT_VAR_DECL(buffer_dup_pad, poly, 8, 16);
 VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 8);
 VECT_VAR_DECL(buffer_dup_pad, poly, 16, 8);
+#if defined (__ARM_FEATURE_CRYPTO)
+VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 2);
+VECT_VAR_DECL(buffer_dup_pad, poly, 64, 2);
+#endif
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 VECT_VAR_DECL_INIT(buffer_dup, float, 16, 8);
 VECT_VAR_DECL(buffer_dup_pad, float, 16, 8);
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
new file mode 100644
index 0000000..ced3884
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
@@ -0,0 +1,665 @@
+/* This file contains tests for all the *p64 intrinsics, except for
+   vreinterpret which have their own testcase.  */
+
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results: vbsl.  */
+VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
+VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
+					      0xfffffff1 };
+
+/* Expected results: vceq.  */
+VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
+
+/* Expected results: vcombine.  */
+VECT_VAR_DECL(vcombine_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x88 };
+
+/* Expected results: vcreate.  */
+VECT_VAR_DECL(vcreate_expected,poly,64,1) [] = { 0x123456789abcdef0 };
+
+/* Expected results: vdup_lane.  */
+VECT_VAR_DECL(vdup_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vdup_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
+						   0xfffffffffffffff0 };
+
+/* Expected results: vdup_n.  */
+VECT_VAR_DECL(vdup_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vdup_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
+						 0xfffffffffffffff0 };
+VECT_VAR_DECL(vdup_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vdup_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
+						 0xfffffffffffffff1 };
+VECT_VAR_DECL(vdup_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vdup_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
+						 0xfffffffffffffff2 };
+
+/* Expected results: vext.  */
+VECT_VAR_DECL(vext_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vext_expected,poly,64,2) [] = { 0xfffffffffffffff1, 0x88 };
+
+/* Expected results: vget_low.  */
+VECT_VAR_DECL(vget_low_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+
+/* Expected results: vld1.  */
+VECT_VAR_DECL(vld1_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld1_expected,poly,64,2) [] = { 0xfffffffffffffff0,
+					      0xfffffffffffffff1 };
+
+/* Expected results: vld1_dup.  */
+VECT_VAR_DECL(vld1_dup_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld1_dup_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
+						   0xfffffffffffffff0 };
+VECT_VAR_DECL(vld1_dup_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld1_dup_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
+						   0xfffffffffffffff1 };
+VECT_VAR_DECL(vld1_dup_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vld1_dup_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
+						   0xfffffffffffffff2 };
+
+/* Expected results: vld1_lane.  */
+VECT_VAR_DECL(vld1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
+						   0xaaaaaaaaaaaaaaaa };
+
+/* Expected results: vldX.  */
+VECT_VAR_DECL(vld2_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld2_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld3_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld3_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld3_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vld4_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld4_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld4_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vld4_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
+
+/* Expected results: vldX_dup.  */
+VECT_VAR_DECL(vld2_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld2_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld3_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld3_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld3_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vld4_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vld4_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(vld4_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(vld4_dup_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
+
+/* Expected results: vsli.  */
+VECT_VAR_DECL(vsli_expected,poly,64,1) [] = { 0x10 };
+VECT_VAR_DECL(vsli_expected,poly,64,2) [] = { 0x7ffffffffffff0,
+					      0x7ffffffffffff1 };
+VECT_VAR_DECL(vsli_expected_max_shift,poly,64,1) [] = { 0x7ffffffffffffff0 };
+VECT_VAR_DECL(vsli_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
+							0xfffffffffffffff1 };
+
+/* Expected results: vsri.  */
+VECT_VAR_DECL(vsri_expected,poly,64,1) [] = { 0xe000000000000000 };
+VECT_VAR_DECL(vsri_expected,poly,64,2) [] = { 0xfffffffffffff800,
+					      0xfffffffffffff800 };
+VECT_VAR_DECL(vsri_expected_max_shift,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vsri_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
+							0xfffffffffffffff1 };
+
+/* Expected results: vst1_lane.  */
+VECT_VAR_DECL(vst1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vst1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
+						   0x3333333333333333 };
+
+int main (void)
+{
+  int i;
+
+  /* vbsl_p64 tests.  */
+#define TEST_MSG "VBSL/VBSLQ"
+
+#define TEST_VBSL(T3, Q, T1, T2, W, N)					\
+  VECT_VAR(vbsl_vector_res, T1, W, N) =					\
+    vbsl##Q##_##T2##W(VECT_VAR(vbsl_vector_first, T3, W, N),		\
+		      VECT_VAR(vbsl_vector, T1, W, N),			\
+		      VECT_VAR(vbsl_vector2, T1, W, N));		\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vbsl_vector_res, T1, W, N))
+
+  DECL_VARIABLE(vbsl_vector, poly, 64, 1);
+  DECL_VARIABLE(vbsl_vector, poly, 64, 2);
+  DECL_VARIABLE(vbsl_vector2, poly, 64, 1);
+  DECL_VARIABLE(vbsl_vector2, poly, 64, 2);
+  DECL_VARIABLE(vbsl_vector_res, poly, 64, 1);
+  DECL_VARIABLE(vbsl_vector_res, poly, 64, 2);
+
+  DECL_VARIABLE(vbsl_vector_first, uint, 64, 1);
+  DECL_VARIABLE(vbsl_vector_first, uint, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vbsl_vector, buffer, , poly, p, 64, 1);
+  VLOAD(vbsl_vector, buffer, q, poly, p, 64, 2);
+
+  VDUP(vbsl_vector2, , poly, p, 64, 1, 0xFFFFFFF3);
+  VDUP(vbsl_vector2, q, poly, p, 64, 2, 0xFFFFFFF3);
+
+  VDUP(vbsl_vector_first, , uint, u, 64, 1, 0xFFFFFFF2);
+  VDUP(vbsl_vector_first, q, uint, u, 64, 2, 0xFFFFFFF2);
+
+  TEST_VBSL(uint, , poly, p, 64, 1);
+  TEST_VBSL(uint, q, poly, p, 64, 2);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vbsl_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vbsl_expected, "");
+
+  /* vceq_p64 tests. */
+#undef TEST_MSG
+#define TEST_MSG "VCEQ"
+
+#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)				\
+  VECT_VAR(vceq_vector_res, T3, W, N) =					\
+    INSN##Q##_##T2##W(VECT_VAR(vceq_vector, T1, W, N),			\
+		      VECT_VAR(vceq_vector2, T1, W, N));		\
+  vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vceq_vector_res, T3, W, N))
+
+#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N)				\
+  TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
+
+  DECL_VARIABLE(vceq_vector, poly, 64, 1);
+  DECL_VARIABLE(vceq_vector2, poly, 64, 1);
+  DECL_VARIABLE(vceq_vector_res, uint, 64, 1);
+
+  CLEAN(result, uint, 64, 1);
+
+  VLOAD(vceq_vector, buffer, , poly, p, 64, 1);
+
+  VDUP(vceq_vector2, , poly, p, 64, 1, 0x88);
+
+  fprintf(stderr, "toto\n");
+  TEST_VCOMP(vceq, , poly, p, uint, 64, 1);
+
+  CHECK(TEST_MSG, uint, 64, 1, PRIx64, vceq_expected, "");
+  fprintf(stderr, "toto\n");
+
+  /* vcombine_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VCOMBINE"
+
+#define TEST_VCOMBINE(T1, T2, W, N, N2)					\
+  VECT_VAR(vcombine_vector128, T1, W, N2) =				\
+    vcombine_##T2##W(VECT_VAR(vcombine_vector64_a, T1, W, N),		\
+		     VECT_VAR(vcombine_vector64_b, T1, W, N));		\
+  vst1q_##T2##W(VECT_VAR(result, T1, W, N2), VECT_VAR(vcombine_vector128, T1, W, N2))
+
+  DECL_VARIABLE(vcombine_vector64_a, poly, 64, 1);
+  DECL_VARIABLE(vcombine_vector64_b, poly, 64, 1);
+  DECL_VARIABLE(vcombine_vector128, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vcombine_vector64_a, buffer, , poly, p, 64, 1);
+
+  VDUP(vcombine_vector64_b, , poly, p, 64, 1, 0x88);
+
+  TEST_VCOMBINE(poly, p, 64, 1, 2);
+
+  CHECK(TEST_MSG, poly, 64, 2, PRIx16, vcombine_expected, "");
+
+  /* vcreate_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VCREATE"
+
+#define TEST_VCREATE(T1, T2, W, N)					\
+  VECT_VAR(vcreate_vector_res, T1, W, N) =				\
+    vcreate_##T2##W(VECT_VAR(vcreate_val, T1, W, N));			\
+  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vcreate_vector_res, T1, W, N))
+
+#define DECL_VAL(VAR, T1, W, N)			\
+  uint64_t VECT_VAR(VAR, T1, W, N)
+
+  DECL_VAL(vcreate_val, poly, 64, 1);
+  DECL_VARIABLE(vcreate_vector_res, poly, 64, 1);
+
+  CLEAN(result, poly, 64, 2);
+
+  VECT_VAR(vcreate_val, poly, 64, 1) = 0x123456789abcdef0ULL;
+
+  TEST_VCREATE(poly, p, 64, 1);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vcreate_expected, "");
+
+  /* vdup_lane_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
+
+#define TEST_VDUP_LANE(Q, T1, T2, W, N, N2, L)				\
+  VECT_VAR(vdup_lane_vector_res, T1, W, N) =				\
+    vdup##Q##_lane_##T2##W(VECT_VAR(vdup_lane_vector, T1, W, N2), L);	\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_lane_vector_res, T1, W, N))
+
+  DECL_VARIABLE(vdup_lane_vector, poly, 64, 1);
+  DECL_VARIABLE(vdup_lane_vector, poly, 64, 2);
+  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 1);
+  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vdup_lane_vector, buffer, , poly, p, 64, 1);
+
+  TEST_VDUP_LANE(, poly, p, 64, 1, 1, 0);
+  TEST_VDUP_LANE(q, poly, p, 64, 2, 1, 0);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_lane_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_lane_expected, "");
+
+  /* vdup_n_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VDUP/VDUPQ"
+
+#define TEST_VDUP(Q, T1, T2, W, N)					\
+  VECT_VAR(vdup_n_vector, T1, W, N) =					\
+    vdup##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]);		\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_n_vector, T1, W, N))
+
+  DECL_VARIABLE(vdup_n_vector, poly, 64, 1);
+  DECL_VARIABLE(vdup_n_vector, poly, 64, 2);
+
+  /* Try to read different places from the input buffer.  */
+  for (i=0; i< 3; i++) {
+    CLEAN(result, poly, 64, 1);
+    CLEAN(result, poly, 64, 2);
+
+    TEST_VDUP(, poly, p, 64, 1);
+    TEST_VDUP(q, poly, p, 64, 2);
+
+    switch (i) {
+    case 0:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected0, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected0, "");
+      break;
+    case 1:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected1, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected1, "");
+      break;
+    case 2:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected2, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected2, "");
+      break;
+    default:
+      abort();
+    }
+  }
+
+  /* vexit_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VEXT/VEXTQ"
+
+#define TEST_VEXT(Q, T1, T2, W, N, V)					\
+  VECT_VAR(vext_vector_res, T1, W, N) =					\
+    vext##Q##_##T2##W(VECT_VAR(vext_vector1, T1, W, N),			\
+		      VECT_VAR(vext_vector2, T1, W, N),			\
+		      V);						\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vext_vector_res, T1, W, N))
+
+  DECL_VARIABLE(vext_vector1, poly, 64, 1);
+  DECL_VARIABLE(vext_vector1, poly, 64, 2);
+  DECL_VARIABLE(vext_vector2, poly, 64, 1);
+  DECL_VARIABLE(vext_vector2, poly, 64, 2);
+  DECL_VARIABLE(vext_vector_res, poly, 64, 1);
+  DECL_VARIABLE(vext_vector_res, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vext_vector1, buffer, , poly, p, 64, 1);
+  VLOAD(vext_vector1, buffer, q, poly, p, 64, 2);
+
+  VDUP(vext_vector2, , poly, p, 64, 1, 0x88);
+  VDUP(vext_vector2, q, poly, p, 64, 2, 0x88);
+
+  TEST_VEXT(, poly, p, 64, 1, 0);
+  TEST_VEXT(q, poly, p, 64, 2, 1);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vext_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vext_expected, "");
+
+  /* vget_low_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VGET_LOW"
+
+#define TEST_VGET_LOW(T1, T2, W, N, N2)					\
+  VECT_VAR(vget_low_vector64, T1, W, N) =				\
+    vget_low_##T2##W(VECT_VAR(vget_low_vector128, T1, W, N2));		\
+  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_low_vector64, T1, W, N))
+
+  DECL_VARIABLE(vget_low_vector64, poly, 64, 1);
+  DECL_VARIABLE(vget_low_vector128, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+
+  VLOAD(vget_low_vector128, buffer, q, poly, p, 64, 2);
+
+  TEST_VGET_LOW(poly, p, 64, 1, 2);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vget_low_expected, "");
+
+  /* vld1_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VLD1/VLD1Q"
+
+#define TEST_VLD1(VAR, BUF, Q, T1, T2, W, N)				\
+  VECT_VAR(VAR, T1, W, N) = vld1##Q##_##T2##W(VECT_VAR(BUF, T1, W, N)); \
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
+
+  DECL_VARIABLE(vld1_vector, poly, 64, 1);
+  DECL_VARIABLE(vld1_vector, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vld1_vector, buffer, , poly, p, 64, 1);
+  VLOAD(vld1_vector, buffer, q, poly, p, 64, 2);
+
+  TEST_VLD1(vld1_vector, buffer, , poly, p, 64, 1);
+  TEST_VLD1(vld1_vector, buffer, q, poly, p, 64, 2);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_expected, "");
+
+  /* vld1_dup_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VLD1_DUP/VLD1_DUPQ"
+
+#define TEST_VLD1_DUP(VAR, BUF, Q, T1, T2, W, N)			\
+  VECT_VAR(VAR, T1, W, N) =						\
+    vld1##Q##_dup_##T2##W(&VECT_VAR(BUF, T1, W, N)[i]);			\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
+
+  DECL_VARIABLE(vld1_dup_vector, poly, 64, 1);
+  DECL_VARIABLE(vld1_dup_vector, poly, 64, 2);
+
+  /* Try to read different places from the input buffer.  */
+  for (i=0; i<3; i++) {
+    CLEAN(result, poly, 64, 1);
+    CLEAN(result, poly, 64, 2);
+
+    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, , poly, p, 64, 1);
+    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, q, poly, p, 64, 2);
+
+    switch (i) {
+    case 0:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected0, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected0, "");
+      break;
+    case 1:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected1, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected1, "");
+      break;
+    case 2:
+      CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected2, "");
+      CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected2, "");
+      break;
+    default:
+      abort();
+    }
+  }
+
+  /* vld1_lane_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
+
+#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)				\
+  memset (VECT_VAR(vld1_lane_buffer_src, T1, W, N), 0xAA, W/8*N);	\
+  VECT_VAR(vld1_lane_vector_src, T1, W, N) =				\
+    vld1##Q##_##T2##W(VECT_VAR(vld1_lane_buffer_src, T1, W, N));	\
+  VECT_VAR(vld1_lane_vector, T1, W, N) =				\
+    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),			\
+			   VECT_VAR(vld1_lane_vector_src, T1, W, N), L); \
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vld1_lane_vector, T1, W, N))
+
+  DECL_VARIABLE(vld1_lane_vector, poly, 64, 1);
+  DECL_VARIABLE(vld1_lane_vector, poly, 64, 2);
+  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 1);
+  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 2);
+
+  ARRAY(vld1_lane_buffer_src, poly, 64, 1);
+  ARRAY(vld1_lane_buffer_src, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  TEST_VLD1_LANE(, poly, p, 64, 1, 0);
+  TEST_VLD1_LANE(q, poly, p, 64, 2, 0);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_lane_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_lane_expected, "");
+
+  /* vldX_p64 tests.  */
+#define DECL_VLDX(T1, W, N, X)						\
+  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_vector, T1, W, N, X); \
+  VECT_VAR_DECL(vldX_result_bis_##X, T1, W, N)[X * N]
+
+#define TEST_VLDX(Q, T1, T2, W, N, X)					\
+  VECT_ARRAY_VAR(vldX_vector, T1, W, N, X) =				\
+    /* Use dedicated init buffer, of size X */				\
+    vld##X##Q##_##T2##W(VECT_ARRAY_VAR(buffer_vld##X, T1, W, N, X));	\
+  vst##X##Q##_##T2##W(VECT_VAR(vldX_result_bis_##X, T1, W, N),		\
+		      VECT_ARRAY_VAR(vldX_vector, T1, W, N, X));	\
+  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_result_bis_##X, T1, W, N), \
+	 sizeof(VECT_VAR(result, T1, W, N)));
+
+  /* Overwrite "result" with the contents of "result_bis"[Y].  */
+#define TEST_EXTRA_CHUNK(T1, W, N, X,Y)				\
+  memcpy(VECT_VAR(result, T1, W, N),				\
+	 &(VECT_VAR(vldX_result_bis_##X, T1, W, N)[Y*N]),	\
+	 sizeof(VECT_VAR(result, T1, W, N)));
+
+  DECL_VLDX(poly, 64, 1, 2);
+  DECL_VLDX(poly, 64, 1, 3);
+  DECL_VLDX(poly, 64, 1, 4);
+
+  VECT_ARRAY_INIT2(buffer_vld2, poly, 64, 1);
+  PAD(buffer_vld2_pad, poly, 64, 1);
+  VECT_ARRAY_INIT3(buffer_vld3, poly, 64, 1);
+  PAD(buffer_vld3_pad, poly, 64, 1);
+  VECT_ARRAY_INIT4(buffer_vld4, poly, 64, 1);
+  PAD(buffer_vld4_pad, poly, 64, 1);
+
+#undef TEST_MSG
+#define TEST_MSG "VLD2/VLD2Q"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX(, poly, p, 64, 1, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 2, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_1, "chunk 1");
+
+#undef TEST_MSG
+#define TEST_MSG "VLD3/VLD3Q"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX(, poly, p, 64, 1, 3);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_1, "chunk 1");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_2, "chunk 2");
+
+#undef TEST_MSG
+#define TEST_MSG "VLD4/VLD4Q"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX(, poly, p, 64, 1, 4);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_1, "chunk 1");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_2, "chunk 2");
+  CLEAN(result, poly, 64, 1);
+  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 3);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_3, "chunk 3");
+
+  /* vldX_dup_p64 tests.  */
+#define DECL_VLDX_DUP(T1, W, N, X)					\
+  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X); \
+  VECT_VAR_DECL(vldX_dup_result_bis_##X, T1, W, N)[X * N]
+
+#define TEST_VLDX_DUP(Q, T1, T2, W, N, X)				\
+  VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X) =			\
+    vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]);	\
+    									\
+  vst##X##Q##_##T2##W(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N),	\
+		      VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X));	\
+  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_dup_result_bis_##X, T1, W, N), \
+	 sizeof(VECT_VAR(result, T1, W, N)));
+
+  /* Overwrite "result" with the contents of "result_bis"[Y].  */
+#define TEST_VLDX_DUP_EXTRA_CHUNK(T1, W, N, X,Y)		\
+  memcpy(VECT_VAR(result, T1, W, N),				\
+	 &(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N)[Y*N]),	\
+	 sizeof(VECT_VAR(result, T1, W, N)));
+
+  DECL_VLDX_DUP(poly, 64, 1, 2);
+  DECL_VLDX_DUP(poly, 64, 1, 3);
+  DECL_VLDX_DUP(poly, 64, 1, 4);
+
+
+#undef TEST_MSG
+#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP(, poly, p, 64, 1, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 2, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_1, "chunk 1");
+
+#undef TEST_MSG
+#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP(, poly, p, 64, 1, 3);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_1, "chunk 1");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_2, "chunk 2");
+
+#undef TEST_MSG
+#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP(, poly, p, 64, 1, 4);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_0, "chunk 0");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 1);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_1, "chunk 1");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 2);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_2, "chunk 2");
+  CLEAN(result, poly, 64, 1);
+  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 3);
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_3, "chunk 3");
+
+  /* vsli_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VSLI"
+
+#define TEST_VSXI1(INSN, Q, T1, T2, W, N, V)				\
+  VECT_VAR(vsXi_vector_res, T1, W, N) =					\
+    INSN##Q##_n_##T2##W(VECT_VAR(vsXi_vector, T1, W, N),		\
+		      VECT_VAR(vsXi_vector2, T1, W, N),			\
+		      V);						\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vsXi_vector_res, T1, W, N))
+
+#define TEST_VSXI(INSN, Q, T1, T2, W, N, V)	\
+  TEST_VSXI1(INSN, Q, T1, T2, W, N, V)
+
+  DECL_VARIABLE(vsXi_vector, poly, 64, 1);
+  DECL_VARIABLE(vsXi_vector, poly, 64, 2);
+  DECL_VARIABLE(vsXi_vector2, poly, 64, 1);
+  DECL_VARIABLE(vsXi_vector2, poly, 64, 2);
+  DECL_VARIABLE(vsXi_vector_res, poly, 64, 1);
+  DECL_VARIABLE(vsXi_vector_res, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
+  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
+
+  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
+  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
+
+  TEST_VSXI(vsli, , poly, p, 64, 1, 3);
+  TEST_VSXI(vsli, q, poly, p, 64, 2, 53);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected, "");
+
+  /* Test cases with maximum shift amount.  */
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  TEST_VSXI(vsli, , poly, p, 64, 1, 63);
+  TEST_VSXI(vsli, q, poly, p, 64, 2, 63);
+
+#define COMMENT "(max shift amount)"
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected_max_shift, COMMENT);
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected_max_shift, COMMENT);
+
+  /* vsri_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VSRI"
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
+  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
+
+  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
+  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
+
+  TEST_VSXI(vsri, , poly, p, 64, 1, 3);
+  TEST_VSXI(vsri, q, poly, p, 64, 2, 53);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected, "");
+
+  /* Test cases with maximum shift amount.  */
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  TEST_VSXI(vsri, , poly, p, 64, 1, 64);
+  TEST_VSXI(vsri, q, poly, p, 64, 2, 64);
+
+#define COMMENT "(max shift amount)"
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected_max_shift, COMMENT);
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected_max_shift, COMMENT);
+
+  /* vst1_lane_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VST1_LANE/VST1_LANEQ"
+
+#define TEST_VST1_LANE(Q, T1, T2, W, N, L)				\
+  VECT_VAR(vst1_lane_vector, T1, W, N) =				\
+    vld1##Q##_##T2##W(VECT_VAR(buffer, T1, W, N));			\
+  vst1##Q##_lane_##T2##W(VECT_VAR(result, T1, W, N),			\
+			 VECT_VAR(vst1_lane_vector, T1, W, N), L)
+
+  DECL_VARIABLE(vst1_lane_vector, poly, 64, 1);
+  DECL_VARIABLE(vst1_lane_vector, poly, 64, 2);
+
+  CLEAN(result, poly, 64, 1);
+  CLEAN(result, poly, 64, 2);
+
+  TEST_VST1_LANE(, poly, p, 64, 1, 0);
+  TEST_VST1_LANE(q, poly, p, 64, 2, 0);
+
+  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vst1_lane_expected, "");
+  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vst1_lane_expected, "");
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
new file mode 100644
index 0000000..a049cb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
@@ -0,0 +1,151 @@
+/* This file contains tests for the vreinterpret *p128 intrinsics.  */
+
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results: vreinterpretq_p128_*.  */
+VECT_VAR_DECL(vreint_expected_q_p128_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							  0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p128_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							   0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p128_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
+							   0xfffffff3fffffff2 };
+VECT_VAR_DECL(vreint_expected_q_p128_s64,poly,64,2) [] = { 0xfffffffffffffff0,
+							   0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p128_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							  0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p128_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							   0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p128_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
+							   0xfffffff3fffffff2 };
+VECT_VAR_DECL(vreint_expected_q_p128_u64,poly,64,2) [] = { 0xfffffffffffffff0,
+							   0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p128_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							  0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							   0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
+							   0xc1500000c1600000 };
+
+/* Expected results: vreinterpretq_*_p128.  */
+VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff,
+							 0xf1, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_s16_p128,int,16,8) [] = { 0xfff0, 0xffff,
+							  0xffff, 0xffff,
+							  0xfff1, 0xffff,
+							  0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_s32_p128,int,32,4) [] = { 0xfffffff0, 0xffffffff,
+							  0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_s64_p128,int,64,2) [] = { 0xfffffffffffffff0,
+							  0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_u8_p128,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							  0xff, 0xff, 0xff, 0xff,
+							  0xf1, 0xff, 0xff, 0xff,
+							  0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_u16_p128,uint,16,8) [] = { 0xfff0, 0xffff,
+							   0xffff, 0xffff,
+							   0xfff1, 0xffff,
+							   0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_u32_p128,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
+							   0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_u64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
+							   0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p8_p128,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							  0xff, 0xff, 0xff, 0xff,
+							  0xf1, 0xff, 0xff, 0xff,
+							  0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_p16_p128,poly,16,8) [] = { 0xfff0, 0xffff,
+							   0xffff, 0xffff,
+							   0xfff1, 0xffff,
+							   0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
+							   0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
+							     0xfffffff1, 0xffffffff };
+
+int main (void)
+{
+  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector);
+  DECL_VARIABLE(vreint_vector, poly, 64, 2);
+  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector_res);
+  DECL_VARIABLE(vreint_vector_res, poly, 64, 2);
+
+  clean_results ();
+
+  TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
+  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
+  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
+
+  /* vreinterpretq_p128_* tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VREINTERPRETQ_P128_*"
+
+  /* Since there is no way to store a poly128_t value, convert to
+     poly64x2_t before storing. This means that we are not able to
+     test vreinterpretq_p128* alone, and that errors in
+     vreinterpretq_p64_p128 could compensate for errors in
+     vreinterpretq_p128*.  */
+#define TEST_VREINTERPRET128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+  VECT_VAR(vreint_vector_res, poly, 64, 2) =  vreinterpretq_p64_p128(	\
+    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS))); \
+  vst1##Q##_##T2##64(VECT_VAR(result, poly, 64, 2),			\
+                     VECT_VAR(vreint_vector_res, poly, 64, 2));		\
+  CHECK(TEST_MSG, T1, 64, 2, PRIx##64, EXPECTED, "");
+
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 8, 16, vreint_expected_q_p128_s8);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 16, 8, vreint_expected_q_p128_s16);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 32, 4, vreint_expected_q_p128_s32);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 64, 2, vreint_expected_q_p128_s64);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 8, 16, vreint_expected_q_p128_u8);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 16, 8, vreint_expected_q_p128_u16);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 32, 4, vreint_expected_q_p128_u32);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
+
+  /* vreinterpretq_*_p128 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VREINTERPRETQ_*_P128"
+
+  /* Since there is no way to load a poly128_t value, load a
+     poly64x2_t and convert it to poly128_t. This means that we are
+     not able to test vreinterpretq_*_p128 alone, and that errors in
+     vreinterpretq_p128_p64 could compensate for errors in
+     vreinterpretq_*_p128*.  */
+#define TEST_VREINTERPRET_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+  VECT_VAR(vreint_vector_res, T1, W, N) =				\
+    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
+  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
+		    VECT_VAR(vreint_vector_res, T1, W, N));		\
+  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+#define TEST_VREINTERPRET_FP_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+  VECT_VAR(vreint_vector_res, T1, W, N) =				\
+    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
+  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
+		    VECT_VAR(vreint_vector_res, T1, W, N));		\
+  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+  TEST_VREINTERPRET_FROM_P128(q, int, s, 8, 16, poly, p, 128, 1, vreint_expected_q_s8_p128);
+  TEST_VREINTERPRET_FROM_P128(q, int, s, 16, 8, poly, p, 128, 1, vreint_expected_q_s16_p128);
+  TEST_VREINTERPRET_FROM_P128(q, int, s, 32, 4, poly, p, 128, 1, vreint_expected_q_s32_p128);
+  TEST_VREINTERPRET_FROM_P128(q, int, s, 64, 2, poly, p, 128, 1, vreint_expected_q_s64_p128);
+  TEST_VREINTERPRET_FROM_P128(q, uint, u, 8, 16, poly, p, 128, 1, vreint_expected_q_u8_p128);
+  TEST_VREINTERPRET_FROM_P128(q, uint, u, 16, 8, poly, p, 128, 1, vreint_expected_q_u16_p128);
+  TEST_VREINTERPRET_FROM_P128(q, uint, u, 32, 4, poly, p, 128, 1, vreint_expected_q_u32_p128);
+  TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
+  TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
+  TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
+  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
new file mode 100644
index 0000000..79f3cd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
@@ -0,0 +1,188 @@
+/* This file contains tests for the vreinterpret *p64 intrinsics.  */
+
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results: vreinterpret_p64_*.  */
+VECT_VAR_DECL(vreint_expected_p64_s8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(vreint_expected_p64_s16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(vreint_expected_p64_s32,poly,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(vreint_expected_p64_s64,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vreint_expected_p64_u8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(vreint_expected_p64_u16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(vreint_expected_p64_u32,poly,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
+
+/* Expected results: vreinterpretq_p64_*.  */
+VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p64_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							  0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p64_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
+							  0xfffffff3fffffff2 };
+VECT_VAR_DECL(vreint_expected_q_p64_s64,poly,64,2) [] = { 0xfffffffffffffff0,
+							  0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p64_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p64_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							  0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p64_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
+							  0xfffffff3fffffff2 };
+VECT_VAR_DECL(vreint_expected_q_p64_u64,poly,64,2) [] = { 0xfffffffffffffff0,
+							  0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p64_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+							 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
+							  0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
+							  0xc1500000c1600000 };
+
+/* Expected results: vreinterpret_*_p64.  */
+VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+						     0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_s16_p64,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_s32_p64,int,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_s64_p64,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vreint_expected_u8_p64,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+						      0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_u16_p64,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_u32_p64,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_u64_p64,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+						      0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+
+/* Expected results: vreinterpretq_*_p64.  */
+VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							0xff, 0xff, 0xff, 0xff,
+							0xf1, 0xff, 0xff, 0xff,
+							0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_s16_p64,int,16,8) [] = { 0xfff0, 0xffff,
+							 0xffff, 0xffff,
+							 0xfff1, 0xffff,
+							 0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_s32_p64,int,32,4) [] = { 0xfffffff0, 0xffffffff,
+							 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_s64_p64,int,64,2) [] = { 0xfffffffffffffff0,
+							 0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_u8_p64,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff,
+							 0xf1, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_u16_p64,uint,16,8) [] = { 0xfff0, 0xffff,
+							  0xffff, 0xffff,
+							  0xfff1, 0xffff,
+							  0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_u32_p64,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
+							  0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_u64_p64,uint,64,2) [] = { 0xfffffffffffffff0,
+							  0xfffffffffffffff1 };
+VECT_VAR_DECL(vreint_expected_q_p8_p64,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff,
+							 0xf1, 0xff, 0xff, 0xff,
+							 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
+							  0xffff, 0xffff,
+							  0xfff1, 0xffff,
+							  0xffff, 0xffff };
+VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
+							    0xfffffff1, 0xffffffff };
+
+int main (void)
+{
+#define TEST_VREINTERPRET(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED)	\
+  VECT_VAR(vreint_vector_res, T1, W, N) =				\
+    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
+		    VECT_VAR(vreint_vector_res, T1, W, N));		\
+  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+#define TEST_VREINTERPRET_FP(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+  VECT_VAR(vreint_vector_res, T1, W, N) =				\
+    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
+		    VECT_VAR(vreint_vector_res, T1, W, N));		\
+  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+  DECL_VARIABLE_ALL_VARIANTS(vreint_vector);
+  DECL_VARIABLE(vreint_vector, poly, 64, 1);
+  DECL_VARIABLE(vreint_vector, poly, 64, 2);
+  DECL_VARIABLE_ALL_VARIANTS(vreint_vector_res);
+  DECL_VARIABLE(vreint_vector_res, poly, 64, 1);
+  DECL_VARIABLE(vreint_vector_res, poly, 64, 2);
+
+  clean_results ();
+
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
+  VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
+  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
+  VLOAD(vreint_vector, buffer, , float, f, 32, 2);
+  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
+
+  /* vreinterpret_p64_* tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VREINTERPRET_P64_*"
+  TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 8, 8, vreint_expected_p64_s8);
+  TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 16, 4, vreint_expected_p64_s16);
+  TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 32, 2, vreint_expected_p64_s32);
+  TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 64, 1, vreint_expected_p64_s64);
+  TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 8, 8, vreint_expected_p64_u8);
+  TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 16, 4, vreint_expected_p64_u16);
+  TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 32, 2, vreint_expected_p64_u32);
+  TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
+  TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
+  TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
+  TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
+
+  /* vreinterpretq_p64_* tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VREINTERPRETQ_P64_*"
+  TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 8, 16, vreint_expected_q_p64_s8);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 16, 8, vreint_expected_q_p64_s16);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 32, 4, vreint_expected_q_p64_s32);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 64, 2, vreint_expected_q_p64_s64);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 8, 16, vreint_expected_q_p64_u8);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 16, 8, vreint_expected_q_p64_u16);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 32, 4, vreint_expected_q_p64_u32);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
+
+  /* vreinterpret_*_p64 tests.  */
+#undef TEST_MSG
+#define TEST_MSG "VREINTERPRET_*_P64"
+
+  TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 64, 1, vreint_expected_s8_p64);
+  TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 64, 1, vreint_expected_s16_p64);
+  TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 64, 1, vreint_expected_s32_p64);
+  TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 64, 1, vreint_expected_s64_p64);
+  TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 64, 1, vreint_expected_u8_p64);
+  TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 64, 1, vreint_expected_u16_p64);
+  TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 64, 1, vreint_expected_u32_p64);
+  TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
+  TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
+  TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
+  TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
+  TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
+  TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
+  TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 64, 2, vreint_expected_q_s32_p64);
+  TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 64, 2, vreint_expected_q_s64_p64);
+  TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 64, 2, vreint_expected_q_u8_p64);
+  TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 64, 2, vreint_expected_q_u16_p64);
+  TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 64, 2, vreint_expected_q_u32_p64);
+  TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
+  TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
+  TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
+  TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
+
+  return 0;
+}
-- 
1.9.1

[Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add
	missing tests for vreinterpretq_p{8,16}.

Change-Id: I7e9bb18c668c34685f12aa578868d7752232a96c

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index d4e5768..2570f73 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -371,6 +371,83 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
 VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
 						 0xfff7fff6fff5fff4 };
 
+
+/* Expected results for vreinterpretq_p8_xx.  */
+VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						0xf4, 0xf5, 0xf6, 0xf7,
+						0xf8, 0xf9, 0xfa, 0xfb,
+						0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_p8_2,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+						0xf2, 0xff, 0xf3, 0xff,
+						0xf4, 0xff, 0xf5, 0xff,
+						0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_p8_3,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+						0xf1, 0xff, 0xff, 0xff,
+						0xf2, 0xff, 0xff, 0xff,
+						0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_p8_4,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff,
+						0xf1, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_p8_5,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						0xf4, 0xf5, 0xf6, 0xf7,
+						0xf8, 0xf9, 0xfa, 0xfb,
+						0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_p8_6,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+						0xf2, 0xff, 0xf3, 0xff,
+						0xf4, 0xff, 0xf5, 0xff,
+						0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_p8_7,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+						0xf1, 0xff, 0xff, 0xff,
+						0xf2, 0xff, 0xff, 0xff,
+						0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_p8_8,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff,
+						0xf1, 0xff, 0xff, 0xff,
+						0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+						0xf2, 0xff, 0xf3, 0xff,
+						0xf4, 0xff, 0xf5, 0xff,
+						0xf6, 0xff, 0xf7, 0xff };
+
+/* Expected results for vreinterpretq_p16_xx.  */
+VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
+						 0xf5f4, 0xf7f6,
+						 0xf9f8, 0xfbfa,
+						 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_p16_2,poly,16,8) [] = { 0xfff0, 0xfff1,
+						 0xfff2, 0xfff3,
+						 0xfff4, 0xfff5,
+						 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_p16_3,poly,16,8) [] = { 0xfff0, 0xffff,
+						 0xfff1, 0xffff,
+						 0xfff2, 0xffff,
+						 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_p16_4,poly,16,8) [] = { 0xfff0, 0xffff,
+						 0xffff, 0xffff,
+						 0xfff1, 0xffff,
+						 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_p16_5,poly,16,8) [] = { 0xf1f0, 0xf3f2,
+						 0xf5f4, 0xf7f6,
+						 0xf9f8, 0xfbfa,
+						 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_p16_6,poly,16,8) [] = { 0xfff0, 0xfff1,
+						 0xfff2, 0xfff3,
+						 0xfff4, 0xfff5,
+						 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_p16_7,poly,16,8) [] = { 0xfff0, 0xffff,
+						 0xfff1, 0xffff,
+						 0xfff2, 0xffff,
+						 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_p16_8,poly,16,8) [] = { 0xfff0, 0xffff,
+						 0xffff, 0xffff,
+						 0xfff1, 0xffff,
+						 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
+						 0xf5f4, 0xf7f6,
+						 0xf9f8, 0xfbfa,
+						 0xfdfc, 0xfffe };
+
 /* Expected results for vreinterpret_f32_xx.  */
 VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_f32_2,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
@@ -685,6 +762,28 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
 
+  /* vreinterpretq_p8_xx.  */
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 16, 8, expected_q_p8_2);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 32, 4, expected_q_p8_3);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 64, 2, expected_q_p8_4);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 8, 16, expected_q_p8_5);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 16, 8, expected_q_p8_6);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
+
+  /* vreinterpretq_p16_xx.  */
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 16, 8, expected_q_p16_2);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 32, 4, expected_q_p16_3);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 64, 2, expected_q_p16_4);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 8, 16, expected_q_p16_5);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 16, 8, expected_q_p16_6);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
+
   /* vreinterpret_f32_xx.  */
   TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
   TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 16, 4, expected_f32_2);
-- 
1.9.1

[Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests.

[Christophe Lyon]

2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Add fp16 tests.

Change-Id: I64e30bc30a9a9cc5c47eff212e7d745bf3230fe7

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
index b923b64..282edd5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
@@ -14,6 +14,7 @@ VECT_VAR_DECL(expected_st2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
 VECT_VAR_DECL(expected_st2_0,poly,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
 VECT_VAR_DECL(expected_st2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -24,6 +25,8 @@ VECT_VAR_DECL(expected_st2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
 					       0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
 						 0x0, 0x0 };
 
@@ -39,6 +42,7 @@ VECT_VAR_DECL(expected_st2_1,uint,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,hfloat,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -48,6 +52,8 @@ VECT_VAR_DECL(expected_st2_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st2_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st2_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Expected results for vst3, chunk 0.  */
@@ -62,6 +68,7 @@ VECT_VAR_DECL(expected_st3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
 VECT_VAR_DECL(expected_st3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0 };
 VECT_VAR_DECL(expected_st3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
 VECT_VAR_DECL(expected_st3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -73,6 +80,8 @@ VECT_VAR_DECL(expected_st3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
 					       0xfffffff2, 0x0 };
 VECT_VAR_DECL(expected_st3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
 						 0xc1600000, 0x0 };
 
@@ -88,6 +97,7 @@ VECT_VAR_DECL(expected_st3_1,uint,32,2) [] = { 0xfffffff2, 0x0 };
 VECT_VAR_DECL(expected_st3_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_1,hfloat,32,2) [] = { 0xc1600000, 0x0 };
 VECT_VAR_DECL(expected_st3_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -97,6 +107,8 @@ VECT_VAR_DECL(expected_st3_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st3_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Expected results for vst3, chunk 2.  */
@@ -111,6 +123,7 @@ VECT_VAR_DECL(expected_st3_2,uint,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,hfloat,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -120,6 +133,8 @@ VECT_VAR_DECL(expected_st3_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st3_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st3_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Expected results for vst4, chunk 0.  */
@@ -134,6 +149,7 @@ VECT_VAR_DECL(expected_st4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
 VECT_VAR_DECL(expected_st4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_st4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
 VECT_VAR_DECL(expected_st4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
 VECT_VAR_DECL(expected_st4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -145,6 +161,8 @@ VECT_VAR_DECL(expected_st4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
 					       0xfffffff2, 0xfffffff3 };
 VECT_VAR_DECL(expected_st4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
 						 0xc1600000, 0xc1500000 };
 
@@ -160,6 +178,7 @@ VECT_VAR_DECL(expected_st4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
 VECT_VAR_DECL(expected_st4_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
 VECT_VAR_DECL(expected_st4_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -169,6 +188,8 @@ VECT_VAR_DECL(expected_st4_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st4_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Expected results for vst4, chunk 2.  */
@@ -183,6 +204,7 @@ VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -192,6 +214,8 @@ VECT_VAR_DECL(expected_st4_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st4_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+					       0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Expected results for vst4, chunk 3.  */
@@ -206,6 +230,7 @@ VECT_VAR_DECL(expected_st4_3,uint,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,hfloat,32,2) [] = { 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					      0x0, 0x0, 0x0, 0x0 };
@@ -215,6 +240,8 @@ VECT_VAR_DECL(expected_st4_3,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 VECT_VAR_DECL(expected_st4_3,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 					       0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+						 0x0, 0x0, 0x0, 0x0 };
 VECT_VAR_DECL(expected_st4_3,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 
 /* Declare additional input buffers as needed.  */
@@ -229,6 +256,7 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2);
 VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2);
 VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2);
 VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2);
 VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2);
 
 /* Input buffers for vld3_lane.  */
@@ -242,6 +270,7 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3);
 VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3);
 VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3);
 VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3);
 VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3);
 
 /* Input buffers for vld4_lane.  */
@@ -255,6 +284,7 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4);
 VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4);
 VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4);
 VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4);
 VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4);
 
 void exec_vstX_lane (void)
@@ -302,7 +332,7 @@ void exec_vstX_lane (void)
 
   /* We need all variants in 64 bits, but there is no 64x2 variant,
      nor 128 bits vectors of int8/uint8/poly8.  */
-#define DECL_ALL_VSTX_LANE(X)			\
+#define DECL_ALL_VSTX_LANE_NO_FP16(X)		\
   DECL_VSTX_LANE(int, 8, 8, X);			\
   DECL_VSTX_LANE(int, 16, 4, X);		\
   DECL_VSTX_LANE(int, 32, 2, X);		\
@@ -319,11 +349,20 @@ void exec_vstX_lane (void)
   DECL_VSTX_LANE(poly, 16, 8, X);		\
   DECL_VSTX_LANE(float, 32, 4, X)
 
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+#define DECL_ALL_VSTX_LANE(X)		\
+  DECL_ALL_VSTX_LANE_NO_FP16(X);	\
+  DECL_VSTX_LANE(float, 16, 4, X);	\
+  DECL_VSTX_LANE(float, 16, 8, X)
+#else
+#define DECL_ALL_VSTX_LANE(X) DECL_ALL_VSTX_LANE_NO_FP16(X)
+#endif
+
 #define DUMMY_ARRAY(V, T, W, N, L) VECT_VAR_DECL(V,T,W,N)[N*L]
 
   /* Use the same lanes regardless of the size of the array (X), for
      simplicity.  */
-#define TEST_ALL_VSTX_LANE(X)			\
+#define TEST_ALL_VSTX_LANE_NO_FP16(X)		\
   TEST_VSTX_LANE(, int, s, 8, 8, X, 7);		\
   TEST_VSTX_LANE(, int, s, 16, 4, X, 2);	\
   TEST_VSTX_LANE(, int, s, 32, 2, X, 0);	\
@@ -340,7 +379,16 @@ void exec_vstX_lane (void)
   TEST_VSTX_LANE(q, poly, p, 16, 8, X, 5);	\
   TEST_VSTX_LANE(q, float, f, 32, 4, X, 2)
 
-#define TEST_ALL_EXTRA_CHUNKS(X, Y)		\
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+#define TEST_ALL_VSTX_LANE(X)			\
+  TEST_ALL_VSTX_LANE_NO_FP16(X);		\
+  TEST_VSTX_LANE(, float, f, 16, 4, X, 2);	\
+  TEST_VSTX_LANE(q, float, f, 16, 8, X, 6)
+#else
+#define TEST_ALL_VSTX_LANE(X) TEST_ALL_VSTX_LANE_NO_FP16(X)
+#endif
+
+#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)	\
   TEST_EXTRA_CHUNK(int, 8, 8, X, Y);		\
   TEST_EXTRA_CHUNK(int, 16, 4, X, Y);		\
   TEST_EXTRA_CHUNK(int, 32, 2, X, Y);		\
@@ -357,6 +405,15 @@ void exec_vstX_lane (void)
   TEST_EXTRA_CHUNK(poly, 16, 8, X, Y);		\
   TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
 
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+#define TEST_ALL_EXTRA_CHUNKS(X,Y)		\
+  TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y);		\
+  TEST_EXTRA_CHUNK(float, 16, 4, X, Y);		\
+  TEST_EXTRA_CHUNK(float, 16, 8, X, Y)
+#else
+#define TEST_ALL_EXTRA_CHUNKS(X,Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)
+#endif
+
   /* Declare the temporary buffers / variables.  */
   DECL_ALL_VSTX_LANE(2);
   DECL_ALL_VSTX_LANE(3);
@@ -371,12 +428,18 @@ void exec_vstX_lane (void)
   DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
   DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
   DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  DUMMY_ARRAY(buffer_src, float, 16, 4, 4);
+#endif
   DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
   DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
   DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
   DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
   DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
   DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  DUMMY_ARRAY(buffer_src, float, 16, 8, 4);
+#endif
   DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
 
   /* Check vst2_lane/vst2q_lane.  */
@@ -400,6 +463,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_0, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_0, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_0, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_0, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(2, 1);
 #undef CMT
@@ -419,6 +486,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_1, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_1, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_1, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_1, CMT);
+#endif
 
 
   /* Check vst3_lane/vst3q_lane.  */
@@ -444,6 +515,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_0, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_0, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_0, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_0, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(3, 1);
 
@@ -464,6 +539,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_1, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_1, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_1, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_1, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(3, 2);
 
@@ -484,6 +563,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_2, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_2, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_2, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_2, CMT);
+#endif
 
 
   /* Check vst4_lane/vst4q_lane.  */
@@ -509,6 +592,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_0, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_0, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_0, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_0, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(4, 1);
 
@@ -529,6 +616,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_1, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_1, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_1, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_1, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(4, 2);
 
@@ -549,6 +640,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_2, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_2, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_2, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_2, CMT);
+#endif
 
   TEST_ALL_EXTRA_CHUNKS(4, 3);
 
@@ -569,6 +664,10 @@ void exec_vstX_lane (void)
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_3, CMT);
   CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_3, CMT);
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_3, CMT);
+  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_3, CMT);
+#endif
 }
 
 int main (void)
-- 
1.9.1

[Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[Christophe Lyon]

2016-05-04  Christophe Lyon  <christophe.lyon@linaro.org>

        * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
        * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
        * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.

Change-Id: Ic8061f1a5f3e042844a33a70c0f42a5f92c43c98

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 2570f73..0de2ab3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
 					    0xf4, 0xf5, 0xf6, 0xf7 };
 VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
 					    0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+					     0x00, 0xcb, 0x80, 0xca };
 
 /* Expected results for vreinterpret_s16_xx.  */
 VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
@@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
 VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
 VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
 VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
 
 /* Expected results for vreinterpret_s32_xx.  */
 VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
 VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
 VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
 
 /* Expected results for vreinterpret_s64_xx.  */
 VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
 VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
 VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
 VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
 
 /* Expected results for vreinterpret_u8_xx.  */
 VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
 					     0xf4, 0xf5, 0xf6, 0xf7 };
 VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
 					     0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+					      0x00, 0xcb, 0x80, 0xca };
 
 /* Expected results for vreinterpret_u16_xx.  */
 VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
@@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
 VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
 VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
 VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
 
 /* Expected results for vreinterpret_u32_xx.  */
 VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
 VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
 VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
 
 /* Expected results for vreinterpret_u64_xx.  */
 VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
 VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
 VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
 VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
 
 /* Expected results for vreinterpret_p8_xx.  */
 VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
 					     0xff, 0xff, 0xff, 0xff };
 VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
 					     0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_p8_10,poly,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+					      0x00, 0xcb, 0x80, 0xca };
 
 /* Expected results for vreinterpret_p16_xx.  */
 VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
@@ -138,6 +150,7 @@ VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
 VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
 VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
 VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_p16_10,poly,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
 
 /* Expected results for vreinterpretq_s8_xx.  */
 VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
@@ -176,6 +189,10 @@ VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
 					       0xf2, 0xff, 0xf3, 0xff,
 					       0xf4, 0xff, 0xf5, 0xff,
 					       0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_s8_10,int,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
+						0x00, 0xcb, 0x80, 0xca,
+						0x00, 0xca, 0x80, 0xc9,
+						0x00, 0xc9, 0x80, 0xc8 };
 
 /* Expected results for vreinterpretq_s16_xx.  */
 VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
@@ -214,6 +231,10 @@ VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
 						0xfff2, 0xfff3,
 						0xfff4, 0xfff5,
 						0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_s16_10,int,16,8) [] = { 0xcc00, 0xcb80,
+						 0xcb00, 0xca80,
+						 0xca00, 0xc980,
+						 0xc900, 0xc880 };
 
 /* Expected results for vreinterpretq_s32_xx.  */
 VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
@@ -234,6 +255,8 @@ VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
 						0xfbfaf9f8, 0xfffefdfc };
 VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
 						0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_s32_10,int,32,4) [] = { 0xcb80cc00, 0xca80cb00,
+						 0xc980ca00, 0xc880c900 };
 
 /* Expected results for vreinterpretq_s64_xx.  */
 VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
@@ -254,6 +277,8 @@ VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
 						0xfffefdfcfbfaf9f8 };
 VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
 						0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(expected_q_s64_10,int,64,2) [] = { 0xca80cb00cb80cc00,
+						 0xc880c900c980ca00 };
 
 /* Expected results for vreinterpretq_u8_xx.  */
 VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -292,6 +317,10 @@ VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
 						0xf2, 0xff, 0xf3, 0xff,
 						0xf4, 0xff, 0xf5, 0xff,
 						0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_u8_10,uint,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
+						 0x00, 0xcb, 0x80, 0xca,
+						 0x00, 0xca, 0x80, 0xc9,
+						 0x00, 0xc9, 0x80, 0xc8 };
 
 /* Expected results for vreinterpretq_u16_xx.  */
 VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
@@ -330,6 +359,10 @@ VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
 						 0xfff2, 0xfff3,
 						 0xfff4, 0xfff5,
 						 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_u16_10,uint,16,8) [] = { 0xcc00, 0xcb80,
+						  0xcb00, 0xca80,
+						  0xca00, 0xc980,
+						  0xc900, 0xc880 };
 
 /* Expected results for vreinterpretq_u32_xx.  */
 VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
@@ -350,6 +383,8 @@ VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
 						 0xfbfaf9f8, 0xfffefdfc };
 VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
 						 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_u32_10,uint,32,4) [] = { 0xcb80cc00, 0xca80cb00,
+						  0xc980ca00, 0xc880c900 };
 
 /* Expected results for vreinterpretq_u64_xx.  */
 VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
@@ -370,7 +405,8 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
 						0xfffefdfcfbfaf9f8 };
 VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
 						 0xfff7fff6fff5fff4 };
-
+VECT_VAR_DECL(expected_q_u64_10,uint,64,2) [] = { 0xca80cb00cb80cc00,
+						  0xc880c900c980ca00 };
 
 /* Expected results for vreinterpretq_p8_xx.  */
 VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -409,6 +445,10 @@ VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
 						0xf2, 0xff, 0xf3, 0xff,
 						0xf4, 0xff, 0xf5, 0xff,
 						0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_p8_10,poly,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
+						 0x00, 0xcb, 0x80, 0xca,
+						 0x00, 0xca, 0x80, 0xc9,
+						 0x00, 0xc9, 0x80, 0xc8 };
 
 /* Expected results for vreinterpretq_p16_xx.  */
 VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
@@ -447,6 +487,10 @@ VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
 						 0xf5f4, 0xf7f6,
 						 0xf9f8, 0xfbfa,
 						 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_p16_10,poly,16,8) [] = { 0xcc00, 0xcb80,
+						  0xcb00, 0xca80,
+						  0xca00, 0xc980,
+						  0xc900, 0xc880 };
 
 /* Expected results for vreinterpret_f32_xx.  */
 VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -459,6 +503,7 @@ VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
 VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
 VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_f32_11,hfloat,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
 
 /* Expected results for vreinterpretq_f32_xx.  */
 VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
@@ -481,6 +526,8 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
 						   0xfbfaf9f8, 0xfffefdfc };
 VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
 						    0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_f32_11,hfloat,32,4) [] = { 0xcb80cc00, 0xca80cb00,
+						    0xc980ca00, 0xc880c900 };
 
 /* Expected results for vreinterpret_xx_f32.  */
 VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
@@ -496,6 +543,7 @@ VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
 VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
 						 0x0, 0x0, 0x70, 0xc1 };
 VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+VECT_VAR_DECL(expected_xx_f32_11,hfloat,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
 
 /* Expected results for vreinterpretq_xx_f32.  */
 VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
@@ -524,6 +572,62 @@ VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
 						    0x0, 0x0, 0x50, 0xc1 };
 VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
 						     0x0, 0xc160, 0x0, 0xc150 };
+VECT_VAR_DECL(expected_q_xx_f32_11,hfloat,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+						      0x0, 0xc160, 0x0, 0xc150 };
+
+/* Expected results for vreinterpret_f16_xx.  */
+VECT_VAR_DECL(expected_f16_1,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_f16_2,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_f16_3,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_f16_4,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_f16_5,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_f16_6,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_f16_7,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_f16_8,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_f16_9,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_f16_10,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+
+/* Expected results for vreinterpretq_f16_xx.  */
+VECT_VAR_DECL(expected_q_f16_1,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
+						   0xf5f4, 0xf7f6,
+						   0xf9f8, 0xfbfa,
+						   0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_f16_2,hfloat,16,8) [] = { 0xfff0, 0xfff1,
+						   0xfff2, 0xfff3,
+						   0xfff4, 0xfff5,
+						   0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_f16_3,hfloat,16,8) [] = { 0xfff0, 0xffff,
+						   0xfff1, 0xffff,
+						   0xfff2, 0xffff,
+						   0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_f16_4,hfloat,16,8) [] = { 0xfff0, 0xffff,
+						   0xffff, 0xffff,
+						   0xfff1, 0xffff,
+						   0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_f16_5,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
+						   0xf5f4, 0xf7f6,
+						   0xf9f8, 0xfbfa,
+						   0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_f16_6,hfloat,16,8) [] = { 0xfff0, 0xfff1,
+						   0xfff2, 0xfff3,
+						   0xfff4, 0xfff5,
+						   0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_f16_7,hfloat,16,8) [] = { 0xfff0, 0xffff,
+						   0xfff1, 0xffff,
+						   0xfff2, 0xffff,
+						   0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_f16_8,hfloat,16,8) [] = { 0xfff0, 0xffff,
+						   0xffff, 0xffff,
+						   0xfff1, 0xffff,
+						   0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_f16_9,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
+						   0xf5f4, 0xf7f6,
+						   0xf9f8, 0xfbfa,
+						   0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_f16_10,hfloat,16,8) [] = { 0xfff0, 0xfff1,
+						    0xfff2, 0xfff3,
+						    0xfff4, 0xfff5,
+						    0xfff6, 0xfff7 };
 
 #define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
 
@@ -561,7 +665,9 @@ void exec_vreinterpret (void)
 
   /* Initialize input "vector" from "buffer".  */
   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+  VLOAD(vector, buffer, , float, f, 16, 4);
   VLOAD(vector, buffer, , float, f, 32, 2);
+  VLOAD(vector, buffer, q, float, f, 16, 8);
   VLOAD(vector, buffer, q, float, f, 32, 4);
 
   /* vreinterpret_s8_xx.  */
@@ -574,6 +680,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
+  TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10);
 
   /* vreinterpret_s16_xx.  */
   TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
@@ -585,6 +692,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
+  TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10);
 
   /* vreinterpret_s32_xx.  */
   TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
@@ -596,6 +704,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
+  TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10);
 
   /* vreinterpret_s64_xx.  */
   TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
@@ -607,6 +716,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
+  TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10);
 
   /* vreinterpret_u8_xx.  */
   TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
@@ -618,6 +728,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
+  TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10);
 
   /* vreinterpret_u16_xx.  */
   TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
@@ -629,6 +740,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
+  TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10);
 
   /* vreinterpret_u32_xx.  */
   TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
@@ -640,6 +752,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
+  TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10);
 
   /* vreinterpret_u64_xx.  */
   TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
@@ -651,6 +764,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
+  TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10);
 
   /* vreinterpret_p8_xx.  */
   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
@@ -662,6 +776,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
+  TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10);
 
   /* vreinterpret_p16_xx.  */
   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
@@ -673,6 +788,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
+  TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10);
 
   /* vreinterpretq_s8_xx.  */
   TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
@@ -684,6 +800,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
+  TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10);
 
   /* vreinterpretq_s16_xx.  */
   TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
@@ -695,6 +812,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
+  TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10);
 
   /* vreinterpretq_s32_xx.  */
   TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
@@ -706,6 +824,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
+  TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10);
 
   /* vreinterpretq_s64_xx.  */
   TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
@@ -717,6 +836,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
+  TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10);
 
   /* vreinterpretq_u8_xx.  */
   TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
@@ -728,6 +848,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
+  TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10);
 
   /* vreinterpretq_u16_xx.  */
   TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
@@ -739,6 +860,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
+  TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10);
 
   /* vreinterpretq_u32_xx.  */
   TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
@@ -750,6 +872,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
+  TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10);
 
   /* vreinterpretq_u64_xx.  */
   TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
@@ -761,6 +884,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
+  TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10);
 
   /* vreinterpretq_p8_xx.  */
   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
@@ -772,6 +896,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
+  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10);
 
   /* vreinterpretq_p16_xx.  */
   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
@@ -783,6 +908,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
+  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10);
 
   /* vreinterpret_f32_xx.  */
   TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
@@ -795,6 +921,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
+  TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11);
 
   /* vreinterpretq_f32_xx.  */
   TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
@@ -807,6 +934,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
+  TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11);
 
   /* vreinterpret_xx_f32.  */
   TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
@@ -819,6 +947,7 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11);
 
   /* vreinterpretq_xx_f32.  */
   TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
@@ -831,6 +960,31 @@ void exec_vreinterpret (void)
   TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11);
+
+  /* vreinterpret_f16_xx.  */
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 8, 8, expected_f16_1);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 16, 4, expected_f16_2);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 32, 2, expected_f16_3);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 64, 1, expected_f16_4);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 8, 8, expected_f16_5);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 16, 4, expected_f16_6);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 32, 2, expected_f16_7);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 64, 1, expected_f16_8);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 8, 8, expected_f16_9);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 16, 4, expected_f16_10);
+
+  /* vreinterpretq_f16_xx.  */
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 8, 16, expected_q_f16_1);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 16, 8, expected_q_f16_2);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 32, 4, expected_q_f16_3);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 64, 2, expected_q_f16_4);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 8, 16, expected_q_f16_5);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 16, 8, expected_q_f16_6);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 32, 4, expected_q_f16_7);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10);
 }
 
 int main (void)
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
index a049cb3..8ba5272 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
@@ -30,6 +30,8 @@ VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
 							   0xfff7fff6fff5fff4 };
 VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
 							   0xc1500000c1600000 };
+VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
+							   0xc880c900c980ca00 };
 
 /* Expected results: vreinterpretq_*_p128.  */
 VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
@@ -68,6 +70,10 @@ VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
 							   0xfffffffffffffff1 };
 VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
 							     0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
+							     0xffff, 0xffff,
+							     0xfff1, 0xffff,
+							     0xffff, 0xffff };
 
 int main (void)
 {
@@ -80,6 +86,7 @@ int main (void)
 
   TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
   VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
+  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
   VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
 
   /* vreinterpretq_p128_* tests.  */
@@ -108,6 +115,7 @@ int main (void)
   TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
   TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
   TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16);
   TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
 
   /* vreinterpretq_*_p128 tests.  */
@@ -145,6 +153,7 @@ int main (void)
   TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
   TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
   TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
+  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128);
   TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
index 79f3cd6..b000797 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
@@ -19,6 +19,7 @@ VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
 VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
 VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
 VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
+VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 };
 
 /* Expected results: vreinterpretq_p64_*.  */
 VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
@@ -43,6 +44,8 @@ VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
 							  0xfff7fff6fff5fff4 };
 VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
 							  0xc1500000c1600000 };
+VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
+							  0xc880c900c980ca00 };
 
 /* Expected results: vreinterpret_*_p64.  */
 VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
@@ -59,6 +62,7 @@ VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
 						      0xff, 0xff, 0xff, 0xff };
 VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
 VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
 
 /* Expected results: vreinterpretq_*_p64.  */
 VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
@@ -95,6 +99,10 @@ VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
 							  0xffff, 0xffff };
 VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
 							    0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff,
+							    0xffff, 0xffff,
+							    0xfff1, 0xffff,
+							    0xffff, 0xffff };
 
 int main (void)
 {
@@ -124,6 +132,8 @@ int main (void)
   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
   VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
   VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
+  VLOAD(vreint_vector, buffer, , float, f, 16, 4);
+  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
   VLOAD(vreint_vector, buffer, , float, f, 32, 2);
   VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
 
@@ -140,6 +150,7 @@ int main (void)
   TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
   TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
   TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
+  TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16);
   TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
 
   /* vreinterpretq_p64_* tests.  */
@@ -155,6 +166,7 @@ int main (void)
   TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
   TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
   TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
+  TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16);
   TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
 
   /* vreinterpret_*_p64 tests.  */
@@ -171,6 +183,7 @@ int main (void)
   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
   TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
   TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
+  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64);
   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
@@ -182,6 +195,7 @@ int main (void)
   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
   TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
   TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
+  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64);
   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
 
   return 0;
-- 
1.9.1

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Jiong Wang]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.
>
> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 0000000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnd
> +#define TEST_MSG "VRND"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> new file mode 100644
> index 0000000..629240d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> @@ -0,0 +1,43 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1 (NAME)
> +
> +void FNNAME (INSN) (void)
> +{
> +  /* vector_res = vrndX (vector), then store the result.  */
> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
> +  VECT_VAR (vector_res, T1, W, N) =					\
> +    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
> +    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
> +		       VECT_VAR (vector_res, T1, W, N))
> +
> +  /* Two auxliary macros are necessary to expand INSN.  */
> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
> +
> +#define TEST_VRND(Q, T1, T2, W, N)		\
> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
> +
> +  DECL_VARIABLE (vector, float, 32, 2);
> +  DECL_VARIABLE (vector, float, 32, 4);
> +
> +  DECL_VARIABLE (vector_res, float, 32, 2);
> +  DECL_VARIABLE (vector_res, float, 32, 4);
> +
> +  clean_results ();
> +
> +  VLOAD (vector, buffer, , float, f, 32, 2);
> +  VLOAD (vector, buffer, q, float, f, 32, 4);
> +
> +  TEST_VRND ( , float, f, 32, 2);
> +  TEST_VRND (q, float, f, 32, 4);
> +
> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int
> +main (void)
> +{
> +  FNNAME (INSN) ();
> +  return 0;
> +}
>

Hi Christophe,

   I have a question on how test inputs are selected?

   For example vrndm is round to integral, towards minus infinity while 
vrnda is to nearest with ties to even, has these differences been tested?

   Thanks.

Regards,
Jiong

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Christophe Lyon]

On 12 May 2016 at 10:45, Jiong Wang <jiong.wang@foss.arm.com> wrote:
>
>
> On 11/05/16 14:23, Christophe Lyon wrote:
>>
>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc:
>> New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
>> New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
>> New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
>> New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
>> New.
>>         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
>> New.
>>
>> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> new file mode 100644
>> index 0000000..5f492d4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> @@ -0,0 +1,16 @@
>> +/* { dg-require-effective-target arm_v8_neon_ok } */
>> +/* { dg-add-options arm_v8_neon } */
>> +
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results.  */
>> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
>> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
>> +                                              0xc1600000, 0xc1500000 };
>> +
>> +#define INSN vrnd
>> +#define TEST_MSG "VRND"
>> +
>> +#include "vrndX.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> new file mode 100644
>> index 0000000..629240d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> @@ -0,0 +1,43 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1 (NAME)
>> +
>> +void FNNAME (INSN) (void)
>> +{
>> +  /* vector_res = vrndX (vector), then store the result.  */
>> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)                              \
>> +  VECT_VAR (vector_res, T1, W, N) =                                    \
>> +    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));                   \
>> +    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),                    \
>> +                      VECT_VAR (vector_res, T1, W, N))
>> +
>> +  /* Two auxliary macros are necessary to expand INSN.  */
>> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)      \
>> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
>> +
>> +#define TEST_VRND(Q, T1, T2, W, N)             \
>> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
>> +
>> +  DECL_VARIABLE (vector, float, 32, 2);
>> +  DECL_VARIABLE (vector, float, 32, 4);
>> +
>> +  DECL_VARIABLE (vector_res, float, 32, 2);
>> +  DECL_VARIABLE (vector_res, float, 32, 4);
>> +
>> +  clean_results ();
>> +
>> +  VLOAD (vector, buffer, , float, f, 32, 2);
>> +  VLOAD (vector, buffer, q, float, f, 32, 4);
>> +
>> +  TEST_VRND ( , float, f, 32, 2);
>> +  TEST_VRND (q, float, f, 32, 4);
>> +
>> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
>> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
>> +}
>> +
>> +int
>> +main (void)
>> +{
>> +  FNNAME (INSN) ();
>> +  return 0;
>> +}
>>
>
> Hi Christophe,
>
>   I have a question on how test inputs are selected?
>
>   For example vrndm is round to integral, towards minus infinity while vrnda
> is to nearest with ties to even, has these differences been tested?
>

Hi Jiong,

For this particular case, no, I didn't specifically chose input values to check
these differences.

This can be done as a follow-up?

Thanks,

Christophe

>   Thanks.
>
> Regards,
> Jiong

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Jiong Wang]

On 12/05/16 13:56, Christophe Lyon wrote:
> On 12 May 2016 at 10:45, Jiong Wang <jiong.wang@foss.arm.com> wrote:
>>
>> On 11/05/16 14:23, Christophe Lyon wrote:
>>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>>
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc:
>>> New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
>>> New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
>>> New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
>>> New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
>>> New.
>>>          * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
>>> New.
>>>
>>> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> new file mode 100644
>>> index 0000000..5f492d4
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> @@ -0,0 +1,16 @@
>>> +/* { dg-require-effective-target arm_v8_neon_ok } */
>>> +/* { dg-add-options arm_v8_neon } */
>>> +
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +/* Expected results.  */
>>> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
>>> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
>>> +                                              0xc1600000, 0xc1500000 };
>>> +
>>> +#define INSN vrnd
>>> +#define TEST_MSG "VRND"
>>> +
>>> +#include "vrndX.inc"
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>>> new file mode 100644
>>> index 0000000..629240d
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>>> @@ -0,0 +1,43 @@
>>> +#define FNNAME1(NAME) exec_ ## NAME
>>> +#define FNNAME(NAME) FNNAME1 (NAME)
>>> +
>>> +void FNNAME (INSN) (void)
>>> +{
>>> +  /* vector_res = vrndX (vector), then store the result.  */
>>> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)                              \
>>> +  VECT_VAR (vector_res, T1, W, N) =                                    \
>>> +    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));                   \
>>> +    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),                    \
>>> +                      VECT_VAR (vector_res, T1, W, N))
>>> +
>>> +  /* Two auxliary macros are necessary to expand INSN.  */
>>> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)      \
>>> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
>>> +
>>> +#define TEST_VRND(Q, T1, T2, W, N)             \
>>> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
>>> +
>>> +  DECL_VARIABLE (vector, float, 32, 2);
>>> +  DECL_VARIABLE (vector, float, 32, 4);
>>> +
>>> +  DECL_VARIABLE (vector_res, float, 32, 2);
>>> +  DECL_VARIABLE (vector_res, float, 32, 4);
>>> +
>>> +  clean_results ();
>>> +
>>> +  VLOAD (vector, buffer, , float, f, 32, 2);
>>> +  VLOAD (vector, buffer, q, float, f, 32, 4);
>>> +
>>> +  TEST_VRND ( , float, f, 32, 2);
>>> +  TEST_VRND (q, float, f, 32, 4);
>>> +
>>> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
>>> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
>>> +}
>>> +
>>> +int
>>> +main (void)
>>> +{
>>> +  FNNAME (INSN) ();
>>> +  return 0;
>>> +}
>>>
>> Hi Christophe,
>>
>>    I have a question on how test inputs are selected?
>>
>>    For example vrndm is round to integral, towards minus infinity while vrnda
>> is to nearest with ties to even, has these differences been tested?
>>
> Hi Jiong,
>
> For this particular case, no, I didn't specifically chose input values to check
> these differences.
>
> This can be done as a follow-up?

I think it's fine as this patch series itself is anyway a step forward 
on making sure all intrinsics are tested.

Thanks.

Regards,
Jiong

Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:51PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in comment.

This one would have been OK to commit as obvious.

OK for trunk.

Thanks,
James

Re: [Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:52PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vmul.c: Remove useless #ifdef.
> 	* gcc.target/aarch64/advsimd-intrinsics/vshl.c: Likewise.
> 	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.

OK.

Thanks,
James

Re: [Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:53PM +0200, Christophe Lyon wrote:
> It is useful to have more detailed information in the logs when checking
> validation results: instead of repeating the intrinsic name, we now print
> its return type too.
> 
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK,
> 	CHECK_FP, CHECK_CUMULATIVE_SAT): Print which type was checked.

OK.

Thanks,
James
 

Re: [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:54PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for vsliq_n_u64.
> 

And vsliq_n_s64 ?

OK with that change.

Thanks,
James

> Change-Id: I90bb2b225ffd7bfd54a0827a0264ac20271f54f2
> 
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
> index 0285083..e5f78d0 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
> @@ -169,6 +169,7 @@ void vsli_extra(void)
>    CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
>    CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
>    CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
> +  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
>    CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
>    CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
>  }
> -- 
> 1.9.1
> 

Re: [Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:55PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add
> 	missing tests for vreinterpretq_p{8,16}.

OK.

Thanks,
James

Re: [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test.

[Christophe Lyon]

On 13 May 2016 at 16:08, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> On Wed, May 11, 2016 at 03:23:54PM +0200, Christophe Lyon wrote:
>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>
>>       * gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for vsliq_n_u64.
>>
>
> And vsliq_n_s64 ?
>
Damn! You are right, I missed that one.

> OK with that change.
OK thanks

> Thanks,
> James
>
>> Change-Id: I90bb2b225ffd7bfd54a0827a0264ac20271f54f2
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>> index 0285083..e5f78d0 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>> @@ -169,6 +169,7 @@ void vsli_extra(void)
>>    CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
>>    CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
>>    CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
>> +  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
>>    CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
>>    CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
>>  }
>> --
>> 1.9.1
>>
>

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
> 	for vtst_p8 and vtstq_p8.

And vtst_p16 and vtstq_p16 too please.

vtst_s64
vtstq_s64
vtst_u64
vtstq_u64 are also missing (AArch64 only).

Thanks,
James

> 
> Change-Id: Id555a9b3214945506a106e2465b42d38bf76a3a7
> 
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> index 9e74ffb..4c7ee79 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> @@ -32,6 +32,14 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
>  VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
>  						  0x0, 0xffffffff };
>  
> +/* Expected results with poly input.  */
> +VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
> +					     0xff, 0xff, 0xff, 0xff };
> +VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
> +					      0xff, 0xff, 0xff, 0xff,
> +					      0xff, 0xff, 0xff, 0xff,
> +					      0xff, 0xff, 0xff, 0xff };
> +
>  #define INSN_NAME vtst
>  #define TEST_MSG "VTST/VTSTQ"
>  
> @@ -71,12 +79,14 @@ FNNAME (INSN_NAME)
>    VDUP(vector2, , uint, u, 8, 8, 15);
>    VDUP(vector2, , uint, u, 16, 4, 5);
>    VDUP(vector2, , uint, u, 32, 2, 1);
> +  VDUP(vector2, , poly, p, 8, 8, 15);
>    VDUP(vector2, q, int, s, 8, 16, 15);
>    VDUP(vector2, q, int, s, 16, 8, 5);
>    VDUP(vector2, q, int, s, 32, 4, 1);
>    VDUP(vector2, q, uint, u, 8, 16, 15);
>    VDUP(vector2, q, uint, u, 16, 8, 5);
>    VDUP(vector2, q, uint, u, 32, 4, 1);
> +  VDUP(vector2, q, poly, p, 8, 16, 15);
>  
>  #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
>    MACRO(VAR, , T1, T2, 8, 8);					\
> @@ -109,6 +119,14 @@ FNNAME (INSN_NAME)
>    CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
>    CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
>    CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
> +
> +  /* Now, test the variants with poly8 as input.  */
> +#undef CMT
> +#define CMT " (poly input)"
> +  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
> +  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
> +  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
> +  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
>  }
>  
>  int main (void)
> -- 
> 1.9.1
> 

Re: [Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:57PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add fp16 tests.

OK.

Thanks,
James

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[Christophe Lyon]

On 13 May 2016 at 16:37, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote:
>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>
>>       * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
>>       for vtst_p8 and vtstq_p8.
>
> And vtst_p16 and vtstq_p16 too please.
>
> vtst_s64
> vtstq_s64
> vtst_u64
> vtstq_u64 are also missing (AArch64 only).
>
vtst_p16/vtstq_p16 are AArch64 only too, right?

My introduction message was not clear enough: this series
only attempts to fully cover AArch32 intrinsics.

There are many more missing for AArch64.


> Thanks,
> James
>
>>
>> Change-Id: Id555a9b3214945506a106e2465b42d38bf76a3a7
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
>> index 9e74ffb..4c7ee79 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
>> @@ -32,6 +32,14 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
>>  VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
>>                                                 0x0, 0xffffffff };
>>
>> +/* Expected results with poly input.  */
>> +VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
>> +                                          0xff, 0xff, 0xff, 0xff };
>> +VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
>> +                                           0xff, 0xff, 0xff, 0xff,
>> +                                           0xff, 0xff, 0xff, 0xff,
>> +                                           0xff, 0xff, 0xff, 0xff };
>> +
>>  #define INSN_NAME vtst
>>  #define TEST_MSG "VTST/VTSTQ"
>>
>> @@ -71,12 +79,14 @@ FNNAME (INSN_NAME)
>>    VDUP(vector2, , uint, u, 8, 8, 15);
>>    VDUP(vector2, , uint, u, 16, 4, 5);
>>    VDUP(vector2, , uint, u, 32, 2, 1);
>> +  VDUP(vector2, , poly, p, 8, 8, 15);
>>    VDUP(vector2, q, int, s, 8, 16, 15);
>>    VDUP(vector2, q, int, s, 16, 8, 5);
>>    VDUP(vector2, q, int, s, 32, 4, 1);
>>    VDUP(vector2, q, uint, u, 8, 16, 15);
>>    VDUP(vector2, q, uint, u, 16, 8, 5);
>>    VDUP(vector2, q, uint, u, 32, 4, 1);
>> +  VDUP(vector2, q, poly, p, 8, 16, 15);
>>
>>  #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)   \
>>    MACRO(VAR, , T1, T2, 8, 8);                                        \
>> @@ -109,6 +119,14 @@ FNNAME (INSN_NAME)
>>    CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
>>    CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
>>    CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
>> +
>> +  /* Now, test the variants with poly8 as input.  */
>> +#undef CMT
>> +#define CMT " (poly input)"
>> +  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
>> +  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
>> +  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
>> +  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
>>  }
>>
>>  int main (void)
>> --
>> 1.9.1
>>
>

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[James Greenhalgh]

On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote:
> On 13 May 2016 at 16:37, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> > On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote:
> >> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> >>
> >>       * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
> >>       for vtst_p8 and vtstq_p8.
> >
> > And vtst_p16 and vtstq_p16 too please.
> >
> > vtst_s64
> > vtstq_s64
> > vtst_u64
> > vtstq_u64 are also missing (AArch64 only).
> >
> vtst_p16/vtstq_p16 are AArch64 only too, right?

Not in my copy of:

  http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf

I see it is missing from config/arm/arm_neon.h so that's a bug in the GCC
implementation. It should be easy to resolve, map it to the same place
as vtst_u16 and vtst_s16 - this is just a bit operation which takes no
semantics from the data-type.

Would you mind spinning the fix for that and committing it before this
patch?

> My introduction message was not clear enough: this series
> only attempts to fully cover AArch32 intrinsics.

Understood, sorry for the extra noise.

Thanks,
James

Re: [Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:58PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Add fp16 tests.

OK.

Thanks,
James

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:59PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.

This is OK in lines with how we test the other intrinsics in this
directory (we haven't really tried to hit corner cases elsewhere). 

Thanks,
James

> 
> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
> 
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 0000000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnd
> +#define TEST_MSG "VRND"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> new file mode 100644
> index 0000000..629240d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> @@ -0,0 +1,43 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1 (NAME)
> +
> +void FNNAME (INSN) (void)
> +{
> +  /* vector_res = vrndX (vector), then store the result.  */
> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
> +  VECT_VAR (vector_res, T1, W, N) =					\
> +    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
> +    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
> +		       VECT_VAR (vector_res, T1, W, N))
> +
> +  /* Two auxliary macros are necessary to expand INSN.  */
> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
> +
> +#define TEST_VRND(Q, T1, T2, W, N)		\
> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
> +
> +  DECL_VARIABLE (vector, float, 32, 2);
> +  DECL_VARIABLE (vector, float, 32, 4);
> +
> +  DECL_VARIABLE (vector_res, float, 32, 2);
> +  DECL_VARIABLE (vector_res, float, 32, 4);
> +
> +  clean_results ();
> +
> +  VLOAD (vector, buffer, , float, f, 32, 2);
> +  VLOAD (vector, buffer, q, float, f, 32, 4);
> +
> +  TEST_VRND ( , float, f, 32, 2);
> +  TEST_VRND (q, float, f, 32, 4);
> +
> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int
> +main (void)
> +{
> +  FNNAME (INSN) ();
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> new file mode 100644
> index 0000000..816fd28d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnda
> +#define TEST_MSG "VRNDA"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> new file mode 100644
> index 0000000..029880c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndm
> +#define TEST_MSG "VRNDM"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> new file mode 100644
> index 0000000..571243c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndn
> +#define TEST_MSG "VRNDN"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> new file mode 100644
> index 0000000..ff4771c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndp
> +#define TEST_MSG "VRNDP"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> new file mode 100644
> index 0000000..ff2357b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndx
> +#define TEST_MSG "VRNDX"
> +
> +#include "vrndX.inc"
> -- 
> 1.9.1
> 

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result):
> 	Add poly64x1_t and poly64x2_t cases if supported.
> 	* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
> 	(buffer, buffer_pad, buffer_dup, buffer_dup_pad): Likewise.
> 	* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: New file.
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: New file.
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: New file.
> 

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
> @@ -0,0 +1,665 @@
> +/* This file contains tests for all the *p64 intrinsics, except for
> +   vreinterpret which have their own testcase.  */
> +
> +/* { dg-require-effective-target arm_crypto_ok } */
> +/* { dg-add-options arm_crypto } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results: vbsl.  */
> +VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
> +VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
> +					      0xfffffff1 };
> +
> +/* Expected results: vceq.  */
> +VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };

vceqq_p64
vceqz_p64
vceqzq_p64
vtst_p64
vtstq_p64

are missing, but will not be trivial to add. Could you raise a bug report
(or fix it if you like :-) )?

This is OK without a fix for those intrinsics with a suitable bug report
opened.

Thanks,
James

Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:24:01PM +0200, Christophe Lyon wrote:
> 2016-05-04  Christophe Lyon  <christophe.lyon@linaro.org>
> 
>         * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
>         * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
>         * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.

OK.

Thanks,
James

Re: [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update

[James Greenhalgh]

On Wed, May 11, 2016 at 03:23:50PM +0200, Christophe Lyon wrote:
> Hi,
> 
> A few months ago, we decided it was time to remove neon-testgen.ml
> and its generated tests. I did it, just to realize too late that
> some intrinsics were not covered anymore, so I reverted the removal.
> 
> This patch series performs a little bit of cleanup and adds the
> missing tests to cover all what is defined in arm_neon.h for AArch32.
> 
> Globally, this consists in adding tests for:
> - missing poly8 and poly16 for vreinterpret and vtst
> - fp16 tests for vget_lane, vstX_lane and vreinterpret
> - armv8 vrnd{,a,m,n,p,x}
> - tests for poly64 and poly128 intrinsics
> 
> Some intrinsics are not covered in aarch64/advsimd-intrinsics, but in
> arm/crypto: vldrq, vstrq, vaes, vsha1, vsha256, vmull_p64,
> vmull_high_p64.
> 
> Patches 1-4 are cleanup.
> Patch 5 adds the missing poly8 and poly16 tests for vreinterpret.
> Patch 6 adds the missing tests for vtst_p8 and vtstq_p8.
> Patches 7,8, 11 add the missing fp16 tests
> Patch 9 adds armv8 vrnd{,a,m,n,p,x} tests
> Patch 10 adds tests for poly64 and poly128 operations
> 
> I've checked the coverage by building the list of intrinsics tested
> via neon-testgen.ml, the list of intrinsics defined in arm_neon.h, and
> running the advsimd-intrinsics.exp tests with -save-temps to gather
> the list of actually tested intrinsics.
> 
> This series partly addresses PR 70369 which I created to keep track
> of these missing intrinsics tests: several AArch64 AdvSIMD intrinsics
> are still missing tests.
> 
> Tested with QEMU on arm* and aarch64*, with no regression, and
> several new PASSes.
> 
> OK for trunk?

D'oh, I wasn't thinking when I started OKing these, but obviously I only
have the privilege to OK them from an AArch64 perspective.

If it isn't too late, please wait for someone from the ARM port to give
their blessing before committing them.

Sorry to the ARM maintainers for forgetting to be explicit about that in
my earlier emails.

Thanks,
James

Re: [Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/vmul.c: Remove useless #ifdef.
> 	* gcc.target/aarch64/advsimd-intrinsics/vshl.c: Likewise.
> 	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.

Ok.
Thanks,
Kyrill

> Change-Id: I1b00b8edc4db6e6457be5bc1f92e8b6e218da644
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
> index 0cbb656..63f0d8d 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
> @@ -37,10 +37,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e,
>   VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000,
>   					   0xc4ae4ccd, 0xc4a1d999 };
>   
> -#ifndef INSN_NAME
>   #define INSN_NAME vmul
>   #define TEST_MSG "VMUL"
> -#endif
>   
>   #define FNNAME1(NAME) exec_ ## NAME
>   #define FNNAME(NAME) FNNAME1(NAME)
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
> index 821c11e..e8a57a4 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
> @@ -101,10 +101,8 @@ VECT_VAR_DECL(expected_negative_shift,uint,64,2) [] = { 0x7ffffffffffffff,
>   							0x7ffffffffffffff };
>   
>   
> -#ifndef INSN_NAME
>   #define INSN_NAME vshl
>   #define TEST_MSG "VSHL/VSHLQ"
> -#endif
>   
>   #define FNNAME1(NAME) exec_ ## NAME
>   #define FNNAME(NAME) FNNAME1(NAME)
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> index 7f96540..9e74ffb 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
> @@ -32,10 +32,8 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
>   VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
>   						  0x0, 0xffffffff };
>   
> -#ifndef INSN_NAME
>   #define INSN_NAME vtst
>   #define TEST_MSG "VTST/VTSTQ"
> -#endif
>   
>   /* We can't use the standard ref_v_binary_op.c template because vtst
>      has no 64 bits variant, and outputs are always of uint type.  */

Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in comment.

Ok (I agree it's obvious)

Thanks,
Kyrill

> Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> index 9e45e25..d4e5768 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> @@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
>   VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
>   						    0xfff5fff4, 0xfff7fff6 };
>   
> -/* Expected results for vreinterpretq_xx_f32.  */
> +/* Expected results for vreinterpret_xx_f32.  */
>   VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
>   						0x0, 0x0, 0x70, 0xc1 };
>   VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };

Re: [Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> It is useful to have more detailed information in the logs when checking
> validation results: instead of repeating the intrinsic name, we now print
> its return type too.

Ok.
Thanks,
Kyrill

> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK,
> 	CHECK_FP, CHECK_CUMULATIVE_SAT): Print which type was checked.
>
> Change-Id: I74759d6a211cf52962f860fe77653a6f6edc1848
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> index 49fbd84..a2c160c 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> @@ -81,7 +81,7 @@ extern size_t strlen(const char *);
>   	  abort();							\
>   	}								\
>         }									\
> -    fprintf(stderr, "CHECKED %s\n", MSG);				\
> +    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
>     }
>   
>   /* Floating-point variant.  */
> @@ -110,7 +110,7 @@ extern size_t strlen(const char *);
>   	  abort();							\
>   	}								\
>         }									\
> -    fprintf(stderr, "CHECKED %s\n", MSG);				\
> +    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
>     }
>   
>   /* Clean buffer with a non-zero pattern to help diagnose buffer
> @@ -335,7 +335,8 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
>   	      strlen(COMMENT) > 0 ? " " COMMENT : "");			\
>         abort();								\
>       }									\
> -    fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG);		\
> +    fprintf(stderr, "CHECKED CUMULATIVE SAT %s %s\n",			\
> +	    STR(VECT_TYPE(T, W, N)), MSG);				\
>     }
>   
>   #define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment)		\

Re: [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test.

[Kyrill Tkachov]

On 13/05/16 15:22, Christophe Lyon wrote:
> On 13 May 2016 at 16:08, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>> On Wed, May 11, 2016 at 03:23:54PM +0200, Christophe Lyon wrote:
>>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>>
>>>        * gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for vsliq_n_u64.
>>>
>> And vsliq_n_s64 ?
>>
> Damn! You are right, I missed that one.
>
>> OK with that change.
> OK thanks
>

Ok by me too with that change.

Thanks,
Kyrill

>> Thanks,
>> James
>>
>>> Change-Id: I90bb2b225ffd7bfd54a0827a0264ac20271f54f2
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>>> index 0285083..e5f78d0 100644
>>> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
>>> @@ -169,6 +169,7 @@ void vsli_extra(void)
>>>     CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
>>>     CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
>>>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
>>> +  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
>>>     CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
>>>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
>>>   }
>>> --
>>> 1.9.1
>>>

Re: [Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add
> 	missing tests for vreinterpretq_p{8,16}.

Ok.
Thanks,
Kyrill

> Change-Id: I7e9bb18c668c34685f12aa578868d7752232a96c
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> index d4e5768..2570f73 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> @@ -371,6 +371,83 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
>   VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
>   						 0xfff7fff6fff5fff4 };
>   
> +
> +/* Expected results for vreinterpretq_p8_xx.  */
> +VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> +						0xf4, 0xf5, 0xf6, 0xf7,
> +						0xf8, 0xf9, 0xfa, 0xfb,
> +						0xfc, 0xfd, 0xfe, 0xff };
> +VECT_VAR_DECL(expected_q_p8_2,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> +						0xf2, 0xff, 0xf3, 0xff,
> +						0xf4, 0xff, 0xf5, 0xff,
> +						0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_p8_3,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> +						0xf1, 0xff, 0xff, 0xff,
> +						0xf2, 0xff, 0xff, 0xff,
> +						0xf3, 0xff, 0xff, 0xff };
> +VECT_VAR_DECL(expected_q_p8_4,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> +						0xff, 0xff, 0xff, 0xff,
> +						0xf1, 0xff, 0xff, 0xff,
> +						0xff, 0xff, 0xff, 0xff };
> +VECT_VAR_DECL(expected_q_p8_5,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> +						0xf4, 0xf5, 0xf6, 0xf7,
> +						0xf8, 0xf9, 0xfa, 0xfb,
> +						0xfc, 0xfd, 0xfe, 0xff };
> +VECT_VAR_DECL(expected_q_p8_6,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> +						0xf2, 0xff, 0xf3, 0xff,
> +						0xf4, 0xff, 0xf5, 0xff,
> +						0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_p8_7,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> +						0xf1, 0xff, 0xff, 0xff,
> +						0xf2, 0xff, 0xff, 0xff,
> +						0xf3, 0xff, 0xff, 0xff };
> +VECT_VAR_DECL(expected_q_p8_8,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> +						0xff, 0xff, 0xff, 0xff,
> +						0xf1, 0xff, 0xff, 0xff,
> +						0xff, 0xff, 0xff, 0xff };
> +VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> +						0xf2, 0xff, 0xf3, 0xff,
> +						0xf4, 0xff, 0xf5, 0xff,
> +						0xf6, 0xff, 0xf7, 0xff };
> +
> +/* Expected results for vreinterpretq_p16_xx.  */
> +VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> +						 0xf5f4, 0xf7f6,
> +						 0xf9f8, 0xfbfa,
> +						 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_p16_2,poly,16,8) [] = { 0xfff0, 0xfff1,
> +						 0xfff2, 0xfff3,
> +						 0xfff4, 0xfff5,
> +						 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_p16_3,poly,16,8) [] = { 0xfff0, 0xffff,
> +						 0xfff1, 0xffff,
> +						 0xfff2, 0xffff,
> +						 0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_p16_4,poly,16,8) [] = { 0xfff0, 0xffff,
> +						 0xffff, 0xffff,
> +						 0xfff1, 0xffff,
> +						 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_p16_5,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> +						 0xf5f4, 0xf7f6,
> +						 0xf9f8, 0xfbfa,
> +						 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_p16_6,poly,16,8) [] = { 0xfff0, 0xfff1,
> +						 0xfff2, 0xfff3,
> +						 0xfff4, 0xfff5,
> +						 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_p16_7,poly,16,8) [] = { 0xfff0, 0xffff,
> +						 0xfff1, 0xffff,
> +						 0xfff2, 0xffff,
> +						 0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_p16_8,poly,16,8) [] = { 0xfff0, 0xffff,
> +						 0xffff, 0xffff,
> +						 0xfff1, 0xffff,
> +						 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> +						 0xf5f4, 0xf7f6,
> +						 0xf9f8, 0xfbfa,
> +						 0xfdfc, 0xfffe };
> +
>   /* Expected results for vreinterpret_f32_xx.  */
>   VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
>   VECT_VAR_DECL(expected_f32_2,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> @@ -685,6 +762,28 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
>     TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
>   
> +  /* vreinterpretq_p8_xx.  */
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 16, 8, expected_q_p8_2);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 32, 4, expected_q_p8_3);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 64, 2, expected_q_p8_4);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 8, 16, expected_q_p8_5);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 16, 8, expected_q_p8_6);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
> +
> +  /* vreinterpretq_p16_xx.  */
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 16, 8, expected_q_p16_2);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 32, 4, expected_q_p16_3);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 64, 2, expected_q_p16_4);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 8, 16, expected_q_p16_5);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 16, 8, expected_q_p16_6);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
> +
>     /* vreinterpret_f32_xx.  */
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 16, 4, expected_f32_2);

Re: [Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add fp16 tests.

I thought for a bit wrapping the expected_f16, expectedq_f16 and other declarations
in an "#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)"
as well but I don't think there's much to gain in that.

So ok for trunk.

Thanks,
Kyrill

> Change-Id: I5fafd1e90baf09588ab9f5444817c74e7d865a20
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
> index 5806050..fe41c5f 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
> @@ -13,6 +13,7 @@ uint32_t   expected_u32  = 0xfffffff1;
>   uint64_t   expected_u64  = 0xfffffffffffffff0;
>   poly8_t    expected_p8   = 0xf6;
>   poly16_t   expected_p16  = 0xfff2;
> +hfloat16_t expected_f16  = 0xcb80;
>   hfloat32_t expected_f32  = 0xc1700000;
>   
>   int8_t     expectedq_s8  = 0xff;
> @@ -25,6 +26,7 @@ uint32_t   expectedq_u32 = 0xfffffff2;
>   uint64_t   expectedq_u64 = 0xfffffffffffffff1;
>   poly8_t    expectedq_p8  = 0xfe;
>   poly16_t   expectedq_p16 = 0xfff6;
> +hfloat16_t expectedq_f16 = 0xca80;
>   hfloat32_t expectedq_f32 = 0xc1500000;
>   
>   int error_found = 0;
> @@ -52,6 +54,10 @@ void exec_vget_lane (void)
>       uint32_t var_int32;
>       float32_t var_float32;
>     } var_int32_float32;
> +  union {
> +    uint16_t var_int16;
> +    float16_t var_float16;
> +  } var_int16_float16;
>   
>   #define TEST_VGET_LANE_FP(Q, T1, T2, W, N, L)				   \
>     VAR(var, T1, W) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
> @@ -81,10 +87,17 @@ void exec_vget_lane (void)
>     VAR_DECL(var, uint, 64);
>     VAR_DECL(var, poly, 8);
>     VAR_DECL(var, poly, 16);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  VAR_DECL(var, float, 16);
> +#endif
>     VAR_DECL(var, float, 32);
>   
>     /* Initialize input values.  */
>     TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  VLOAD(vector, buffer, , float, f, 16, 4);
> +  VLOAD(vector, buffer, q, float, f, 16, 8);
> +#endif
>     VLOAD(vector, buffer, , float, f, 32, 2);
>     VLOAD(vector, buffer, q, float, f, 32, 4);
>   
> @@ -99,6 +112,9 @@ void exec_vget_lane (void)
>     TEST_VGET_LANE(, uint, u, 64, 1, 0);
>     TEST_VGET_LANE(, poly, p, 8, 8, 6);
>     TEST_VGET_LANE(, poly, p, 16, 4, 2);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  TEST_VGET_LANE_FP(, float, f, 16, 4, 1);
> +#endif
>     TEST_VGET_LANE_FP(, float, f, 32, 2, 1);
>   
>     TEST_VGET_LANE(q, int, s, 8, 16, 15);
> @@ -111,6 +127,9 @@ void exec_vget_lane (void)
>     TEST_VGET_LANE(q, uint, u, 64, 2, 1);
>     TEST_VGET_LANE(q, poly, p, 8, 16, 14);
>     TEST_VGET_LANE(q, poly, p, 16, 8, 6);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  TEST_VGET_LANE_FP(q, float, f, 16, 8, 3);
> +#endif
>     TEST_VGET_LANE_FP(q, float, f, 32, 4, 3);
>   }
>   

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[Christophe Lyon]

[-- Attachment #1: Type: text/plain, Size: 1778 bytes --]

On 13 May 2016 at 16:47, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote:
>> On 13 May 2016 at 16:37, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>> > On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote:
>> >> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>> >>
>> >>       * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
>> >>       for vtst_p8 and vtstq_p8.
>> >
>> > And vtst_p16 and vtstq_p16 too please.
>> >
>> > vtst_s64
>> > vtstq_s64
>> > vtst_u64
>> > vtstq_u64 are also missing (AArch64 only).
>> >
>> vtst_p16/vtstq_p16 are AArch64 only too, right?
>
> Not in my copy of:
>
>   http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
>
> I see it is missing from config/arm/arm_neon.h so that's a bug in the GCC
> implementation. It should be easy to resolve, map it to the same place
> as vtst_u16 and vtst_s16 - this is just a bit operation which takes no
> semantics from the data-type.
>
Maybe you have a way of automatically checking that the doc and arm_neon.h
contents match? I mean:
- are there other intrinsics documented, but not defined in arm_neon.h ?
- are there intrinsics in arm_neon.h, but not in the doc?

> Would you mind spinning the fix for that and committing it before this
> patch?
>

I've attached an updated patch which contains the definition for the
missing vtst_p16 and vtstq_p16,
as well as tests for vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16.

>> My introduction message was not clear enough: this series
>> only attempts to fully cover AArch32 intrinsics.
>
> Understood, sorry for the extra noise.
>
Coverage of AArch64 intrinsics will require another effort :)

> Thanks,
> James
>
>

[-- Attachment #2: vtst_poly.log.txt --]
[-- Type: text/plain, Size: 249 bytes --]

2016-05-19  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/arm_neon.h (vtst_p16, vtstq_p16): New.

	gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
        for vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16.

[-- Attachment #3: vtst_poly.patch.txt --]
[-- Type: text/plain, Size: 3653 bytes --]

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 07503d7..7997cb4 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -2607,6 +2607,12 @@ vtst_p8 (poly8x8_t __a, poly8x8_t __b)
   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
 }
 
+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+vtst_p16 (poly16x4_t __a, poly16x4_t __b)
+{
+  return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
+}
+
 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
 vtstq_s8 (int8x16_t __a, int8x16_t __b)
 {
@@ -2649,6 +2655,12 @@ vtstq_p8 (poly8x16_t __a, poly8x16_t __b)
   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
 }
 
+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+vtstq_p16 (poly16x8_t __a, poly16x8_t __b)
+{
+  return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
+}
+
 __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
 vabd_s8 (int8x8_t __a, int8x8_t __b)
 {
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
index 9e74ffb..8f9e651 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -32,6 +32,19 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
 VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
 						  0x0, 0xffffffff };
 
+/* Expected results with poly input.  */
+VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+					     0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff,
+					      0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_poly,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_poly,uint,16,8) [] = { 0x0, 0xffff,
+					      0x0, 0xffff,
+					      0xffff, 0xffff,
+					      0xffff, 0xffff };
+
 #define INSN_NAME vtst
 #define TEST_MSG "VTST/VTSTQ"
 
@@ -71,12 +84,16 @@ FNNAME (INSN_NAME)
   VDUP(vector2, , uint, u, 8, 8, 15);
   VDUP(vector2, , uint, u, 16, 4, 5);
   VDUP(vector2, , uint, u, 32, 2, 1);
+  VDUP(vector2, , poly, p, 8, 8, 15);
+  VDUP(vector2, , poly, p, 16, 4, 5);
   VDUP(vector2, q, int, s, 8, 16, 15);
   VDUP(vector2, q, int, s, 16, 8, 5);
   VDUP(vector2, q, int, s, 32, 4, 1);
   VDUP(vector2, q, uint, u, 8, 16, 15);
   VDUP(vector2, q, uint, u, 16, 8, 5);
   VDUP(vector2, q, uint, u, 32, 4, 1);
+  VDUP(vector2, q, poly, p, 8, 16, 15);
+  VDUP(vector2, q, poly, p, 16, 8, 5);
 
 #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
   MACRO(VAR, , T1, T2, 8, 8);					\
@@ -109,6 +126,18 @@ FNNAME (INSN_NAME)
   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
+
+  /* Now, test the variants with poly8 and poly16 as input.  */
+#undef CMT
+#define CMT " (poly input)"
+  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
+  TEST_BINARY_OP(INSN_NAME, , poly, p, 16, 4);
+  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
+  TEST_BINARY_OP(INSN_NAME, q, poly, p, 16, 8);
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_poly, CMT);
 }
 
 int main (void)

Re: [Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests.

[Kyrill Tkachov]

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Add fp16 tests.

Ok.
Thanks,
Kyrill

>
> Change-Id: I64e30bc30a9a9cc5c47eff212e7d745bf3230fe7
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
> index b923b64..282edd5 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
> @@ -14,6 +14,7 @@ VECT_VAR_DECL(expected_st2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>   VECT_VAR_DECL(expected_st2_0,poly,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st2_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
>   VECT_VAR_DECL(expected_st2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -24,6 +25,8 @@ VECT_VAR_DECL(expected_st2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
>   					       0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st2_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>   						 0x0, 0x0 };
>   
> @@ -39,6 +42,7 @@ VECT_VAR_DECL(expected_st2_1,uint,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st2_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,hfloat,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -48,6 +52,8 @@ VECT_VAR_DECL(expected_st2_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st2_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st2_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st2_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Expected results for vst3, chunk 0.  */
> @@ -62,6 +68,7 @@ VECT_VAR_DECL(expected_st3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>   VECT_VAR_DECL(expected_st3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
> +VECT_VAR_DECL(expected_st3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0 };
>   VECT_VAR_DECL(expected_st3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
>   VECT_VAR_DECL(expected_st3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -73,6 +80,8 @@ VECT_VAR_DECL(expected_st3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
>   					       0xfffffff2, 0x0 };
>   VECT_VAR_DECL(expected_st3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st3_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>   						 0xc1600000, 0x0 };
>   
> @@ -88,6 +97,7 @@ VECT_VAR_DECL(expected_st3_1,uint,32,2) [] = { 0xfffffff2, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st3_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,hfloat,32,2) [] = { 0xc1600000, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -97,6 +107,8 @@ VECT_VAR_DECL(expected_st3_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st3_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st3_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Expected results for vst3, chunk 2.  */
> @@ -111,6 +123,7 @@ VECT_VAR_DECL(expected_st3_2,uint,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st3_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,hfloat,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -120,6 +133,8 @@ VECT_VAR_DECL(expected_st3_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st3_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st3_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st3_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Expected results for vst4, chunk 0.  */
> @@ -134,6 +149,7 @@ VECT_VAR_DECL(expected_st4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>   VECT_VAR_DECL(expected_st4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_st4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>   VECT_VAR_DECL(expected_st4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
>   VECT_VAR_DECL(expected_st4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -145,6 +161,8 @@ VECT_VAR_DECL(expected_st4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
>   					       0xfffffff2, 0xfffffff3 };
>   VECT_VAR_DECL(expected_st4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>   						 0xc1600000, 0xc1500000 };
>   
> @@ -160,6 +178,7 @@ VECT_VAR_DECL(expected_st4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
>   VECT_VAR_DECL(expected_st4_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
>   VECT_VAR_DECL(expected_st4_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -169,6 +188,8 @@ VECT_VAR_DECL(expected_st4_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st4_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Expected results for vst4, chunk 2.  */
> @@ -183,6 +204,7 @@ VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -192,6 +214,8 @@ VECT_VAR_DECL(expected_st4_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st4_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +					       0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Expected results for vst4, chunk 3.  */
> @@ -206,6 +230,7 @@ VECT_VAR_DECL(expected_st4_3,uint,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_3,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,hfloat,32,2) [] = { 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					      0x0, 0x0, 0x0, 0x0 };
> @@ -215,6 +240,8 @@ VECT_VAR_DECL(expected_st4_3,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   VECT_VAR_DECL(expected_st4_3,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
>   					       0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_st4_3,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
> +						 0x0, 0x0, 0x0, 0x0 };
>   VECT_VAR_DECL(expected_st4_3,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>   
>   /* Declare additional input buffers as needed.  */
> @@ -229,6 +256,7 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2);
>   VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2);
>   VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2);
>   VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2);
> +VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2);
>   VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2);
>   
>   /* Input buffers for vld3_lane.  */
> @@ -242,6 +270,7 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3);
>   VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3);
>   VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3);
>   VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3);
> +VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3);
>   VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3);
>   
>   /* Input buffers for vld4_lane.  */
> @@ -255,6 +284,7 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4);
>   VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4);
>   VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4);
>   VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4);
> +VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4);
>   VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4);
>   
>   void exec_vstX_lane (void)
> @@ -302,7 +332,7 @@ void exec_vstX_lane (void)
>   
>     /* We need all variants in 64 bits, but there is no 64x2 variant,
>        nor 128 bits vectors of int8/uint8/poly8.  */
> -#define DECL_ALL_VSTX_LANE(X)			\
> +#define DECL_ALL_VSTX_LANE_NO_FP16(X)		\
>     DECL_VSTX_LANE(int, 8, 8, X);			\
>     DECL_VSTX_LANE(int, 16, 4, X);		\
>     DECL_VSTX_LANE(int, 32, 2, X);		\
> @@ -319,11 +349,20 @@ void exec_vstX_lane (void)
>     DECL_VSTX_LANE(poly, 16, 8, X);		\
>     DECL_VSTX_LANE(float, 32, 4, X)
>   
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +#define DECL_ALL_VSTX_LANE(X)		\
> +  DECL_ALL_VSTX_LANE_NO_FP16(X);	\
> +  DECL_VSTX_LANE(float, 16, 4, X);	\
> +  DECL_VSTX_LANE(float, 16, 8, X)
> +#else
> +#define DECL_ALL_VSTX_LANE(X) DECL_ALL_VSTX_LANE_NO_FP16(X)
> +#endif
> +
>   #define DUMMY_ARRAY(V, T, W, N, L) VECT_VAR_DECL(V,T,W,N)[N*L]
>   
>     /* Use the same lanes regardless of the size of the array (X), for
>        simplicity.  */
> -#define TEST_ALL_VSTX_LANE(X)			\
> +#define TEST_ALL_VSTX_LANE_NO_FP16(X)		\
>     TEST_VSTX_LANE(, int, s, 8, 8, X, 7);		\
>     TEST_VSTX_LANE(, int, s, 16, 4, X, 2);	\
>     TEST_VSTX_LANE(, int, s, 32, 2, X, 0);	\
> @@ -340,7 +379,16 @@ void exec_vstX_lane (void)
>     TEST_VSTX_LANE(q, poly, p, 16, 8, X, 5);	\
>     TEST_VSTX_LANE(q, float, f, 32, 4, X, 2)
>   
> -#define TEST_ALL_EXTRA_CHUNKS(X, Y)		\
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +#define TEST_ALL_VSTX_LANE(X)			\
> +  TEST_ALL_VSTX_LANE_NO_FP16(X);		\
> +  TEST_VSTX_LANE(, float, f, 16, 4, X, 2);	\
> +  TEST_VSTX_LANE(q, float, f, 16, 8, X, 6)
> +#else
> +#define TEST_ALL_VSTX_LANE(X) TEST_ALL_VSTX_LANE_NO_FP16(X)
> +#endif
> +
> +#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)	\
>     TEST_EXTRA_CHUNK(int, 8, 8, X, Y);		\
>     TEST_EXTRA_CHUNK(int, 16, 4, X, Y);		\
>     TEST_EXTRA_CHUNK(int, 32, 2, X, Y);		\
> @@ -357,6 +405,15 @@ void exec_vstX_lane (void)
>     TEST_EXTRA_CHUNK(poly, 16, 8, X, Y);		\
>     TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
>   
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +#define TEST_ALL_EXTRA_CHUNKS(X,Y)		\
> +  TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y);		\
> +  TEST_EXTRA_CHUNK(float, 16, 4, X, Y);		\
> +  TEST_EXTRA_CHUNK(float, 16, 8, X, Y)
> +#else
> +#define TEST_ALL_EXTRA_CHUNKS(X,Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)
> +#endif
> +
>     /* Declare the temporary buffers / variables.  */
>     DECL_ALL_VSTX_LANE(2);
>     DECL_ALL_VSTX_LANE(3);
> @@ -371,12 +428,18 @@ void exec_vstX_lane (void)
>     DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
>     DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
>     DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  DUMMY_ARRAY(buffer_src, float, 16, 4, 4);
> +#endif
>     DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
>     DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
>     DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
>     DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
>     DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
>     DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  DUMMY_ARRAY(buffer_src, float, 16, 8, 4);
> +#endif
>     DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
>   
>     /* Check vst2_lane/vst2q_lane.  */
> @@ -400,6 +463,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_0, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_0, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_0, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_0, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(2, 1);
>   #undef CMT
> @@ -419,6 +486,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_1, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_1, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_1, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_1, CMT);
> +#endif
>   
>   
>     /* Check vst3_lane/vst3q_lane.  */
> @@ -444,6 +515,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_0, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_0, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_0, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_0, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(3, 1);
>   
> @@ -464,6 +539,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_1, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_1, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_1, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_1, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(3, 2);
>   
> @@ -484,6 +563,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_2, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_2, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_2, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_2, CMT);
> +#endif
>   
>   
>     /* Check vst4_lane/vst4q_lane.  */
> @@ -509,6 +592,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_0, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_0, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_0, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_0, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(4, 1);
>   
> @@ -529,6 +616,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_1, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_1, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_1, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_1, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(4, 2);
>   
> @@ -549,6 +640,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_2, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_2, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_2, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_2, CMT);
> +#endif
>   
>     TEST_ALL_EXTRA_CHUNKS(4, 3);
>   
> @@ -569,6 +664,10 @@ void exec_vstX_lane (void)
>     CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_3, CMT);
>     CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
>     CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_3, CMT);
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_3, CMT);
> +  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_3, CMT);
> +#endif
>   }
>   
>   int main (void)

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Kyrill Tkachov]

Hi Christophe,

On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
> 	* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.

Drop the gcc/testsuite from the ChangeLog entry. Just "* gcc.target/aarch64/..."

Ok with the fixed ChangeLog.

Thanks,
Kyrill


> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 0000000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnd
> +#define TEST_MSG "VRND"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> new file mode 100644
> index 0000000..629240d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> @@ -0,0 +1,43 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1 (NAME)
> +
> +void FNNAME (INSN) (void)
> +{
> +  /* vector_res = vrndX (vector), then store the result.  */
> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
> +  VECT_VAR (vector_res, T1, W, N) =					\
> +    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
> +    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
> +		       VECT_VAR (vector_res, T1, W, N))
> +
> +  /* Two auxliary macros are necessary to expand INSN.  */
> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
> +
> +#define TEST_VRND(Q, T1, T2, W, N)		\
> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
> +
> +  DECL_VARIABLE (vector, float, 32, 2);
> +  DECL_VARIABLE (vector, float, 32, 4);
> +
> +  DECL_VARIABLE (vector_res, float, 32, 2);
> +  DECL_VARIABLE (vector_res, float, 32, 4);
> +
> +  clean_results ();
> +
> +  VLOAD (vector, buffer, , float, f, 32, 2);
> +  VLOAD (vector, buffer, q, float, f, 32, 4);
> +
> +  TEST_VRND ( , float, f, 32, 2);
> +  TEST_VRND (q, float, f, 32, 4);
> +
> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int
> +main (void)
> +{
> +  FNNAME (INSN) ();
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> new file mode 100644
> index 0000000..816fd28d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnda
> +#define TEST_MSG "VRNDA"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> new file mode 100644
> index 0000000..029880c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndm
> +#define TEST_MSG "VRNDM"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> new file mode 100644
> index 0000000..571243c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndn
> +#define TEST_MSG "VRNDN"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> new file mode 100644
> index 0000000..ff4771c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndp
> +#define TEST_MSG "VRNDP"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> new file mode 100644
> index 0000000..ff2357b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> +					       0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndx
> +#define TEST_MSG "VRNDX"
> +
> +#include "vrndX.inc"

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

[Kyrill Tkachov]

On 13/05/16 16:16, James Greenhalgh wrote:
> On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote:
>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>
>> 	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result):
>> 	Add poly64x1_t and poly64x2_t cases if supported.
>> 	* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
>> 	(buffer, buffer_pad, buffer_dup, buffer_dup_pad): Likewise.
>> 	* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: New file.
>> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: New file.
>> 	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: New file.
>>
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
>> @@ -0,0 +1,665 @@
>> +/* This file contains tests for all the *p64 intrinsics, except for
>> +   vreinterpret which have their own testcase.  */
>> +
>> +/* { dg-require-effective-target arm_crypto_ok } */
>> +/* { dg-add-options arm_crypto } */
>> +
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results: vbsl.  */
>> +VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
>> +VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
>> +					      0xfffffff1 };
>> +
>> +/* Expected results: vceq.  */
>> +VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
> vceqq_p64
> vceqz_p64
> vceqzq_p64
> vtst_p64
> vtstq_p64
>
> are missing, but will not be trivial to add. Could you raise a bug report
> (or fix it if you like :-) )?
>
> This is OK without a fix for those intrinsics with a suitable bug report
> opened.

That's ok by me too.
Thanks,
Kyrill

> Thanks,
> James
>

Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[Kyrill Tkachov]

On 11/05/16 14:24, Christophe Lyon wrote:
> 2016-05-04  Christophe Lyon  <christophe.lyon@linaro.org>
>
>          * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
>          * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
>          * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.

Ok.
Thanks for working on these!
Kyrill


> Change-Id: Ic8061f1a5f3e042844a33a70c0f42a5f92c43c98
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> index 2570f73..0de2ab3 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> @@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>   					    0xf4, 0xf5, 0xf6, 0xf7 };
>   VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   					    0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +					     0x00, 0xcb, 0x80, 0xca };
>   
>   /* Expected results for vreinterpret_s16_xx.  */
>   VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
>   VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>   VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
>   VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>   
>   /* Expected results for vreinterpret_s32_xx.  */
>   VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>   VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
>   VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
>   VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>   
>   /* Expected results for vreinterpret_s64_xx.  */
>   VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> @@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
>   VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
>   VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
>   VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
> +VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
>   
>   /* Expected results for vreinterpret_u8_xx.  */
>   VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>   					     0xf4, 0xf5, 0xf6, 0xf7 };
>   VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   					     0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +					      0x00, 0xcb, 0x80, 0xca };
>   
>   /* Expected results for vreinterpret_u16_xx.  */
>   VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
>   VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>   VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
>   VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>   
>   /* Expected results for vreinterpret_u32_xx.  */
>   VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
>   VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
>   VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
>   VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>   
>   /* Expected results for vreinterpret_u64_xx.  */
>   VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> @@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
>   VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
>   VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
>   VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
> +VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
>   
>   /* Expected results for vreinterpret_p8_xx.  */
>   VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
>   					     0xff, 0xff, 0xff, 0xff };
>   VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   					     0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_p8_10,poly,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +					      0x00, 0xcb, 0x80, 0xca };
>   
>   /* Expected results for vreinterpret_p16_xx.  */
>   VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -138,6 +150,7 @@ VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
>   VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
>   VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>   VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_p16_10,poly,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>   
>   /* Expected results for vreinterpretq_s8_xx.  */
>   VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> @@ -176,6 +189,10 @@ VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   					       0xf2, 0xff, 0xf3, 0xff,
>   					       0xf4, 0xff, 0xf5, 0xff,
>   					       0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_s8_10,int,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +						0x00, 0xcb, 0x80, 0xca,
> +						0x00, 0xca, 0x80, 0xc9,
> +						0x00, 0xc9, 0x80, 0xc8 };
>   
>   /* Expected results for vreinterpretq_s16_xx.  */
>   VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -214,6 +231,10 @@ VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
>   						0xfff2, 0xfff3,
>   						0xfff4, 0xfff5,
>   						0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_s16_10,int,16,8) [] = { 0xcc00, 0xcb80,
> +						 0xcb00, 0xca80,
> +						 0xca00, 0xc980,
> +						 0xc900, 0xc880 };
>   
>   /* Expected results for vreinterpretq_s32_xx.  */
>   VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -234,6 +255,8 @@ VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
>   						0xfbfaf9f8, 0xfffefdfc };
>   VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
>   						0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_s32_10,int,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> +						 0xc980ca00, 0xc880c900 };
>   
>   /* Expected results for vreinterpretq_s64_xx.  */
>   VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -254,6 +277,8 @@ VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
>   						0xfffefdfcfbfaf9f8 };
>   VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
>   						0xfff7fff6fff5fff4 };
> +VECT_VAR_DECL(expected_q_s64_10,int,64,2) [] = { 0xca80cb00cb80cc00,
> +						 0xc880c900c980ca00 };
>   
>   /* Expected results for vreinterpretq_u8_xx.  */
>   VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -292,6 +317,10 @@ VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   						0xf2, 0xff, 0xf3, 0xff,
>   						0xf4, 0xff, 0xf5, 0xff,
>   						0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_u8_10,uint,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +						 0x00, 0xcb, 0x80, 0xca,
> +						 0x00, 0xca, 0x80, 0xc9,
> +						 0x00, 0xc9, 0x80, 0xc8 };
>   
>   /* Expected results for vreinterpretq_u16_xx.  */
>   VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -330,6 +359,10 @@ VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
>   						 0xfff2, 0xfff3,
>   						 0xfff4, 0xfff5,
>   						 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_u16_10,uint,16,8) [] = { 0xcc00, 0xcb80,
> +						  0xcb00, 0xca80,
> +						  0xca00, 0xc980,
> +						  0xc900, 0xc880 };
>   
>   /* Expected results for vreinterpretq_u32_xx.  */
>   VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -350,6 +383,8 @@ VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
>   						 0xfbfaf9f8, 0xfffefdfc };
>   VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
>   						 0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_u32_10,uint,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> +						  0xc980ca00, 0xc880c900 };
>   
>   /* Expected results for vreinterpretq_u64_xx.  */
>   VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -370,7 +405,8 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
>   						0xfffefdfcfbfaf9f8 };
>   VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
>   						 0xfff7fff6fff5fff4 };
> -
> +VECT_VAR_DECL(expected_q_u64_10,uint,64,2) [] = { 0xca80cb00cb80cc00,
> +						  0xc880c900c980ca00 };
>   
>   /* Expected results for vreinterpretq_p8_xx.  */
>   VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -409,6 +445,10 @@ VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
>   						0xf2, 0xff, 0xf3, 0xff,
>   						0xf4, 0xff, 0xf5, 0xff,
>   						0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_p8_10,poly,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> +						 0x00, 0xcb, 0x80, 0xca,
> +						 0x00, 0xca, 0x80, 0xc9,
> +						 0x00, 0xc9, 0x80, 0xc8 };
>   
>   /* Expected results for vreinterpretq_p16_xx.  */
>   VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -447,6 +487,10 @@ VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
>   						 0xf5f4, 0xf7f6,
>   						 0xf9f8, 0xfbfa,
>   						 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_p16_10,poly,16,8) [] = { 0xcc00, 0xcb80,
> +						  0xcb00, 0xca80,
> +						  0xca00, 0xc980,
> +						  0xc900, 0xc880 };
>   
>   /* Expected results for vreinterpret_f32_xx.  */
>   VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -459,6 +503,7 @@ VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>   VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
>   VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
>   VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_f32_11,hfloat,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>   
>   /* Expected results for vreinterpretq_f32_xx.  */
>   VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -481,6 +526,8 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
>   						   0xfbfaf9f8, 0xfffefdfc };
>   VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
>   						    0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_f32_11,hfloat,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> +						    0xc980ca00, 0xc880c900 };
>   
>   /* Expected results for vreinterpret_xx_f32.  */
>   VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
> @@ -496,6 +543,7 @@ VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
>   VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
>   						 0x0, 0x0, 0x70, 0xc1 };
>   VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
> +VECT_VAR_DECL(expected_xx_f32_11,hfloat,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
>   
>   /* Expected results for vreinterpretq_xx_f32.  */
>   VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
> @@ -524,6 +572,62 @@ VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
>   						    0x0, 0x0, 0x50, 0xc1 };
>   VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
>   						     0x0, 0xc160, 0x0, 0xc150 };
> +VECT_VAR_DECL(expected_q_xx_f32_11,hfloat,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
> +						      0x0, 0xc160, 0x0, 0xc150 };
> +
> +/* Expected results for vreinterpret_f16_xx.  */
> +VECT_VAR_DECL(expected_f16_1,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_2,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_f16_3,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> +VECT_VAR_DECL(expected_f16_4,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_f16_5,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_6,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_f16_7,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> +VECT_VAR_DECL(expected_f16_8,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_f16_9,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_10,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +
> +/* Expected results for vreinterpretq_f16_xx.  */
> +VECT_VAR_DECL(expected_q_f16_1,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> +						   0xf5f4, 0xf7f6,
> +						   0xf9f8, 0xfbfa,
> +						   0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_2,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> +						   0xfff2, 0xfff3,
> +						   0xfff4, 0xfff5,
> +						   0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_f16_3,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +						   0xfff1, 0xffff,
> +						   0xfff2, 0xffff,
> +						   0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_4,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +						   0xffff, 0xffff,
> +						   0xfff1, 0xffff,
> +						   0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_5,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> +						   0xf5f4, 0xf7f6,
> +						   0xf9f8, 0xfbfa,
> +						   0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_6,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> +						   0xfff2, 0xfff3,
> +						   0xfff4, 0xfff5,
> +						   0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_f16_7,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +						   0xfff1, 0xffff,
> +						   0xfff2, 0xffff,
> +						   0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_8,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +						   0xffff, 0xffff,
> +						   0xfff1, 0xffff,
> +						   0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_9,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> +						   0xf5f4, 0xf7f6,
> +						   0xf9f8, 0xfbfa,
> +						   0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_10,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> +						    0xfff2, 0xfff3,
> +						    0xfff4, 0xfff5,
> +						    0xfff6, 0xfff7 };
>   
>   #define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
>   
> @@ -561,7 +665,9 @@ void exec_vreinterpret (void)
>   
>     /* Initialize input "vector" from "buffer".  */
>     TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
> +  VLOAD(vector, buffer, , float, f, 16, 4);
>     VLOAD(vector, buffer, , float, f, 32, 2);
> +  VLOAD(vector, buffer, q, float, f, 16, 8);
>     VLOAD(vector, buffer, q, float, f, 32, 4);
>   
>     /* vreinterpret_s8_xx.  */
> @@ -574,6 +680,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
>     TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
>     TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
> +  TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10);
>   
>     /* vreinterpret_s16_xx.  */
>     TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
> @@ -585,6 +692,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
>     TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
>     TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
> +  TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10);
>   
>     /* vreinterpret_s32_xx.  */
>     TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
> @@ -596,6 +704,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
>     TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
>     TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
> +  TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10);
>   
>     /* vreinterpret_s64_xx.  */
>     TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
> @@ -607,6 +716,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
>     TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
>     TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
> +  TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10);
>   
>     /* vreinterpret_u8_xx.  */
>     TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
> @@ -618,6 +728,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
>     TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
>     TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
> +  TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10);
>   
>     /* vreinterpret_u16_xx.  */
>     TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
> @@ -629,6 +740,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
>     TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
>     TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
> +  TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10);
>   
>     /* vreinterpret_u32_xx.  */
>     TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
> @@ -640,6 +752,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
>     TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
>     TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
> +  TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10);
>   
>     /* vreinterpret_u64_xx.  */
>     TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
> @@ -651,6 +764,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
>     TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
>     TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
> +  TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10);
>   
>     /* vreinterpret_p8_xx.  */
>     TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
> @@ -662,6 +776,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
>     TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
>     TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
> +  TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10);
>   
>     /* vreinterpret_p16_xx.  */
>     TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
> @@ -673,6 +788,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
>     TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
>     TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
> +  TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10);
>   
>     /* vreinterpretq_s8_xx.  */
>     TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
> @@ -684,6 +800,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
>     TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
>     TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
> +  TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10);
>   
>     /* vreinterpretq_s16_xx.  */
>     TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
> @@ -695,6 +812,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
>     TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
>     TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
> +  TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10);
>   
>     /* vreinterpretq_s32_xx.  */
>     TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
> @@ -706,6 +824,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
>     TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
>     TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
> +  TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10);
>   
>     /* vreinterpretq_s64_xx.  */
>     TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
> @@ -717,6 +836,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
>     TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
>     TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
> +  TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10);
>   
>     /* vreinterpretq_u8_xx.  */
>     TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
> @@ -728,6 +848,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
>     TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
>     TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
> +  TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10);
>   
>     /* vreinterpretq_u16_xx.  */
>     TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
> @@ -739,6 +860,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
>     TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
>     TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
> +  TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10);
>   
>     /* vreinterpretq_u32_xx.  */
>     TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
> @@ -750,6 +872,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
>     TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
>     TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
> +  TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10);
>   
>     /* vreinterpretq_u64_xx.  */
>     TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
> @@ -761,6 +884,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
>     TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
>     TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
> +  TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10);
>   
>     /* vreinterpretq_p8_xx.  */
>     TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
> @@ -772,6 +896,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
>     TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
>     TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10);
>   
>     /* vreinterpretq_p16_xx.  */
>     TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
> @@ -783,6 +908,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
>     TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
>     TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
> +  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10);
>   
>     /* vreinterpret_f32_xx.  */
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
> @@ -795,6 +921,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
> +  TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11);
>   
>     /* vreinterpretq_f32_xx.  */
>     TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
> @@ -807,6 +934,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
>     TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
>     TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
> +  TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11);
>   
>     /* vreinterpret_xx_f32.  */
>     TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
> @@ -819,6 +947,7 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
>     TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
>     TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11);
>   
>     /* vreinterpretq_xx_f32.  */
>     TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
> @@ -831,6 +960,31 @@ void exec_vreinterpret (void)
>     TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
>     TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
>     TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11);
> +
> +  /* vreinterpret_f16_xx.  */
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 8, 8, expected_f16_1);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 16, 4, expected_f16_2);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 32, 2, expected_f16_3);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 64, 1, expected_f16_4);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 8, 8, expected_f16_5);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 16, 4, expected_f16_6);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 32, 2, expected_f16_7);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 64, 1, expected_f16_8);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 8, 8, expected_f16_9);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 16, 4, expected_f16_10);
> +
> +  /* vreinterpretq_f16_xx.  */
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 8, 16, expected_q_f16_1);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 16, 8, expected_q_f16_2);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 32, 4, expected_q_f16_3);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 64, 2, expected_q_f16_4);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 8, 16, expected_q_f16_5);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 16, 8, expected_q_f16_6);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 32, 4, expected_q_f16_7);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10);
>   }
>   
>   int main (void)
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> index a049cb3..8ba5272 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> @@ -30,6 +30,8 @@ VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
>   							   0xfff7fff6fff5fff4 };
>   VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
>   							   0xc1500000c1600000 };
> +VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
> +							   0xc880c900c980ca00 };
>   
>   /* Expected results: vreinterpretq_*_p128.  */
>   VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -68,6 +70,10 @@ VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
>   							   0xfffffffffffffff1 };
>   VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
>   							     0xfffffff1, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +							     0xffff, 0xffff,
> +							     0xfff1, 0xffff,
> +							     0xffff, 0xffff };
>   
>   int main (void)
>   {
> @@ -80,6 +86,7 @@ int main (void)
>   
>     TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
>     VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
> +  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
>     VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
>   
>     /* vreinterpretq_p128_* tests.  */
> @@ -108,6 +115,7 @@ int main (void)
>     TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
>     TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
>     TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
> +  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16);
>     TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
>   
>     /* vreinterpretq_*_p128 tests.  */
> @@ -145,6 +153,7 @@ int main (void)
>     TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
>     TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
>     TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
> +  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128);
>     TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
>   
>     return 0;
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> index 79f3cd6..b000797 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> @@ -19,6 +19,7 @@ VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
>   VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
>   VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
>   VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
> +VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 };
>   
>   /* Expected results: vreinterpretq_p64_*.  */
>   VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -43,6 +44,8 @@ VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
>   							  0xfff7fff6fff5fff4 };
>   VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
>   							  0xc1500000c1600000 };
> +VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
> +							  0xc880c900c980ca00 };
>   
>   /* Expected results: vreinterpret_*_p64.  */
>   VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -59,6 +62,7 @@ VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
>   						      0xff, 0xff, 0xff, 0xff };
>   VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>   VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>   
>   /* Expected results: vreinterpretq_*_p64.  */
>   VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -95,6 +99,10 @@ VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
>   							  0xffff, 0xffff };
>   VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
>   							    0xfffffff1, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff,
> +							    0xffff, 0xffff,
> +							    0xfff1, 0xffff,
> +							    0xffff, 0xffff };
>   
>   int main (void)
>   {
> @@ -124,6 +132,8 @@ int main (void)
>     TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
>     VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
>     VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
> +  VLOAD(vreint_vector, buffer, , float, f, 16, 4);
> +  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
>     VLOAD(vreint_vector, buffer, , float, f, 32, 2);
>     VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
>   
> @@ -140,6 +150,7 @@ int main (void)
>     TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
>     TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
>     TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
> +  TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16);
>     TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
>   
>     /* vreinterpretq_p64_* tests.  */
> @@ -155,6 +166,7 @@ int main (void)
>     TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
>     TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
>     TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
> +  TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16);
>     TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
>   
>     /* vreinterpret_*_p64 tests.  */
> @@ -171,6 +183,7 @@ int main (void)
>     TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
>     TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
>     TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
> +  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64);
>     TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
>     TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
>     TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
> @@ -182,6 +195,7 @@ int main (void)
>     TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
>     TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
>     TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
> +  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64);
>     TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
>   
>     return 0;

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

[Kyrill Tkachov]

Hi Christophe,

On 19/05/16 12:54, Christophe Lyon wrote:
> On 13 May 2016 at 16:47, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>> On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote:
>>> On 13 May 2016 at 16:37, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>>>> On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote:
>>>>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>>>>
>>>>>        * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests
>>>>>        for vtst_p8 and vtstq_p8.
>>>> And vtst_p16 and vtstq_p16 too please.
>>>>
>>>> vtst_s64
>>>> vtstq_s64
>>>> vtst_u64
>>>> vtstq_u64 are also missing (AArch64 only).
>>>>
>>> vtst_p16/vtstq_p16 are AArch64 only too, right?
>> Not in my copy of:
>>
>>    http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
>>
>> I see it is missing from config/arm/arm_neon.h so that's a bug in the GCC
>> implementation. It should be easy to resolve, map it to the same place
>> as vtst_u16 and vtst_s16 - this is just a bit operation which takes no
>> semantics from the data-type.
>>
> Maybe you have a way of automatically checking that the doc and arm_neon.h
> contents match? I mean:
> - are there other intrinsics documented, but not defined in arm_neon.h ?
> - are there intrinsics in arm_neon.h, but not in the doc?
>
>> Would you mind spinning the fix for that and committing it before this
>> patch?
>>
> I've attached an updated patch which contains the definition for the
> missing vtst_p16 and vtstq_p16,
> as well as tests for vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16.

The patch is ok (I'm assuming the newly added tests pass ;)

Thanks,
Kyrill

>>> My introduction message was not clear enough: this series
>>> only attempts to fully cover AArch32 intrinsics.
>> Understood, sorry for the extra noise.
>>
> Coverage of AArch64 intrinsics will require another effort :)
>
>> Thanks,
>> James
>>
>>

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

[Christophe Lyon]

On 13 May 2016 at 17:16, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote:
>> 2016-05-02  Christophe Lyon  <christophe.lyon@linaro.org>
>>
>>       * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result):
>>       Add poly64x1_t and poly64x2_t cases if supported.
>>       * gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
>>       (buffer, buffer_pad, buffer_dup, buffer_dup_pad): Likewise.
>>       * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: New file.
>>       * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: New file.
>>       * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: New file.
>>
>
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
>> @@ -0,0 +1,665 @@
>> +/* This file contains tests for all the *p64 intrinsics, except for
>> +   vreinterpret which have their own testcase.  */
>> +
>> +/* { dg-require-effective-target arm_crypto_ok } */
>> +/* { dg-add-options arm_crypto } */
>> +
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results: vbsl.  */
>> +VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
>> +VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
>> +                                           0xfffffff1 };
>> +
>> +/* Expected results: vceq.  */
>> +VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
>
> vceqq_p64
> vceqz_p64
> vceqzq_p64
> vtst_p64
> vtstq_p64
>
> are missing, but will not be trivial to add. Could you raise a bug report
> (or fix it if you like :-) )?
>
> This is OK without a fix for those intrinsics with a suitable bug report
> opened.
>

OK, I've opened PR 71233 to track this.

Thanks,

Christophe.

> Thanks,
> James
>