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Tue, 17 May 2016 10:23:03 +0100 Received: from DB6PR0801CA0001.eurprd08.prod.outlook.com (10.165.173.139) by AM2PR08MB0532.eurprd08.prod.outlook.com (10.163.149.142) with Microsoft SMTP Server (TLS) id 15.1.497.12; Tue, 17 May 2016 09:23:01 +0000 Received: from AM1FFO11FD031.protection.gbl (2a01:111:f400:7e00::135) by DB6PR0801CA0001.outlook.office365.com (2603:10a6:4:2::11) with Microsoft SMTP Server (TLS) id 15.1.497.12 via Frontend Transport; Tue, 17 May 2016 09:23:01 +0000 Received: from nebula.arm.com (217.140.96.140) by AM1FFO11FD031.mail.protection.outlook.com (10.174.64.220) with Microsoft SMTP Server (TLS) id 15.1.497.8 via Frontend Transport; Tue, 17 May 2016 09:23:01 +0000 Received: from e107456-lin.cambridge.arm.com (10.1.2.79) by mail.arm.com (10.1.105.66) with Microsoft SMTP Server id 14.3.279.2; Tue, 17 May 2016 10:22:45 +0100 From: James Greenhalgh To: CC: , , , Subject: [Patch AArch64 2/2] Some more cleanup of ldp/stp generation Date: Tue, 17 May 2016 09:23:00 -0000 Message-ID: <1463476951-1567-3-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1463476951-1567-1-git-send-email-james.greenhalgh@arm.com> References: <1463476951-1567-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:217.140.96.140;IPV:CAL;SCL:-1;CTRY:GB;EFV:NLI;SFV:NSPM;SFS:(10009020)(979002)(6009001)(2980300002)(438002)(189002)(377424004)(199003)(33646002)(2906002)(5008740100001)(104016004)(450100001)(5003600100002)(87936001)(19580405001)(19580395003)(5000100001)(92566002)(512874002)(4610100001)(229853001)(2351001)(36756003)(106466001)(86362001)(50986999)(76176999)(189998001)(586003)(84326002)(568964002)(8676002)(8936002)(4326007)(50226002)(5890100001)(11100500001)(6806005)(2476003)(1220700001)(110136002)(77096005)(2950100001)(969003)(989001)(999001)(1009001)(1019001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM2PR08MB0532;H:nebula.arm.com;FPR:;SPF:Pass;MLV:ovrnspm;MX:1;A:1;PTR:fw-tnat.cambridge.arm.com;LANG:en; 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boundary="------------2.6.4.2.gae996d8" X-IsSubscribed: yes X-SW-Source: 2016-05/txt/msg01192.txt.bz2 --------------2.6.4.2.gae996d8 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 437 This is another refactoring patch to clean up more of the ldp/stp handling code and avoid duplicating quite as much code. Much like the other refactoring patch, this reduces the use of reg_1, reg_2, etc. leading to a cleaner implementation. Bootstrapped on AArch64 with no issues. OK? Thanks, James --- 2016-05-17 James Greenhalgh * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Refactor. --------------2.6.4.2.gae996d8 Content-Type: text/x-patch; name=0002-Patch-AArch64-2-2-Some-more-cleanup-of-ldp-stp-gener.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0002-Patch-AArch64-2-2-Some-more-cleanup-of-ldp-stp-gener.patch" Content-length: 3779 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 434c154..01bbe81 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -13549,26 +13549,18 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool = load, enum machine_mode mode, RTX_CODE code) { rtx base, offset, t1, t2; - rtx mem_1, mem_2, mem_3, mem_4; + rtx mem[4]; HOST_WIDE_INT off_val, abs_off, adj_off, new_off, stp_off_limit, msize; =20 - if (load) - { - mem_1 =3D operands[1]; - mem_2 =3D operands[3]; - mem_3 =3D operands[5]; - mem_4 =3D operands[7]; - } - else - { - mem_1 =3D operands[0]; - mem_2 =3D operands[2]; - mem_3 =3D operands[4]; - mem_4 =3D operands[6]; - gcc_assert (code =3D=3D UNKNOWN); - } + unsigned op_offset =3D load ? 1 : 0; + + for (int i =3D 0; i < 4; i++) + mem[i] =3D operands[(2 * i) + op_offset]; =20 - extract_base_offset_in_addr (mem_1, &base, &offset); + if (!load) + gcc_assert (code =3D=3D UNKNOWN); + + extract_base_offset_in_addr (mem[0], &base, &offset); gcc_assert (base !=3D NULL_RTX && offset !=3D NULL_RTX); =20 /* Adjust offset thus it can fit in ldp/stp instruction. */ @@ -13597,59 +13589,32 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool = load, } =20 /* Create new memory references. */ - mem_1 =3D change_address (mem_1, VOIDmode, - plus_constant (DImode, operands[8], new_off)); + mem[0] =3D change_address (mem[0], VOIDmode, + plus_constant (Pmode, operands[8], new_off)); =20 /* Check if the adjusted address is OK for ldp/stp. */ - if (!aarch64_mem_pair_operand (mem_1, mode)) + if (!aarch64_mem_pair_operand (mem[0], mode)) return false; =20 msize =3D GET_MODE_SIZE (mode); - mem_2 =3D change_address (mem_2, VOIDmode, - plus_constant (DImode, - operands[8], - new_off + msize)); - mem_3 =3D change_address (mem_3, VOIDmode, - plus_constant (DImode, - operands[8], - new_off + msize * 2)); - mem_4 =3D change_address (mem_4, VOIDmode, - plus_constant (DImode, - operands[8], - new_off + msize * 3)); - - if (code =3D=3D ZERO_EXTEND) - { - mem_1 =3D gen_rtx_ZERO_EXTEND (DImode, mem_1); - mem_2 =3D gen_rtx_ZERO_EXTEND (DImode, mem_2); - mem_3 =3D gen_rtx_ZERO_EXTEND (DImode, mem_3); - mem_4 =3D gen_rtx_ZERO_EXTEND (DImode, mem_4); - } - else if (code =3D=3D SIGN_EXTEND) - { - mem_1 =3D gen_rtx_SIGN_EXTEND (DImode, mem_1); - mem_2 =3D gen_rtx_SIGN_EXTEND (DImode, mem_2); - mem_3 =3D gen_rtx_SIGN_EXTEND (DImode, mem_3); - mem_4 =3D gen_rtx_SIGN_EXTEND (DImode, mem_4); - } =20 - if (load) - { - operands[1] =3D mem_1; - operands[3] =3D mem_2; - operands[5] =3D mem_3; - operands[7] =3D mem_4; - } - else - { - operands[0] =3D mem_1; - operands[2] =3D mem_2; - operands[4] =3D mem_3; - operands[6] =3D mem_4; - } + for (int i =3D 1; i < 4; i++) + mem[i] =3D change_address (mem[i], VOIDmode, + plus_constant (Pmode, + operands[8], + new_off + (msize * i))); + + for (int i =3D 0; i < 4; i++) + if (code =3D=3D ZERO_EXTEND) + mem[i] =3D gen_rtx_ZERO_EXTEND (Pmode, mem[i]); + else if (code =3D=3D SIGN_EXTEND) + mem[i] =3D gen_rtx_SIGN_EXTEND (Pmode, mem[i]); + + for (int i =3D 0; i < 4; i++) + operands[(2 * i) + op_offset] =3D mem[i]; =20 /* Emit adjusting instruction. */ - emit_insn (gen_rtx_SET (operands[8], plus_constant (DImode, base, adj_of= f))); + emit_insn (gen_rtx_SET (operands[8], plus_constant (Pmode, base, adj_off= ))); /* Emit ldp/stp instructions. */ t1 =3D gen_rtx_SET (operands[0], operands[1]); t2 =3D gen_rtx_SET (operands[2], operands[3]); --------------2.6.4.2.gae996d8--