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From: Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
To: <gcc-patches@gcc.gnu.org>
Cc: <Claudiu.Zissulescu@synopsys.com>, <gnu@amylaar.uk>,
	<Francois.Bedard@synopsys.com>
Subject: [PATCH] [ARC] Add simple shift/rotate ops.
Date: Fri, 17 Jun 2016 09:13:00 -0000	[thread overview]
Message-ID: <1466154788-5054-1-git-send-email-claziss@synopsys.com> (raw)

Basic ARC cpus are having only simple shift operations. Here they are.

OK to apply?
Claudiu

gcc/
2016-06-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (*rotrsi3_cnt1): New pattern,
	(*ashlsi2_cnt1, *lshrsi3_cnt1, *ashrsi3_cnt1): Likewise.
---
 gcc/config/arc/arc.md | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 852f0e0..a095ba1 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6219,6 +6219,46 @@
 		   (zero_extract:SI (match_dup 1) (match_dup 5) (match_dup 7)))])
    (match_dup 1)])
 
+(define_insn "*rotrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=w")
+	(rotatert:SI (match_operand:SI 1 "register_operand" "c")
+		     (const_int 1)))]
+  ""
+  "ror %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "predicable" "no")
+   (set_attr "length" "4")])
+
+(define_insn "*ashlsi2_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"           "=Rcqq,w")
+	(ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		   (const_int 1)))]
+  ""
+  "asl%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
+(define_insn "*lshrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=Rcqq,w")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		     (const_int 1)))]
+  ""
+  "lsr%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
+(define_insn "*ashrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=Rcqq,w")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		     (const_int 1)))]
+  ""
+  "asr%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
 ;; include the arc-FPX instructions
 (include "fpx.md")
 
-- 
1.9.1

             reply	other threads:[~2016-06-17  9:13 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-17  9:13 Claudiu Zissulescu [this message]
2016-09-27 14:29 ` Andrew Burgess
2016-09-28 13:54   ` Claudiu Zissulescu

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