From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 116987 invoked by alias); 17 Jun 2016 09:13:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 116970 invoked by uid 89); 17 Jun 2016 09:13:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=asl X-HELO: smtprelay.synopsys.com Received: from smtprelay.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 17 Jun 2016 09:13:39 +0000 Received: from dc8secmta2.synopsys.com (dc8secmta2.synopsys.com [10.13.218.202]) by smtprelay.synopsys.com (Postfix) with ESMTP id C70EF24E158E; Fri, 17 Jun 2016 02:13:35 -0700 (PDT) Received: from dc8secmta2.internal.synopsys.com (dc8secmta2.internal.synopsys.com [127.0.0.1]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id A6FC7A4112; Fri, 17 Jun 2016 02:13:35 -0700 (PDT) Received: from mailhost.synopsys.com (unknown [10.13.184.66]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id 89BACA4102; Fri, 17 Jun 2016 02:13:35 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 78F892CE; Fri, 17 Jun 2016 02:13:35 -0700 (PDT) Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id 5C5FE2CB; Fri, 17 Jun 2016 02:13:35 -0700 (PDT) Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 17 Jun 2016 02:13:35 -0700 Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.105) by IN01WEHTCA.internal.synopsys.com (10.144.199.103) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 17 Jun 2016 14:43:33 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCB.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 17 Jun 2016 14:43:32 +0530 From: Claudiu Zissulescu To: CC: , , Subject: [PATCH] [ARC] Add simple shift/rotate ops. Date: Fri, 17 Jun 2016 09:13:00 -0000 Message-ID: <1466154788-5054-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2016-06/txt/msg01290.txt.bz2 Basic ARC cpus are having only simple shift operations. Here they are. OK to apply? Claudiu gcc/ 2016-06-09 Claudiu Zissulescu * config/arc/arc.md (*rotrsi3_cnt1): New pattern, (*ashlsi2_cnt1, *lshrsi3_cnt1, *ashrsi3_cnt1): Likewise. --- gcc/config/arc/arc.md | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 852f0e0..a095ba1 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6219,6 +6219,46 @@ (zero_extract:SI (match_dup 1) (match_dup 5) (match_dup 7)))]) (match_dup 1)]) +(define_insn "*rotrsi3_cnt1" + [(set (match_operand:SI 0 "dest_reg_operand" "=w") + (rotatert:SI (match_operand:SI 1 "register_operand" "c") + (const_int 1)))] + "" + "ror %0,%1%&" + [(set_attr "type" "shift") + (set_attr "predicable" "no") + (set_attr "length" "4")]) + +(define_insn "*ashlsi2_cnt1" + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") + (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + (const_int 1)))] + "" + "asl%? %0,%1%&" + [(set_attr "type" "shift") + (set_attr "iscompact" "maybe,false") + (set_attr "predicable" "no,no")]) + +(define_insn "*lshrsi3_cnt1" + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + (const_int 1)))] + "" + "lsr%? %0,%1%&" + [(set_attr "type" "shift") + (set_attr "iscompact" "maybe,false") + (set_attr "predicable" "no,no")]) + +(define_insn "*ashrsi3_cnt1" + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + (const_int 1)))] + "" + "asr%? %0,%1%&" + [(set_attr "type" "shift") + (set_attr "iscompact" "maybe,false") + (set_attr "predicable" "no,no")]) + ;; include the arc-FPX instructions (include "fpx.md") -- 1.9.1