[PATCH 0/5] [ARC] Fixes backend issues

[PATCH 0/5] [ARC] Fixes backend issues

[Claudiu Zissulescu]

Hi Andrew,

This is a set of 5 patches that are fixing a number of issues observed
during dejagnu testing. Each patch has a small description about what
it solves.

Ok to apply?
Claudiu

Claudiu Zissulescu (5):
  [ARC] Save/restore blink when in ISR.
  [ARC] Fix detection of long immediate for load/store operands.
  [ARC] Disable TP register when building for bare metal.
  [ARC] Fix divdf3 emulation for arcem.
  [ARC] Fix move_double_src_operand predicate.

 gcc/config/arc/arc.c                       | 10 ++++++----
 gcc/config/arc/arc.md                      |  7 ++++++-
 gcc/config/arc/arc.opt                     |  2 +-
 gcc/config/arc/elf.h                       |  5 +++++
 gcc/config/arc/linux.h                     |  4 ++++
 gcc/config/arc/predicates.md               |  7 ++++++-
 gcc/testsuite/gcc.target/arc/interrupt-4.c | 15 +++++++++++++++
 libgcc/config/arc/ieee-754/divdf3.S        |  8 ++++----
 8 files changed, 47 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-4.c

-- 
1.9.1

[PATCH 1/5] [ARC] Save/restore blink when in ISR.

[Claudiu Zissulescu]

BLIBK register needs to be saved/restored in a interrupt. Fix this issue.

gcc/
2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_epilogue_uses): BLINK should be also
	restored when in interrupt.
	* config/arc/arc.md (simple_return): ARCv2 rtie instruction
	doesn't have delay slot.

gcc/testsuite/
2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/interrupt-4.c: New file.
---
 gcc/config/arc/arc.c                       | 10 ++++++----
 gcc/config/arc/arc.md                      |  7 ++++++-
 gcc/testsuite/gcc.target/arc/interrupt-4.c | 15 +++++++++++++++
 3 files changed, 27 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-4.c

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 556b587..50bfa11 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9513,9 +9513,10 @@ arc_can_follow_jump (const rtx_insn *follower, const rtx_insn *followee)
    Return true if REGNO should be added to the deemed uses of the epilogue.
 
    We use the return address
-   arc_return_address_regs[arc_compute_function_type (cfun)] .
-   But also, we have to make sure all the register restore instructions
-   are known to be live in interrupt functions.  */
+   arc_return_address_regs[arc_compute_function_type (cfun)].  But
+   also, we have to make sure all the register restore instructions
+   are known to be live in interrupt functions, plus the blink
+   register if it is clobbered by the isr.  */
 
 bool
 arc_epilogue_uses (int regno)
@@ -9528,7 +9529,8 @@ arc_epilogue_uses (int regno)
 	{
 	  if (!fixed_regs[regno])
 	    return true;
-	  return regno == arc_return_address_regs[cfun->machine->fn_type];
+	  return ((regno == arc_return_address_regs[cfun->machine->fn_type])
+		  || (regno == RETURN_ADDR_REGNUM));
 	}
       else
 	return regno == RETURN_ADDR_REGNUM;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a06c2ed..b912bd4 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4748,7 +4748,12 @@
   output_asm_insn (\"j%!%* [%0]%&\", &reg);
   return \"\";
 }
-  [(set_attr "type" "return")
+  [(set (attr "type")
+	(cond [(and (eq (symbol_ref "arc_compute_function_type (cfun)")
+			(symbol_ref "ARC_FUNCTION_ILINK1"))
+		    (match_test "TARGET_V2"))
+	       (const_string "brcc_no_delay_slot")]
+	      (const_string "return")))
    ; predicable won't help here since the canonical rtl looks different
    ; for branches.
    (set (attr "cond")
diff --git a/gcc/testsuite/gcc.target/arc/interrupt-4.c b/gcc/testsuite/gcc.target/arc/interrupt-4.c
new file mode 100644
index 0000000..ea6596e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/interrupt-4.c
@@ -0,0 +1,15 @@
+#if defined (__ARCHS__) || defined (__ARCEM__)
+#define RILINK "ilink"
+#else
+#define RILINK "ilink1"
+#endif
+
+extern int gpio_int;
+extern int read_reg (int);
+
+void __attribute__ ((interrupt(RILINK)))
+isr_handler (void)
+{
+  gpio_int = read_reg (1);
+}
+/* { dg-final { scan-assembler-times "blink" 2 } } */
-- 
1.9.1

Re: [PATCH 1/5] [ARC] Save/restore blink when in ISR.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-03-20 12:43:26 +0100]:

> BLIBK register needs to be saved/restored in a interrupt. Fix this issue.
> 
> gcc/
> 2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_epilogue_uses): BLINK should be also
> 	restored when in interrupt.
> 	* config/arc/arc.md (simple_return): ARCv2 rtie instruction
> 	doesn't have delay slot.

Looks good thanks,
Andrew



> 
> gcc/testsuite/
> 2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* gcc.target/arc/interrupt-4.c: New file.
> ---
>  gcc/config/arc/arc.c                       | 10 ++++++----
>  gcc/config/arc/arc.md                      |  7 ++++++-
>  gcc/testsuite/gcc.target/arc/interrupt-4.c | 15 +++++++++++++++
>  3 files changed, 27 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-4.c
> 
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 556b587..50bfa11 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -9513,9 +9513,10 @@ arc_can_follow_jump (const rtx_insn *follower, const rtx_insn *followee)
>     Return true if REGNO should be added to the deemed uses of the epilogue.
>  
>     We use the return address
> -   arc_return_address_regs[arc_compute_function_type (cfun)] .
> -   But also, we have to make sure all the register restore instructions
> -   are known to be live in interrupt functions.  */
> +   arc_return_address_regs[arc_compute_function_type (cfun)].  But
> +   also, we have to make sure all the register restore instructions
> +   are known to be live in interrupt functions, plus the blink
> +   register if it is clobbered by the isr.  */
>  
>  bool
>  arc_epilogue_uses (int regno)
> @@ -9528,7 +9529,8 @@ arc_epilogue_uses (int regno)
>  	{
>  	  if (!fixed_regs[regno])
>  	    return true;
> -	  return regno == arc_return_address_regs[cfun->machine->fn_type];
> +	  return ((regno == arc_return_address_regs[cfun->machine->fn_type])
> +		  || (regno == RETURN_ADDR_REGNUM));
>  	}
>        else
>  	return regno == RETURN_ADDR_REGNUM;
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index a06c2ed..b912bd4 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -4748,7 +4748,12 @@
>    output_asm_insn (\"j%!%* [%0]%&\", &reg);
>    return \"\";
>  }
> -  [(set_attr "type" "return")
> +  [(set (attr "type")
> +	(cond [(and (eq (symbol_ref "arc_compute_function_type (cfun)")
> +			(symbol_ref "ARC_FUNCTION_ILINK1"))
> +		    (match_test "TARGET_V2"))
> +	       (const_string "brcc_no_delay_slot")]
> +	      (const_string "return")))
>     ; predicable won't help here since the canonical rtl looks different
>     ; for branches.
>     (set (attr "cond")
> diff --git a/gcc/testsuite/gcc.target/arc/interrupt-4.c b/gcc/testsuite/gcc.target/arc/interrupt-4.c
> new file mode 100644
> index 0000000..ea6596e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arc/interrupt-4.c
> @@ -0,0 +1,15 @@
> +#if defined (__ARCHS__) || defined (__ARCEM__)
> +#define RILINK "ilink"
> +#else
> +#define RILINK "ilink1"
> +#endif
> +
> +extern int gpio_int;
> +extern int read_reg (int);
> +
> +void __attribute__ ((interrupt(RILINK)))
> +isr_handler (void)
> +{
> +  gpio_int = read_reg (1);
> +}
> +/* { dg-final { scan-assembler-times "blink" 2 } } */
> -- 
> 1.9.1
> 

[PATCH 4/5] [ARC] Fix divdf3 emulation for arcem.

[Claudiu Zissulescu]

Missing case for ARCEM cpus. Add it.

libgcc/
2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/ieee-754/divdf3.S (__divdf3): Use __ARCEM__.
---
 libgcc/config/arc/ieee-754/divdf3.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/libgcc/config/arc/ieee-754/divdf3.S b/libgcc/config/arc/ieee-754/divdf3.S
index 4d6aae2..b8085a6 100644
--- a/libgcc/config/arc/ieee-754/divdf3.S
+++ b/libgcc/config/arc/ieee-754/divdf3.S
@@ -189,13 +189,13 @@ __divdf3:
 	asl r8,DBL1H,12
 	lsr r12,DBL1L,20
 	lsr r4,r8,26
-#ifdef __HS__
+#if defined (__ARCHS__) || defined (__ARCEM__)
 	add3 r10,pcl,60 ; (.Ldivtab-.) >> 3
 #else
 	add3 r10,pcl,59 ; (.Ldivtab-.) >> 3
 #endif
 	ld.as r4,[r10,r4]
-#ifdef __HS__
+#if defined (__ARCHS__) || defined (__ARCEM__)
 	ld.as r9,[pcl,182]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
 #else
 	ld.as r9,[pcl,180]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
@@ -299,14 +299,14 @@ __divdf3:
 	rsub r7,r6,5
 	asr r10,r12,28
 	bmsk r4,r12,27
-#ifdef __HS__
+#if defined (__ARCHS__) || defined (__ARCEM__)
 	min  r7, r7, 31
 	asr  DBL0L, r4, r7
 #else
 	asrs DBL0L,r4,r7
 #endif
 	add DBL1H,r11,r10
-#ifdef __HS__
+#if defined (__ARCHS__) || defined (__ARCEM__)
 	abs.f r10, r4
 	sub.mi r10, r10, 1
 #endif
-- 
1.9.1

Re: [PATCH 4/5] [ARC] Fix divdf3 emulation for arcem.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-03-20 12:43:29 +0100]:

> Missing case for ARCEM cpus. Add it.
> 
> libgcc/
> 2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/ieee-754/divdf3.S (__divdf3): Use __ARCEM__.

Looks good, thanks,
Andrew


> ---
>  libgcc/config/arc/ieee-754/divdf3.S | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/libgcc/config/arc/ieee-754/divdf3.S b/libgcc/config/arc/ieee-754/divdf3.S
> index 4d6aae2..b8085a6 100644
> --- a/libgcc/config/arc/ieee-754/divdf3.S
> +++ b/libgcc/config/arc/ieee-754/divdf3.S
> @@ -189,13 +189,13 @@ __divdf3:
>  	asl r8,DBL1H,12
>  	lsr r12,DBL1L,20
>  	lsr r4,r8,26
> -#ifdef __HS__
> +#if defined (__ARCHS__) || defined (__ARCEM__)
>  	add3 r10,pcl,60 ; (.Ldivtab-.) >> 3
>  #else
>  	add3 r10,pcl,59 ; (.Ldivtab-.) >> 3
>  #endif
>  	ld.as r4,[r10,r4]
> -#ifdef __HS__
> +#if defined (__ARCHS__) || defined (__ARCEM__)
>  	ld.as r9,[pcl,182]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
>  #else
>  	ld.as r9,[pcl,180]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
> @@ -299,14 +299,14 @@ __divdf3:
>  	rsub r7,r6,5
>  	asr r10,r12,28
>  	bmsk r4,r12,27
> -#ifdef __HS__
> +#if defined (__ARCHS__) || defined (__ARCEM__)
>  	min  r7, r7, 31
>  	asr  DBL0L, r4, r7
>  #else
>  	asrs DBL0L,r4,r7
>  #endif
>  	add DBL1H,r11,r10
> -#ifdef __HS__
> +#if defined (__ARCHS__) || defined (__ARCEM__)
>  	abs.f r10, r4
>  	sub.mi r10, r10, 1
>  #endif
> -- 
> 1.9.1
> 

[PATCH 5/5] [ARC] Fix move_double_src_operand predicate.

[Claudiu Zissulescu]

Durring compilation process, (subreg (mem ...) ...) can occur. Hence,
we need to check if the address of mem is a valid one. This patch is
fixing this check by directly calling the address_operand, instead of
calling move_double_src_operand, as the latter is always checking
against the original mode, thus, returning false when the inner and
outer modes are different.

gcc/
2016-10-07  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/predicates.md (move_double_src_operand): Replace the
	call to move_double_src_operand with a call to address_operand.
---
 gcc/config/arc/predicates.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 8dd8d55..9e60cb7 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -318,7 +318,7 @@
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
       if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return move_double_src_operand (SUBREG_REG (op), mode);
+	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
       else
 	return register_operand (op, mode);
     case MEM :
-- 
1.9.1

Re: [PATCH 5/5] [ARC] Fix move_double_src_operand predicate.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-03-20 12:43:30 +0100]:

> Durring compilation process, (subreg (mem ...) ...) can occur. Hence,
> we need to check if the address of mem is a valid one. This patch is
> fixing this check by directly calling the address_operand, instead of
> calling move_double_src_operand, as the latter is always checking
> against the original mode, thus, returning false when the inner and
> outer modes are different.
> 
> gcc/
> 2016-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/predicates.md (move_double_src_operand): Replace the
> 	call to move_double_src_operand with a call to
> 	address_operand.

Sounds good, thanks,
Andrew


> ---
>  gcc/config/arc/predicates.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
> index 8dd8d55..9e60cb7 100644
> --- a/gcc/config/arc/predicates.md
> +++ b/gcc/config/arc/predicates.md
> @@ -318,7 +318,7 @@
>        /* (subreg (mem ...) ...) can occur here if the inner part was once a
>  	 pseudo-reg and is now a stack slot.  */
>        if (GET_CODE (SUBREG_REG (op)) == MEM)
> -	return move_double_src_operand (SUBREG_REG (op), mode);
> +	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
>        else
>  	return register_operand (op, mode);
>      case MEM :
> -- 
> 1.9.1
> 

[PATCH 2/5] [ARC] Fix detection of long immediate for load/store operands.

[Claudiu Zissulescu]

ARC can use scaled offsets when loading (i.e. ld.as rA,[base,
offset]).  Where base and offset can be a register or an immediate
operand.  The scaling only applies on the offset part of the
instruction.  The compiler can accept an address like this:

(plus:SI (mult:SI (reg:SI 2 r2 [orig:596 _2129 ] [596])
	          (const_int 4 [0x4]))
	 (const_int 60 [0x3c]))

Hence, to emit this instruction we place the (const_int 60) into base
and the register into offset to take advantage of the scaled offset
facility of the load instruction.  As a result the length of the load
instruction is 8 bytes.  However, the long_immediate_loadstore_operand
predicate used for calculating the length attribute doesn't recognize
this address and returns a wrong decision leading to a wrong length
computation for a load instruction using the above address.

gcc/
2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/predicates.md (long_immediate_loadstore_operand):
	Consider scaled addresses cases.
---
 gcc/config/arc/predicates.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 0dec736..8dd8d55 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -148,6 +148,11 @@
       {
 	rtx x = XEXP (op, 1);
 
+	if ((GET_CODE (XEXP (op, 0)) == MULT)
+	    && REG_P (XEXP (XEXP (op, 0), 0))
+	    && CONSTANT_P (x))
+	  return 1;
+
 	if (GET_CODE (x) == CONST)
 	  {
 	    x = XEXP (x, 0);
-- 
1.9.1

Re: [PATCH 2/5] [ARC] Fix detection of long immediate for load/store operands.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-03-20 12:43:27 +0100]:

> ARC can use scaled offsets when loading (i.e. ld.as rA,[base,
> offset]).  Where base and offset can be a register or an immediate
> operand.  The scaling only applies on the offset part of the
> instruction.  The compiler can accept an address like this:
> 
> (plus:SI (mult:SI (reg:SI 2 r2 [orig:596 _2129 ] [596])
> 	          (const_int 4 [0x4]))
> 	 (const_int 60 [0x3c]))
> 
> Hence, to emit this instruction we place the (const_int 60) into base
> and the register into offset to take advantage of the scaled offset
> facility of the load instruction.  As a result the length of the load
> instruction is 8 bytes.  However, the long_immediate_loadstore_operand
> predicate used for calculating the length attribute doesn't recognize
> this address and returns a wrong decision leading to a wrong length
> computation for a load instruction using the above address.
> 
> gcc/
> 2016-09-21  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/predicates.md (long_immediate_loadstore_operand):
> 	Consider scaled addresses cases.

Looks good thanks,
Andrew



> ---
>  gcc/config/arc/predicates.md | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
> index 0dec736..8dd8d55 100644
> --- a/gcc/config/arc/predicates.md
> +++ b/gcc/config/arc/predicates.md
> @@ -148,6 +148,11 @@
>        {
>  	rtx x = XEXP (op, 1);
>  
> +	if ((GET_CODE (XEXP (op, 0)) == MULT)
> +	    && REG_P (XEXP (XEXP (op, 0), 0))
> +	    && CONSTANT_P (x))
> +	  return 1;
> +
>  	if (GET_CODE (x) == CONST)
>  	  {
>  	    x = XEXP (x, 0);
> -- 
> 1.9.1
> 

[PATCH 3/5] [ARC] Disable TP register when building for bare metal.

[Claudiu Zissulescu]

No need for thread pointer in bare metal toolchain. Use TP register normally.

gcc/
2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/elf.h (ARGET_ARC_TP_REGNO_DEFAULT): Define.
	* config/arc/linux.h (ARGET_ARC_TP_REGNO_DEFAULT): Likewise.
	* config/arc/arc.opt (mtp-regno): Use ARGET_ARC_TP_REGNO_DEFAULT.
---
 gcc/config/arc/arc.opt | 2 +-
 gcc/config/arc/elf.h   | 5 +++++
 gcc/config/arc/linux.h | 4 ++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 17af736..6060ded 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -469,7 +469,7 @@ EnumValue
 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 
 mtp-regno=
-Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(25)
+Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 Specify thread pointer register number.
 
 mtp-regno=none
diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h
index d2106c5..a6d6c05 100644
--- a/gcc/config/arc/elf.h
+++ b/gcc/config/arc/elf.h
@@ -53,3 +53,8 @@ along with GCC; see the file COPYING3.  If not see
 #  define MULTILIB_DEFAULTS { "mcpu=" ARC_MULTILIB_CPU_DEFAULT }
 # endif
 #endif
+
+/* Bare-metal toolchains are not having a thread pointer register
+   set.  */
+#undef TARGET_ARC_TP_REGNO_DEFAULT
+#define TARGET_ARC_TP_REGNO_DEFAULT -1
diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
index 10c291c..1d10357 100644
--- a/gcc/config/arc/linux.h
+++ b/gcc/config/arc/linux.h
@@ -74,3 +74,7 @@ along with GCC; see the file COPYING3.  If not see
 /* We do not have any MULTILIB_OPTIONS specified, so there are no
    MULTILIB_DEFAULTS.  */
 #undef  MULTILIB_DEFAULTS
+
+/* Linux toolchains are using r25 as TLS register.  */
+#undef TARGET_ARC_TP_REGNO_DEFAULT
+#define TARGET_ARC_TP_REGNO_DEFAULT 25
-- 
1.9.1

Re: [PATCH 3/5] [ARC] Disable TP register when building for bare metal.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-03-20 12:43:28 +0100]:

> No need for thread pointer in bare metal toolchain. Use TP register normally.
> 
> gcc/
> 2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/elf.h (ARGET_ARC_TP_REGNO_DEFAULT): Define.
> 	* config/arc/linux.h (ARGET_ARC_TP_REGNO_DEFAULT): Likewise.
> 	* config/arc/arc.opt (mtp-regno): Use
> 	* ARGET_ARC_TP_REGNO_DEFAULT.

Looks fine.  I've suggested some alternative phrasing for the comments
to make them read a little easier.

Thanks,
Andrew



> ---
>  gcc/config/arc/arc.opt | 2 +-
>  gcc/config/arc/elf.h   | 5 +++++
>  gcc/config/arc/linux.h | 4 ++++
>  3 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
> index 17af736..6060ded 100644
> --- a/gcc/config/arc/arc.opt
> +++ b/gcc/config/arc/arc.opt
> @@ -469,7 +469,7 @@ EnumValue
>  Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
>  
>  mtp-regno=
> -Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(25)
> +Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
>  Specify thread pointer register number.
>  
>  mtp-regno=none
> diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h
> index d2106c5..a6d6c05 100644
> --- a/gcc/config/arc/elf.h
> +++ b/gcc/config/arc/elf.h
> @@ -53,3 +53,8 @@ along with GCC; see the file COPYING3.  If not see
>  #  define MULTILIB_DEFAULTS { "mcpu=" ARC_MULTILIB_CPU_DEFAULT }
>  # endif
>  #endif
> +
> +/* Bare-metal toolchains are not having a thread pointer register
> +   set.  */

/* Bare-metal toolchains do not need a thread pointer register.  */

> +#undef TARGET_ARC_TP_REGNO_DEFAULT
> +#define TARGET_ARC_TP_REGNO_DEFAULT -1
> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> index 10c291c..1d10357 100644
> --- a/gcc/config/arc/linux.h
> +++ b/gcc/config/arc/linux.h
> @@ -74,3 +74,7 @@ along with GCC; see the file COPYING3.  If not see
>  /* We do not have any MULTILIB_OPTIONS specified, so there are no
>     MULTILIB_DEFAULTS.  */
>  #undef  MULTILIB_DEFAULTS
> +
> +/* Linux toolchains are using r25 as TLS register.  */

/* Linux toolchains use r25 as the thread pointer register.  */

> +#undef TARGET_ARC_TP_REGNO_DEFAULT
> +#define TARGET_ARC_TP_REGNO_DEFAULT 25
> -- 
> 1.9.1
> 

RE: [PATCH 0/5] [ARC] Fixes backend issues

[Claudiu Zissulescu]

Hi Andrew,

>   [ARC] Save/restore blink when in ISR.
>   [ARC] Fix detection of long immediate for load/store operands.
>   [ARC] Disable TP register when building for bare metal.
>   [ARC] Fix divdf3 emulation for arcem.
>   [ARC] Fix move_double_src_operand predicate.
> 

All the above patches were successfully committed having the indicated mods.

Thank you for your review,
Claudiu

P.S. The ARC backend is broken due to some wrong patterns in simd.md. I've prepared a patch which fixes that.