* [PATCH 2/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for ADD insns.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
@ 2017-04-14 12:19 ` Claudiu Zissulescu
2017-04-14 12:19 ` [PATCH 4/7] [ARC] Make D0, D1 double regs fix when not used Claudiu Zissulescu
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:19 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-08 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_output_addsi): Check for h-register class
when emitting short ADD instructions.
---
gcc/config/arc/arc.c | 42 +++++++++++++++++++++++++++---------------
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d8ac6a6..8a8ac86 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -7455,6 +7455,10 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p)
int short_p = (!cond_p && short_0 && satisfies_constraint_Rcq (operands[1]));
int ret = 0;
+#define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \
+ && REGNO (OP) != 30) \
+ || !TARGET_V2))
+
#define ADDSI_OUTPUT1(FORMAT) do {\
if (output_p) \
output_asm_insn (FORMAT, operands);\
@@ -7477,32 +7481,40 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p)
but add1 r0,sp,35 doesn't. */
&& (!output_p || (get_attr_length (current_output_insn) & 2)))
{
+ /* Generate add_s a,b,c; add_s b,b,u7; add_s c,b,u3; add_s b,b,h
+ patterns. */
if (short_p
- && (REG_P (operands[2])
- ? (match || satisfies_constraint_Rcq (operands[2]))
- : (unsigned) intval <= (match ? 127 : 7)))
- ADDSI_OUTPUT1 ("add%? %0,%1,%2");
- if (short_0 && REG_P (operands[1]) && match2)
- ADDSI_OUTPUT1 ("add%? %0,%2,%1");
+ && ((REG_H_P (operands[2])
+ && (match || satisfies_constraint_Rcq (operands[2])))
+ || (CONST_INT_P (operands[2])
+ && ((unsigned) intval <= (match ? 127 : 7)))))
+ ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
+
+ /* Generate add_s b,b,h patterns. */
+ if (short_0 && match2 && REG_H_P (operands[1]))
+ ADDSI_OUTPUT1 ("add%? %0,%2,%1 ;2");
+
+ /* Generate add_s b,sp,u7; add_s sp,sp,u7 patterns. */
if ((short_0 || REGNO (operands[0]) == STACK_POINTER_REGNUM)
&& REGNO (operands[1]) == STACK_POINTER_REGNUM && !(intval & ~124))
- ADDSI_OUTPUT1 ("add%? %0,%1,%2");
+ ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
if ((short_p && (unsigned) neg_intval <= (match ? 31 : 7))
|| (REGNO (operands[0]) == STACK_POINTER_REGNUM
&& match && !(neg_intval & ~124)))
- ADDSI_OUTPUT1 ("sub%? %0,%1,%n2");
+ ADDSI_OUTPUT1 ("sub%? %0,%1,%n2 ;4");
- if (REG_P(operands[0]) && REG_P(operands[1])
- && (REGNO(operands[0]) <= 31) && (REGNO(operands[0]) == REGNO(operands[1]))
- && CONST_INT_P (operands[2]) && ( (intval>= -1) && (intval <= 6)))
- ADDSI_OUTPUT1 ("add%? %0,%1,%2");
+ /* Generate add_s h,h,s3 patterns. */
+ if (REG_H_P (operands[0]) && match && TARGET_V2
+ && CONST_INT_P (operands[2]) && ((intval>= -1) && (intval <= 6)))
+ ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;5");
- if (TARGET_CODE_DENSITY && REG_P(operands[0]) && REG_P(operands[1])
- && ((REGNO(operands[0]) == 0) || (REGNO(operands[0]) == 1))
+ /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */
+ if (TARGET_CODE_DENSITY && REG_P (operands[0]) && REG_P (operands[1])
+ && ((REGNO (operands[0]) == 0) || (REGNO (operands[0]) == 1))
&& satisfies_constraint_Rcq (operands[1])
&& satisfies_constraint_L (operands[2]))
- ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
+ ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6");
}
/* Now try to emit a 32 bit insn without long immediate. */
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/7] [ARC] Make D0, D1 double regs fix when not used.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
2017-04-14 12:19 ` [PATCH 2/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for ADD insns Claudiu Zissulescu
@ 2017-04-14 12:19 ` Claudiu Zissulescu
2017-04-14 12:19 ` [PATCH 1/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for CMP insns Claudiu Zissulescu
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:19 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_conditional_register_usage): Make D0, D1
double regs fix when not used.
---
gcc/config/arc/arc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 8a8ac86..f820622 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1546,6 +1546,11 @@ arc_conditional_register_usage (void)
arc_regno_reg_class[42] = ALL_REGS;
arc_regno_reg_class[43] = ALL_REGS;
+ fixed_regs[40] = 1;
+ fixed_regs[41] = 1;
+ fixed_regs[42] = 1;
+ fixed_regs[43] = 1;
+
arc_hard_regno_mode_ok[40] = 0;
arc_hard_regno_mode_ok[42] = 0;
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for CMP insns.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
2017-04-14 12:19 ` [PATCH 2/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for ADD insns Claudiu Zissulescu
2017-04-14 12:19 ` [PATCH 4/7] [ARC] Make D0, D1 double regs fix when not used Claudiu Zissulescu
@ 2017-04-14 12:19 ` Claudiu Zissulescu
2017-04-14 12:20 ` [PATCH 3/7] [ARC] Allow extension core registers to be used for addresses Claudiu Zissulescu
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:19 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-08 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (cmpsi_cc_insn_mixed): Use 'h' register
constraint.
(cmpsi_cc_c_insn): Likewise.
(cbranchsi4_scratch): Compute proper instruction length using
compact_hreg_operand.
* config/arc/predicates.md (compact_hreg_operand): New predicate.
---
gcc/config/arc/arc.md | 28 ++++++++++++++++------------
gcc/config/arc/predicates.md | 13 +++++++++++++
2 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index da760ed..053f8a6 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -3458,15 +3458,16 @@
;; modifed cc user if second, but not first operand is a compact register.
(define_insn "cmpsi_cc_insn_mixed"
[(set (reg:CC CC_REG)
- (compare:CC (match_operand:SI 0 "register_operand" "Rcq#q, h, c, c,qRcq,c")
- (match_operand:SI 1 "nonmemory_operand" "cO,Cm1,cI,cL, Cal,Cal")))]
+ (compare:CC (match_operand:SI 0 "register_operand" "Rcq#q,Rcqq, h, c, c,qRcq,c")
+ (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI,cL, Cal,Cal")))]
""
"cmp%? %0,%B1%&"
[(set_attr "type" "compare")
- (set_attr "iscompact" "true,true,false,false,true_limm,false")
- (set_attr "predicable" "no,no,no,yes,no,yes")
+ (set_attr "iscompact" "true,true,true,false,false,true_limm,false")
+ (set_attr "predicable" "no,no,no,no,yes,no,yes")
(set_attr "cond" "set")
- (set_attr "length" "*,*,4,4,*,8")])
+ (set_attr "length" "*,*,*,4,4,*,8")
+ (set_attr "cpu_facility" "av1,av2,*,*,*,*,*")])
(define_insn "*cmpsi_cc_zn_insn"
[(set (reg:CC_ZN CC_REG)
@@ -3542,14 +3543,15 @@
(define_insn "*cmpsi_cc_c_insn"
[(set (reg:CC_C CC_REG)
- (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq, h, c,Rcqq, c")
- (match_operand:SI 1 "nonmemory_operand" "cO,Cm1,cI, Cal,Cal")))]
+ (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c")
+ (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))]
""
"cmp%? %0,%S1%&"
[(set_attr "type" "compare")
- (set_attr "iscompact" "true,true,false,true_limm,false")
+ (set_attr "iscompact" "true,true,true,false,true_limm,false")
(set_attr "cond" "set")
- (set_attr "length" "*,*,4,*,8")])
+ (set_attr "length" "*,*,*,4,*,8")
+ (set_attr "cpu_facility" "av1,av2,*,*,*,*")])
;; Next come the scc insns.
@@ -4844,7 +4846,7 @@
return \"br%d0%* %1, %B2, %^%l3\";
/* FALLTHRU */
case 6: case 10:
- case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3%&;br%d0 out of range\";
+ case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3%& ;br%d0 out of range\";
default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length (insn)); fflush (stderr); gcc_unreachable ();
}
"
@@ -4874,13 +4876,15 @@
(minus (const_int 244)
(symbol_ref "get_attr_delay_slot_length (insn)"))))
(const_int 4)
- (match_operand:SI 1 "compact_register_operand" "")
+ (and (match_operand:SI 1 "compact_register_operand" "")
+ (match_operand:SI 2 "compact_hreg_operand" ""))
(const_int 6)]
(const_int 8))]
(cond [(and (ge (minus (match_dup 3) (pc)) (const_int -256))
(le (minus (match_dup 3) (pc)) (const_int 244)))
(const_int 8)
- (match_operand:SI 1 "compact_register_operand" "")
+ (and (match_operand:SI 1 "compact_register_operand" "")
+ (match_operand:SI 2 "compact_hreg_operand" ""))
(const_int 10)]
(const_int 12))))
(set (attr "iscompact")
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 9e60cb7..f4c2a80 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -189,6 +189,19 @@
}
)
+(define_predicate "compact_hreg_operand"
+ (match_code "reg, subreg")
+ {
+ if ((GET_MODE (op) != mode) && (mode != VOIDmode))
+ return 0;
+
+ return (GET_CODE (op) == REG)
+ && (REGNO (op) >= FIRST_PSEUDO_REGISTER
+ || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30)
+ || !TARGET_V2);
+ }
+)
+
;; Return true if OP is an acceptable memory operand for ARCompact
;; 16-bit store instructions
(define_predicate "compact_store_memory_operand"
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/7] [ARC] Allow extension core registers to be used for addresses.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
` (2 preceding siblings ...)
2017-04-14 12:19 ` [PATCH 1/7] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for CMP insns Claudiu Zissulescu
@ 2017-04-14 12:20 ` Claudiu Zissulescu
2017-04-14 12:20 ` [PATCH 7/7] [ARC] Addresses can use long immediate for offsets Claudiu Zissulescu
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (REGNO_OK_FOR_BASE_P): Consider also extension
core registers.
(REG_OK_FOR_INDEX_P_NONSTRICT): Likewise.
(REG_OK_FOR_BASE_P_NONSTRICT): Likewise.
---
gcc/config/arc/arc.h | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 0c7e561..9f6a272 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -640,7 +640,8 @@ extern enum reg_class arc_regno_reg_class[];
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \
|| ((unsigned) reg_renumber[REGNO] < 29) \
- || ((unsigned) (REGNO) == (unsigned) arc_tp_regno))
+ || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
+ || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)))
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
@@ -922,18 +923,15 @@ extern int arc_initial_elimination_offset(int from, int to);
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
-((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
- (unsigned) REGNO (X) < 29 || \
- (unsigned) REGNO (X) == 63 || \
- (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
+#define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
+ ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
+ || REGNO_OK_FOR_BASE_P (REGNO (X)))
+
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P_NONSTRICT(X) \
-((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
- (unsigned) REGNO (X) < 29 || \
- (unsigned) REGNO (X) == 63 || \
- (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
+#define REG_OK_FOR_BASE_P_NONSTRICT(X) \
+ ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
+ || REGNO_OK_FOR_BASE_P (REGNO (X)))
/* Nonzero if X is a hard reg that can be used as an index. */
#define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 7/7] [ARC] Addresses can use long immediate for offsets.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
` (3 preceding siblings ...)
2017-04-14 12:20 ` [PATCH 3/7] [ARC] Allow extension core registers to be used for addresses Claudiu Zissulescu
@ 2017-04-14 12:20 ` Claudiu Zissulescu
2017-04-14 12:20 ` [PATCH 5/7] [ARC] Use ACCL, ACCH registers whenever they are available Claudiu Zissulescu
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (LEGITIMATE_OFFSET_ADDRESS_P): Delete macro.
(legitimate_offset_address_p): New function.
(arc_legitimate_address_p): Use above function.
---
gcc/config/arc/arc.c | 44 +++++++++++++++++++++++++++++++++++---------
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 36582d2..a113c41 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -77,13 +77,6 @@ static const char *arc_cpu_string = arc_cpu_name;
? 0 \
: -(-GET_MODE_SIZE (MODE) | -4) >> 1)))
-#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, INDEX, STRICT) \
-(GET_CODE (X) == PLUS \
- && RTX_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
- && ((INDEX && RTX_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT)) \
- && GET_MODE_SIZE ((MODE)) <= 4) \
- || RTX_OK_FOR_OFFSET_P (MODE, XEXP (X, 1))))
-
#define LEGITIMATE_SCALED_ADDRESS_P(MODE, X, STRICT) \
(GET_CODE (X) == PLUS \
&& GET_CODE (XEXP (X, 0)) == MULT \
@@ -246,6 +239,39 @@ static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
/* Globally visible information about currently selected cpu. */
const arc_cpu_t *arc_selected_cpu;
+/* Check for constructions like REG + OFFS, where OFFS can be a
+ register, an immediate or an long immediate. */
+
+static bool
+legitimate_offset_address_p (enum machine_mode mode, rtx x, bool index,
+ bool strict)
+{
+ if (GET_CODE (x) != PLUS)
+ return false;
+
+ if (!RTX_OK_FOR_BASE_P (XEXP (x, 0), (strict)))
+ return false;
+
+ /* Check for: [Rx + small offset] or [Rx + Ry]. */
+ if (((index && RTX_OK_FOR_INDEX_P (XEXP (x, 1), (strict))
+ && GET_MODE_SIZE ((mode)) <= 4)
+ || RTX_OK_FOR_OFFSET_P (mode, XEXP (x, 1))))
+ return true;
+
+ /* Check for [Rx + symbol]. */
+ if (!flag_pic
+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ /* Avoid this type of address for double or larger modes. */
+ && (GET_MODE_SIZE (mode) <= 4)
+ /* Avoid small data which ends in something like GP +
+ symb@sda. */
+ && (!SYMBOL_REF_SMALL_P (XEXP (x, 1))
+ || TARGET_NO_SDATA_SET))
+ return true;
+
+ return false;
+}
+
/* Implements target hook vector_mode_supported_p. */
static bool
@@ -5600,7 +5626,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict)
{
if (RTX_OK_FOR_BASE_P (x, strict))
return true;
- if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, TARGET_INDEXED_LOADS, strict))
+ if (legitimate_offset_address_p (mode, x, TARGET_INDEXED_LOADS, strict))
return true;
if (LEGITIMATE_SCALED_ADDRESS_P (mode, x, strict))
return true;
@@ -5641,7 +5667,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY)
&& GET_CODE (XEXP ((x), 1)) == PLUS
&& rtx_equal_p (XEXP ((x), 0), XEXP (XEXP (x, 1), 0))
- && LEGITIMATE_OFFSET_ADDRESS_P (QImode, XEXP (x, 1),
+ && legitimate_offset_address_p (QImode, XEXP (x, 1),
TARGET_AUTO_MODIFY_REG, strict))
return true;
return false;
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 5/7] [ARC] Use ACCL, ACCH registers whenever they are available.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
` (4 preceding siblings ...)
2017-04-14 12:20 ` [PATCH 7/7] [ARC] Addresses can use long immediate for offsets Claudiu Zissulescu
@ 2017-04-14 12:20 ` Claudiu Zissulescu
2017-04-14 12:45 ` [PATCH 6/7] [ARC] [Cxx] Fix calling multiple inheritances Claudiu Zissulescu
2017-04-24 19:07 ` [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Andrew Burgess
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
gcc/
2016-12-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_conditional_register_usage): Use ACCL,
ACCH registers whenever they are available.
---
gcc/config/arc/arc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index f820622..73d72c68 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1588,6 +1588,15 @@ arc_conditional_register_usage (void)
SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], ACCH_REGNO);
SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCL_REGNO);
SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCH_REGNO);
+ SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCL_REGNO);
+ SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCH_REGNO);
+ SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCL_REGNO);
+ SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCH_REGNO);
+
+ /* Allow the compiler to freely use them. */
+ fixed_regs[ACCL_REGNO] = 0;
+ fixed_regs[ACCH_REGNO] = 0;
+
arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES;
}
}
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 6/7] [ARC] [Cxx] Fix calling multiple inheritances.
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
` (5 preceding siblings ...)
2017-04-14 12:20 ` [PATCH 5/7] [ARC] Use ACCL, ACCH registers whenever they are available Claudiu Zissulescu
@ 2017-04-14 12:45 ` Claudiu Zissulescu
2017-04-24 19:07 ` [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Andrew Burgess
7 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-14 12:45 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
The TARGET_ASM_OUTPUT_MI_THUNK hook doesn't take into account the
variant when we compile for PIC.
gcc/
2016-12-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_output_mi_thunk): Emit PIC calls.
---
gcc/config/arc/arc.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 73d72c68..36582d2 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -6434,10 +6434,28 @@ arc_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
fnaddr = XEXP (DECL_RTL (function), 0);
if (arc_is_longcall_p (fnaddr))
- fputs ("\tj\t", file);
+ {
+ if (flag_pic)
+ {
+ asm_fprintf (file, "\tld\t%s, [pcl, @",
+ ARC_TEMP_SCRATCH_REG);
+ assemble_name (file, XSTR (fnaddr, 0));
+ fputs ("@gotpc]\n", file);
+ asm_fprintf (file, "\tj\t[%s]", ARC_TEMP_SCRATCH_REG);
+ }
+ else
+ {
+ fputs ("\tj\t@", file);
+ assemble_name (file, XSTR (fnaddr, 0));
+ }
+ }
else
- fputs ("\tb\t", file);
- assemble_name (file, XSTR (fnaddr, 0));
+ {
+ fputs ("\tb\t@", file);
+ assemble_name (file, XSTR (fnaddr, 0));
+ if (flag_pic)
+ fputs ("@plt\n", file);
+ }
fputc ('\n', file);
}
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers
2017-04-14 12:17 [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Claudiu Zissulescu
` (6 preceding siblings ...)
2017-04-14 12:45 ` [PATCH 6/7] [ARC] [Cxx] Fix calling multiple inheritances Claudiu Zissulescu
@ 2017-04-24 19:07 ` Andrew Burgess
2017-04-25 12:29 ` Claudiu Zissulescu
7 siblings, 1 reply; 10+ messages in thread
From: Andrew Burgess @ 2017-04-24 19:07 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-04-14 14:14:37 +0200]:
> From: claziss <claziss@synopsys.com>
>
> Hi,
>
> There is an issue with 'h'- register class for ARCv2, which accepts
> only the first 32 general purposes registers as oposite to the ARCv1
> which accepts all 64 GPRs. Fix this issue in two patches for CMP and
> ADD instructions.
>
> Also, allow the compiler to use extra GPRs if they are available and
> mark D0, D1 registers fixed when not available.
>
> Fix also C++ calling multiple inheritances when compiling for PIC, and
> allow addresses to use Rx + @symbol.
These all look good.
Thanks,
Andrew
>
> --
>
> Claudiu Zissulescu (7):
> [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for CMP
> insns.
> [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for ADD
> insns.
> [ARC] Allow extension core registers to be used for addresses.
> [ARC] Make D0, D1 double regs fix when not used.
> [ARC] Use ACCL, ACCH registers whenever they are available.
> [ARC] [Cxx] Fix calling multiple inheritances.
> [ARC] Addresses can use long immediate for offsets.
>
> gcc/config/arc/arc.c | 124 +++++++++++++++++++++++++++++++++----------
> gcc/config/arc/arc.h | 20 ++++---
> gcc/config/arc/arc.md | 28 +++++-----
> gcc/config/arc/predicates.md | 13 +++++
> 4 files changed, 135 insertions(+), 50 deletions(-)
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers
2017-04-24 19:07 ` [PATCH 0/7] [ARC] Fix constraint letters and allow extra registers Andrew Burgess
@ 2017-04-25 12:29 ` Claudiu Zissulescu
0 siblings, 0 replies; 10+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 12:29 UTC (permalink / raw)
To: Andrew Burgess; +Cc: gcc-patches, Francois.Bedard
> These all look good.
>
> Thanks,
> Andrew
Committed in r247201, r247200, r247199, r247198, r247196, r247195, and r247194
Thank you for your review,
Claudiu
^ permalink raw reply [flat|nested] 10+ messages in thread