From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26231 invoked by alias); 25 May 2017 01:42:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 26219 invoked by uid 89); 25 May 2017 01:42:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=77, BMI, bmi X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 25 May 2017 01:42:53 +0000 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4P1cSJx041198 for ; Wed, 24 May 2017 21:42:55 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2anmywhq4d-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 24 May 2017 21:42:55 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 24 May 2017 21:42:52 -0400 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4P1gp3c11272496; Thu, 25 May 2017 01:42:51 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6947FB204E; Wed, 24 May 2017 21:40:28 -0400 (EDT) Received: from [9.85.167.119] (unknown [9.85.167.119]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP id 18514B204D; Wed, 24 May 2017 21:40:28 -0400 (EDT) Subject: [PATCH rs6000] Addition fixes to BMI intrinsic test From: Steven Munroe Reply-To: munroesj@linux.vnet.ibm.com To: gcc-patches Cc: Segher Boessenkool , David Edelsohn Content-Type: text/plain; charset="UTF-8" Date: Thu, 25 May 2017 02:17:00 -0000 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 17052501-0024-0000-0000-0000027A5C48 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007113; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000212; SDB=6.00865214; UDB=6.00429590; IPR=6.00644995; BA=6.00005372; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015574; XFM=3.00000015; UTC=2017-05-25 01:42:53 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052501-0025-0000-0000-0000441FFCF3 Message-Id: <1495676565.15444.31.camel@oc7878010663> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-05-24_18:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705250030 X-SW-Source: 2017-05/txt/msg01922.txt.bz2 Bill Seurer pointed out that building the BMI tests on a power8 but with gcc built --with-cpu=power6 fails with link errors. The intrinsics _pdep_u64/32 and _pext_u64/32 are guarded with #ifdef _ARCH_PWR7 as the implementation uses bpermd and popcntd instructions introduced with power7 (PowerISA-2.06). But if the GCC is built --with-cpu=power6, the compiler is capable of supporting -mcpu=power7 but will not generate bpermd/popcntd by default. Then if some code them uses say _pext_u64 with -mcpu=power6 the intrinsic is not not supported (needs power7) and so not defined. The dg tests are guarded with dg-require-effective-target powerpc_vsx_ok, This only tests if GCC and Binutils are capable of generating vsx (and by extension PowerISA-2.06 bpermd and popcntd) instructions. In this case the result is the intrinsic functions are implicitly defined as extern and cause a link failure. The solution is to guard the test code with #ifdef _ARCH_PWR7 so that it does not attempt to use instructions that are not there. However for dg-compile test bmi2-pext64-1a.c we have no alternative to add -mcpu=power7 to dg-options. [gcc/testsuite] 2017-05-24 Steven Munroe * gcc.target/powerpc/bmi2-pdep32-1.c [_ARCH_PWR7]: Prevent implicit function for processors without bpermd instruction. * gcc.target/powerpc/bmi2-pdep64-1.c: Likewise. * gcc.target/powerpc/bmi2-pext32-1.c: Likewise. * gcc.target/powerpc/bmi2-pext64-1.c: Likewise. * gcc.target/powerpc/bmi2-pext64-1a.c: Add -mcpu=power7 to dg-option. Index: gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c (revision 248381) +++ gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c (working copy) @@ -7,6 +7,7 @@ #include #include "bmi2-check.h" +#ifdef _ARCH_PWR7 __attribute__((noinline)) unsigned long long calc_pdep_u64 (unsigned long long a, unsigned long long mask) @@ -21,11 +22,13 @@ calc_pdep_u64 (unsigned long long a, unsigned long } return res; } +#endif /* _ARCH_PWR7 */ static void bmi2_test () { +#ifdef _ARCH_PWR7 unsigned long long i; unsigned long long src = 0xce7acce7acce7ac; unsigned long long res, res_ref; @@ -39,4 +42,5 @@ bmi2_test () if (res != res_ref) abort (); } +#endif /* _ARCH_PWR7 */ } Index: gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c (revision 248381) +++ gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c (working copy) @@ -7,6 +7,7 @@ #include #include "bmi2-check.h" +#ifdef _ARCH_PWR7 __attribute__((noinline)) unsigned long long calc_pext_u64 (unsigned long long a, unsigned long long mask) @@ -22,10 +23,12 @@ calc_pext_u64 (unsigned long long a, unsigned long return res; } +#endif /* _ARCH_PWR7 */ static void bmi2_test () { +#ifdef _ARCH_PWR7 unsigned long long i; unsigned long long src = 0xce7acce7acce7ac; unsigned long long res, res_ref; @@ -39,4 +42,5 @@ bmi2_test () if (res != res_ref) abort(); } +#endif /* _ARCH_PWR7 */ } Index: gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c (revision 248381) +++ gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c (working copy) @@ -7,6 +7,7 @@ #include #include "bmi2-check.h" +#ifdef _ARCH_PWR7 __attribute__((noinline)) unsigned calc_pdep_u32 (unsigned a, int mask) @@ -22,10 +23,12 @@ calc_pdep_u32 (unsigned a, int mask) return res; } +#endif /* _ARCH_PWR7 */ static void bmi2_test () { +#ifdef _ARCH_PWR7 unsigned i; unsigned src = 0xce7acc; unsigned res, res_ref; @@ -39,4 +42,5 @@ bmi2_test () if (res != res_ref) abort(); } +#endif /* _ARCH_PWR7 */ } Index: gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c (revision 248381) +++ gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3" } */ +/* { dg-options "-O3 -mcpu=power7" } */ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target powerpc_vsx_ok } */ Index: gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c (revision 248381) +++ gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c (working copy) @@ -7,6 +7,7 @@ #include #include "bmi2-check.h" +#ifdef _ARCH_PWR7 __attribute__((noinline)) unsigned calc_pext_u32 (unsigned a, unsigned mask) @@ -22,10 +23,12 @@ calc_pext_u32 (unsigned a, unsigned mask) return res; } +#endif /* _ARCH_PWR7 */ static void bmi2_test () { +#ifdef _ARCH_PWR7 unsigned i; unsigned src = 0xce7acc; unsigned res, res_ref; @@ -39,4 +42,5 @@ bmi2_test () if (res != res_ref) abort(); } +#endif /* _ARCH_PWR7 */ }