From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71158 invoked by alias); 26 May 2017 17:19:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 69876 invoked by uid 89); 26 May 2017 17:19:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=H*MI:171, H*m:171 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 26 May 2017 17:19:32 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4QHEAXH126493 for ; Fri, 26 May 2017 13:19:34 -0400 Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) by mx0a-001b2d01.pphosted.com with ESMTP id 2apqr1j2t1-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 26 May 2017 13:19:34 -0400 Received: from localhost by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 26 May 2017 11:19:29 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4QHJTxq15663372 for ; Fri, 26 May 2017 10:19:29 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 35BE7C603C for ; Fri, 26 May 2017 11:19:29 -0600 (MDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP id F3254C6043 for ; Fri, 26 May 2017 11:19:28 -0600 (MDT) Subject: [PATCH, rs6000] fold vector min/max in GIMPLE From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Content-Type: text/plain; charset="UTF-8" Date: Fri, 26 May 2017 17:19:00 -0000 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 17052617-0008-0000-0000-000007E234C0 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007121; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000212; SDB=6.00865921; UDB=6.00430066; IPR=6.00645783; BA=6.00005375; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015597; XFM=3.00000015; UTC=2017-05-26 17:19:31 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052617-0009-0000-0000-0000425418B7 Message-Id: <1495819168.15163.171.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-05-26_12:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705260308 X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg02067.txt.bz2 Hi, Add support for early expansion of vec_min, vec_max built-ins. Bootstraps currently running. OK for trunk? Thanks, -Will [gcc] 2017-05-26 Will Schmidt * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vec_min and vec_max builtins. (builtin_function_type): Add min/max unsigned variants to those identified as having unsigned arguments. [gcc/testsuite] 2017-05-26 Will Schmidt * testsuite/gcc.target/powerpc/fold-vec-minmax-char.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-floatdouble.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-int.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-short.c: New. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 104a052..ce6cc1b 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -17348,6 +17348,46 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* flavors of vec_min. */ + case VSX_BUILTIN_XVMINDP: + case P8V_BUILTIN_VMINSD: + case P8V_BUILTIN_VMINUD: + case ALTIVEC_BUILTIN_VMINSB: + case ALTIVEC_BUILTIN_VMINSH: + case ALTIVEC_BUILTIN_VMINSW: + case ALTIVEC_BUILTIN_VMINUB: + case ALTIVEC_BUILTIN_VMINUH: + case ALTIVEC_BUILTIN_VMINUW: + case ALTIVEC_BUILTIN_VMINFP: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* flavors of vec_max. */ + case VSX_BUILTIN_XVMAXDP: + case P8V_BUILTIN_VMAXSD: + case P8V_BUILTIN_VMAXUD: + case ALTIVEC_BUILTIN_VMAXSB: + case ALTIVEC_BUILTIN_VMAXSH: + case ALTIVEC_BUILTIN_VMAXSW: + case ALTIVEC_BUILTIN_VMAXUB: + case ALTIVEC_BUILTIN_VMAXUH: + case ALTIVEC_BUILTIN_VMAXUW: + case ALTIVEC_BUILTIN_VMAXFP: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } default: break; } @@ -18986,6 +19026,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, case MISC_BUILTIN_DIVDEU: case MISC_BUILTIN_DIVDEUO: case VSX_BUILTIN_UDIV_V2DI: + case ALTIVEC_BUILTIN_VMAXUB: + case ALTIVEC_BUILTIN_VMINUB: + case ALTIVEC_BUILTIN_VMAXUH: + case ALTIVEC_BUILTIN_VMINUH: + case ALTIVEC_BUILTIN_VMAXUW: + case ALTIVEC_BUILTIN_VMINUW: + case P8V_BUILTIN_VMAXUD: + case P8V_BUILTIN_VMINUD: h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-char.c new file mode 100644 index 0000000..9df6ecd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-char.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_min with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed char +test3_min (vector signed char x, vector signed char y) +{ + return vec_min (x, y); +} + +vector unsigned char +test6_min (vector unsigned char x, vector unsigned char y) +{ + return vec_min (x, y); +} + +vector signed char +test3_max (vector signed char x, vector signed char y) +{ + return vec_max (x, y); +} + +vector unsigned char +test6_max (vector unsigned char x, vector unsigned char y) +{ + return vec_max (x, y); +} + +/* { dg-final { scan-assembler-times "vminsb" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */ +/* { dg-final { scan-assembler-times "vminub" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxub" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-floatdouble.c new file mode 100644 index 0000000..1185ce2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-floatdouble.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_max with float and + double inputs for VSX produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector float +test1_min (vector float x, vector float y) +{ + return vec_min (x, y); +} + +vector double +test2_min (vector double x, vector double y) +{ + return vec_min (x, y); +} + +vector float +test1_max (vector float x, vector float y) +{ + return vec_max (x, y); +} + +vector double +test2_max (vector double x, vector double y) +{ + return vec_max (x, y); +} + +/* { dg-final { scan-assembler-times "vminsp" 1 } } */ +/* { dg-final { scan-assembler-times "vmindp" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsp" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxdp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-int.c new file mode 100644 index 0000000..1ce1c2b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-int.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_min with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed int +test3_min (vector signed int x, vector signed int y) +{ + return vec_min (x, y); +} + +vector unsigned int +test6_min (vector unsigned int x, vector unsigned int y) +{ + return vec_min (x, y); +} + +vector signed int +test3_max (vector signed int x, vector signed int y) +{ + return vec_max (x, y); +} + +vector unsigned int +test6_max (vector unsigned int x, vector unsigned int y) +{ + return vec_max (x, y); +} + +/* { dg-final { scan-assembler-times "vminsw" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ +/* { dg-final { scan-assembler-times "vminuw" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxuw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c new file mode 100644 index 0000000..ed9c66d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_min with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector" } */ + +#include + +vector signed long long +test3_min (vector signed long long x, vector signed long long y) +{ + return vec_min (x, y); +} + +vector unsigned long long +test6_min (vector unsigned long long x, vector unsigned long long y) +{ + return vec_min (x, y); +} + +vector signed long long +test3_max (vector signed long long x, vector signed long long y) +{ + return vec_max (x, y); +} + +vector unsigned long long +test6_max (vector unsigned long long x, vector unsigned long long y) +{ + return vec_max (x, y); +} + +/* { dg-final { scan-assembler-times "vminsd" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ +/* { dg-final { scan-assembler-times "vminud" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxud" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-short.c new file mode 100644 index 0000000..fa608c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-short.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_min with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed short +test3_min (vector signed short x, vector signed short y) +{ + return vec_min (x, y); +} + +vector unsigned short +test6_min (vector unsigned short x, vector unsigned short y) +{ + return vec_min (x, y); +} + +vector signed short +test3_max (vector signed short x, vector signed short y) +{ + return vec_max (x, y); +} + +vector unsigned short +test6_max (vector unsigned short x, vector unsigned short y) +{ + return vec_max (x, y); +} + +/* { dg-final { scan-assembler-times "vminsh" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */ +/* { dg-final { scan-assembler-times "vminuh" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxuh" 1 } } */