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From: Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
To: <gcc-patches@gcc.gnu.org>
Cc: <Claudiu.Zissulescu@synopsys.com>,	<Francois.Bedard@synopsys.com>,
	<andrew.burgess@embecosm.com>
Subject: [PATCH 4/7] [ARC] [LRA] Avoid emitting COND_EXEC during expand.
Date: Thu, 01 Jun 2017 13:37:00 -0000	[thread overview]
Message-ID: <1496324097-21221-5-git-send-email-claziss@synopsys.com> (raw)
In-Reply-To: <1496324097-21221-1-git-send-email-claziss@synopsys.com>

Emmitting COND_EXEC rtxes during expand does not always work.

gcc/
2017-01-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (clzsi2): Expand to an arc_clzsi2 instruction
	that also clobbers the CC register. The old expand code is moved
	to ...
	(*arc_clzsi2): ... here.
	(ctzsi2): Expand to an arc_ctzsi2 instruction that also clobbers
	the CC register. The old expand code is moved to ...
	(arc_ctzsi2): ... here.
---
 gcc/config/arc/arc.md | 41 ++++++++++++++++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 39bcc26..928feb1 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4533,9 +4533,21 @@
    (set_attr "type" "two_cycle_core,two_cycle_core")])
 
 (define_expand "clzsi2"
-  [(set (match_operand:SI 0 "dest_reg_operand" "")
-	(clz:SI (match_operand:SI 1 "register_operand" "")))]
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+	  (clz:SI (match_operand:SI 1 "register_operand" "")))
+     (clobber (match_dup 2))])]
+  "TARGET_NORM"
+  "operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);")
+
+(define_insn_and_split "*arc_clzsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(clz:SI (match_operand:SI 1 "register_operand" "r")))
+   (clobber (reg:CC_ZN CC_REG))]
   "TARGET_NORM"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
 {
   emit_insn (gen_norm_f (operands[0], operands[1]));
   emit_insn
@@ -4552,9 +4564,23 @@
 })
 
 (define_expand "ctzsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ctz:SI (match_operand:SI 1 "register_operand" "")))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")]
   "TARGET_NORM"
+  "
+  emit_insn (gen_arc_ctzsi2 (operands[0], operands[1]));
+  DONE;
+")
+
+(define_insn_and_split "arc_ctzsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ctz:SI (match_operand:SI 1 "register_operand" "r")))
+   (clobber (reg:CC_ZN CC_REG))
+   (clobber (match_scratch:SI 2 "=&r"))]
+  "TARGET_NORM"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
 {
   rtx temp = operands[0];
 
@@ -4562,10 +4588,10 @@
       || (REGNO (temp) < FIRST_PSEUDO_REGISTER
 	  && !TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
 				 REGNO (temp))))
-    temp = gen_reg_rtx (SImode);
+    temp = operands[2];
   emit_insn (gen_addsi3 (temp, operands[1], constm1_rtx));
   emit_insn (gen_bic_f_zn (temp, temp, operands[1]));
-  emit_insn (gen_clrsbsi2 (temp, temp));
+  emit_insn (gen_clrsbsi2 (operands[0], temp));
   emit_insn
     (gen_rtx_COND_EXEC
       (VOIDmode,
@@ -4575,7 +4601,8 @@
     (gen_rtx_COND_EXEC
       (VOIDmode,
        gen_rtx_GE (VOIDmode, gen_rtx_REG (CC_ZNmode, CC_REG), const0_rtx),
-       gen_rtx_SET (operands[0], gen_rtx_MINUS (SImode, GEN_INT (31), temp))));
+       gen_rtx_SET (operands[0], gen_rtx_MINUS (SImode, GEN_INT (31),
+						operands[0]))));
   DONE;
 })
 
-- 
1.9.1

  parent reply	other threads:[~2017-06-01 13:37 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-01 13:37 [PATCH 0/7] [ARC] Bug fixing, add support for naked functions Claudiu Zissulescu
2017-06-01 13:37 ` [PATCH 2/7] [ARC] Define ADDITIONAL_REGISTER_NAMES Claudiu Zissulescu
2017-06-16 19:37   ` Andrew Burgess
2017-07-10 13:57     ` Claudiu Zissulescu
2017-06-01 13:37 ` Claudiu Zissulescu [this message]
2017-07-13 11:38   ` [PATCH 4/7] [ARC] [LRA] Avoid emitting COND_EXEC during expand Andrew Burgess
2017-07-13 12:54     ` Claudiu Zissulescu
2017-07-17 13:02     ` Claudiu Zissulescu
2017-06-01 13:37 ` [PATCH 3/7] [ARC] [LRA] Fix tests asm constraints Claudiu Zissulescu
2017-06-16 19:37   ` Andrew Burgess
2017-07-10 13:56     ` Claudiu Zissulescu
2017-06-01 13:38 ` [PATCH 7/7] [ARC] Consolidate PIC implementation Claudiu Zissulescu
2017-07-13 13:31   ` Andrew Burgess
2017-07-17 11:05     ` Claudiu Zissulescu
2017-06-01 13:38 ` [PATCH 5/7] [ARC] Enable indexed loads for elf targers Claudiu Zissulescu
2017-07-13 11:55   ` Andrew Burgess
2017-07-13 13:08     ` Claudiu Zissulescu
2017-07-17 12:33     ` Claudiu Zissulescu
2017-06-01 13:38 ` [PATCH 1/7] [ARC] Add support for naked functions Claudiu Zissulescu
2017-06-16 19:36   ` Andrew Burgess
2017-06-19  9:55     ` [PATCH][ARC] " Claudiu Zissulescu
2017-07-13 11:21       ` Andrew Burgess
2017-07-17 10:47         ` Claudiu Zissulescu
2017-06-01 13:38 ` [PATCH 6/7] [ARC] Deprecate mexpand-adddi option Claudiu Zissulescu
2017-07-13 13:18   ` Andrew Burgess
2017-07-13 13:31     ` Claudiu Zissulescu
2017-07-17 13:01     ` Claudiu Zissulescu

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