From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 84980 invoked by alias); 21 Jun 2017 01:23:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 84953 invoked by uid 89); 21 Jun 2017 01:23:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KHOP_DYNAMIC,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=vui, 3.5, vsc X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 21 Jun 2017 01:23:41 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v5L1Na66024937 for ; Tue, 20 Jun 2017 21:23:39 -0400 Received: from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208]) by mx0a-001b2d01.pphosted.com with ESMTP id 2b7anss1m1-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 20 Jun 2017 21:23:39 -0400 Received: from localhost by e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 20 Jun 2017 21:23:36 -0400 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v5L1NZwO25165900; Wed, 21 Jun 2017 01:23:35 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A02D928041; Tue, 20 Jun 2017 21:23:29 -0400 (EDT) Received: from oc3304648336.ibm.com (unknown [9.85.130.216]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP id E564C28046; Tue, 20 Jun 2017 21:23:28 -0400 (EDT) Subject: [PATCH, rs6000] Add vec_reve support From: Carl Love To: gcc-patches@gcc.gnu.org, David Edelsohn , Segher Boessenkool Cc: Bill Schmidt , cel@us.ibm.com Date: Wed, 21 Jun 2017 01:23:00 -0000 Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 17062101-0044-0000-0000-000003571740 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007264; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00877692; UDB=6.00437250; IPR=6.00657829; BA=6.00005432; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015905; XFM=3.00000015; UTC=2017-06-21 01:23:37 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17062101-0045-0000-0000-000007851E31 Message-Id: <1498008213.20531.1.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-20_13:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706210023 X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01530.txt.bz2 GCC maintainers: This patch adds support for the various vec_reve builtins. The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE) and on powerpc64-unknown-linux-gnu (Power 8 BE) with no regressions. Is the patch OK for gcc mainline? Carl Love ------------------------------------------------------- gcc/ChangeLog: 2017-06-20 Carl Love * config/rs6000/rs6000-c.c: Add support for built-in functions vector bool char vec_reve (vector bool char); vector signed char vec_reve (vector signed char); vector unsigned char vec_reve (vector unsigned char); vector bool int vec_reve (vector bool int); vector signed int vec_reve (vector signed int); vector unsigned int vec_reve (vector unsigned int); vector bool long long vec_reve (vector bool long long); vector signed long long vec_reve (vector signed long long); vector unsigned long long vec_reve (vector unsigned long long); vector bool short vec_reve (vector bool short); vector signed short vec_reve (vector signed short); vector double vec_reve (vector double); vector float vec_reve (vector float); * config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI, VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New * config/rs6000/altivec.md (UNSPEC_VREVEV, VEC_A_size, altivec_vrev): New UNSPEC, new mode_attr, new patterns. * config/rs6000/altivec.h (vec_reve): New define * doc/extend.texi (vec_rev): Update the built-in documentation file for the new built-in functions. gcc/testsuite/ChangeLog: 2017-06-20 Carl Love * gcc.target/powerpc/builtins-3-vec_reve-runable.c (test_results, main): Add new runnable test file for the vec_rev built-ins. --- gcc/config/rs6000/altivec.h | 1 + gcc/config/rs6000/altivec.md | 31 +++ gcc/config/rs6000/rs6000-builtin.def | 9 + gcc/config/rs6000/rs6000-c.c | 29 +++ gcc/doc/extend.texi | 13 ++ .../powerpc/builtins-3-vec_reve-runnable.c | 251 +++++++++++++++++++++ 6 files changed, 334 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index d542315..98ccfd2 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -142,6 +142,7 @@ #define vec_madd __builtin_vec_madd #define vec_madds __builtin_vec_madds #define vec_mtvscr __builtin_vec_mtvscr +#define vec_reve __builtin_vec_vreve #define vec_vmaxfp __builtin_vec_vmaxfp #define vec_vmaxsw __builtin_vec_vmaxsw #define vec_vmaxsh __builtin_vec_vmaxsh diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 25b2768..800d70c 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -46,6 +46,7 @@ UNSPEC_VPACK_UNS_UNS_SAT UNSPEC_VPACK_UNS_UNS_MOD UNSPEC_VPACK_UNS_UNS_MOD_DIRECT + UNSPEC_VREVEV UNSPEC_VSLV4SI UNSPEC_VSLO UNSPEC_VSR @@ -231,6 +232,11 @@ ;; Vector negate (define_mode_iterator VNEG [V4SI V2DI]) +;; Vector reverse elements, uses define_mode_iterator VEC_A +;; size in bytes of the vector element +(define_mode_attr VEC_A_size [(V2DI "8") (V4SI "4") (V8HI "2") + (V16QI "1") (V2DF "8") (V4SF "4")]) + ;; Vector move instructions. (define_insn "*altivec_mov" [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,?Y,?*r,?*r,v,v,?*r") @@ -3727,6 +3733,31 @@ DONE; }") +;; Vector reverse elements +(define_expand "altivec_vreve2" + [(set (match_operand:VEC_A 0 "register_operand" "=v") + (unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")] + UNSPEC_VREVEV))] + "TARGET_ALTIVEC" +{ + int i, j, k, size, num_elements; + rtvec v = rtvec_alloc (16); + rtx mask = gen_reg_rtx (V16QImode); + + size = ; + num_elements = 16 / size; + k = 0; + + for (j = num_elements-1; j >= 0; j--) + for (i = 0; i < size; i++) + RTVEC_ELT (v, i + j*size) = gen_rtx_CONST_INT (QImode, k++); + + emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); + emit_insn (gen_altivec_vperm_ (operands[0], operands[1], + operands[1], mask)); + DONE; +}) + ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL, ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell. (define_insn "altivec_lvlx" diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 4682628..20974b4 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1130,6 +1130,13 @@ BU_ALTIVEC_1 (VUPKLSB, "vupklsb", CONST, altivec_vupklsb) BU_ALTIVEC_1 (VUPKLPX, "vupklpx", CONST, altivec_vupklpx) BU_ALTIVEC_1 (VUPKLSH, "vupklsh", CONST, altivec_vupklsh) +BU_ALTIVEC_1 (VREVE_V2DI, "vreve_v2di", CONST, altivec_vrevev2di2) +BU_ALTIVEC_1 (VREVE_V4SI, "vreve_v4si", CONST, altivec_vrevev4si2) +BU_ALTIVEC_1 (VREVE_V8HI, "vreve_v8hi", CONST, altivec_vrevev8hi2) +BU_ALTIVEC_1 (VREVE_V16QI, "vreve_v16qi", CONST, altivec_vrevev16qi2) +BU_ALTIVEC_1 (VREVE_V2DF, "vreve_v2df", CONST, altivec_vrevev2df2) +BU_ALTIVEC_1 (VREVE_V4SF, "vreve_v4sf", CONST, altivec_vrevev4sf2) + BU_ALTIVEC_1 (FLOAT_V4SI_V4SF, "float_sisf", FP, floatv4siv4sf2) BU_ALTIVEC_1 (UNSFLOAT_V4SI_V4SF, "uns_float_sisf", FP, floatunsv4siv4sf2) BU_ALTIVEC_1 (FIX_V4SF_V4SI, "fix_sfsi", FP, fix_truncv4sfv4si2) @@ -1414,6 +1421,8 @@ BU_ALTIVEC_OVERLOAD_1 (VUPKLPX, "vupklpx") BU_ALTIVEC_OVERLOAD_1 (VUPKLSB, "vupklsb") BU_ALTIVEC_OVERLOAD_1 (VUPKLSH, "vupklsh") +BU_ALTIVEC_OVERLOAD_1 (VREVE, "vreve") + /* Overloaded altivec predicates. */ BU_ALTIVEC_OVERLOAD_P (VCMPEQ_P, "vcmpeq_p") BU_ALTIVEC_OVERLOAD_P (VCMPGT_P, "vcmpgt_p") diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 19f6d9c..07738e2 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -5521,6 +5521,35 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + /* Crypto builtins. */ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 43f9ecf..7f5191d 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -16558,6 +16558,19 @@ vector bool char vec_perm (vector bool char, vector float vec_re (vector float); +vector bool char vec_reve (vector bool char); +vector signed char vec_reve (vector signed char); +vector unsigned char vec_reve (vector unsigned char); +vector bool int vec_reve (vector bool int); +vector signed int vec_reve (vector signed int); +vector unsigned int vec_reve (vector unsigned int); +vector bool long long vec_reve (vector bool long long); +vector signed long long vec_reve (vector signed long long); +vector unsigned long long vec_reve (vector unsigned long long); +vector bool short vec_reve (vector bool short); +vector signed short vec_reve (vector signed short); +vector unsigned short vec_reve (vector unsigned short); + vector signed char vec_rl (vector signed char, vector unsigned char); vector unsigned char vec_rl (vector unsigned char, diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c new file mode 100644 index 0000000..a4bb5bf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c @@ -0,0 +1,251 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target vsx_hw } */ +/* { dg-options "-O2 -mvsx -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + +#include // vector + +#define VBC 0 +#define VSC 1 +#define VUC 2 +#define VBS 3 +#define VSS 4 +#define VUS 5 +#define VBI 6 +#define VI 7 +#define VUI 8 +#define VLLB 9 +#define VLLI 10 +#define VLLUI 11 +#define VF 12 +#define VD 13 + +union vector_value +{ + vector bool char vbc; + vector signed char vsc; + vector unsigned char vuc; + vector bool short vbs; + vector signed short vss; + vector unsigned short vus; + vector bool int vbi; + vector signed int vi; + vector unsigned int vui; + vector bool long long vllb; + vector long long signed int vlli; + vector long long unsigned int vllui; + vector float vf; + vector double vd; +} vec_element; + +struct vector_struct +{ + int vector_id; + int element_size; // element size in bytes + union vector_value vec; +} vec; + +void abort (void); + +void test_results(struct vector_struct *vec_result, + struct vector_struct *vec_expected) +{ + int i; + int num_elements; + if (vec_result->element_size != vec_expected->element_size) + abort(); + + if (vec_result->vector_id != vec_expected->vector_id) + abort(); + + num_elements = 16 / vec_result->element_size; + + for (i = 0; ivector_id) { + case VBC: + if (vec_result->vec.vbc[i] != vec_expected->vec.vbc[i]) + abort(); + break; + + case VSC: + if (vec_result->vec.vsc[i] != vec_expected->vec.vsc[i]) + abort(); + break; + + case VUC: + if (vec_result->vec.vuc[i] != vec_expected->vec.vuc[i]) + abort(); + break; + + case VBS: + if (vec_result->vec.vbs[i] != vec_expected->vec.vbs[i]) + abort(); + break; + + case VSS: + if (vec_result->vec.vss[i] != vec_expected->vec.vss[i]) + abort(); + break; + + case VUS: + if (vec_result->vec.vus[i] != vec_expected->vec.vus[i]) + abort(); + break; + + case VBI: + if (vec_result->vec.vbi[i] != vec_expected->vec.vbi[i]) + abort(); + break; + + case VI: + if (vec_result->vec.vi[i] != vec_expected->vec.vi[i]) + abort(); + break; + + case VUI: + if (vec_result->vec.vui[i] != vec_expected->vec.vui[i]) + abort(); + break; + + case VLLB: + if (vec_result->vec.vllb[i] != vec_expected->vec.vllb[i]) + abort(); + break; + + case VLLI: + if (vec_result->vec.vlli[i] != vec_expected->vec.vlli[i]) + abort(); + break; + + case VLLUI: + if (vec_result->vec.vllui[i] != vec_expected->vec.vllui[i]) + abort(); + break; + + case VF: + if (vec_result->vec.vf[i] != vec_expected->vec.vf[i]) + abort(); + break; + + case VD: + if (vec_result->vec.vd[i] != vec_expected->vec.vd[i]) + abort(); + break; + + default: abort(); + } + } +} + +int main() +{ + int i; + struct vector_struct vec_src, vec_expected, vec_result; + + vec_src.vec.vbc = (vector bool char){ 0, 1, 0, 0, 1, 1, 0, 0, + 0, 1, 1, 1, 0, 0, 0, 0 }; + vec_expected.vec.vbc = (vector bool char){ 0, 0, 0, 0, 1, 1, 1, 0, + 0, 0, 1, 1, 0, 0, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VBC; + vec_result.vec.vbc = vec_reve (vec_src.vec.vbc); + test_results(&vec_result, &vec_expected); + + vec_src.vec.vsc = (vector signed char){ 0, 1, -2, -3, 4, 5, -6, -7, 8, + 9, -10, -11, 12, 13, -14, -15 }; + vec_expected.vec.vsc = (vector signed char){ -15, -14, 13, 12, -11, -10, + 9, 8, -7, -6, 5, 4, -3, -2, + 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VSC; + vec_result.vec.vsc = vec_reve (vec_src.vec.vsc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vuc = (vector unsigned char){ 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25 }; + vec_expected.vec.vuc = (vector unsigned char){ 25, 24, 23, 22, 21, 20, + 19, 18, 17, 16, 15, 14, 13, + 12, 11, 10 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VUC; + vec_result.vec.vuc = vec_reve (vec_src.vec.vuc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbs = (vector bool short){ 0, 0, 1, 1, 0, 1, 0, 1 }; + vec_expected.vec.vbs = (vector bool short){ 1, 0, 1, 0, 1, 1, 0, 0 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VBS; + vec_result.vec.vbs = vec_reve (vec_src.vec.vbs); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vss = (vector signed short){ -1, -2, 3, 4, -5, -6, 7, 8 }; + vec_expected.vec.vss = (vector signed short){ 8, 7, -6, -5, 4, 3, -2, -1 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VSS; + vec_result.vec.vss = vec_reve (vec_src.vec.vss); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vus = (vector unsigned short){ 11, 22, 33, 44, 55, 66, 77, 88 }; + vec_expected.vec.vus = (vector unsigned short){ 88, 77, 66, 55, + 44, 33, 22, 11 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VUS; + vec_result.vec.vus = vec_reve (vec_src.vec.vus); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbi = (vector bool int){ 0, 1, 1, 1 }; + vec_expected.vec.vbi = (vector bool int){ 1, 1, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VBI; + vec_result.vec.vbi = vec_reve (vec_src.vec.vbi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vi = (vector signed int){ -1, 3, -5, 1234567 }; + vec_expected.vec.vi = (vector signed int){1234567, -5, 3, -1}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VI; + vec_result.vec.vi = vec_reve (vec_src.vec.vi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vui = (vector unsigned int){ 9, 11, 15, 2468013579 }; + vec_expected.vec.vui = (vector unsigned int){2468013579, 15, 11, 9}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VUI; + vec_result.vec.vui = vec_reve (vec_src.vec.vui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllb = (vector bool long long ){ 0, 1 }; + vec_expected.vec.vllb = (vector bool long long){1, 0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLB; + vec_result.vec.vllb = vec_reve (vec_src.vec.vllb); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vlli = (vector long long int){ -12, -12345678901234 }; + vec_expected.vec.vlli = (vector long long int){-12345678901234, -12}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLI; + vec_result.vec.vlli = vec_reve (vec_src.vec.vlli); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllui = (vector unsigned long long int){ 102, 9753108642 }; + vec_expected.vec.vllui = (vector unsigned long long int){9753108642, 102}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLUI; + vec_result.vec.vllui = vec_reve (vec_src.vec.vllui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vf = (vector float){ -21., 3.5, -53., 78. }; + vec_expected.vec.vf = (vector float){78., -53, 3.5, -21}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VF; + vec_result.vec.vf = vec_reve (vec_src.vec.vf); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vd = (vector double){ 34.0, 97.0 }; + vec_expected.vec.vd = (vector double){97.0, 34.0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VD; + vec_result.vec.vd = vec_reve (vec_src.vec.vd); + test_results (&vec_result, &vec_expected); +} -- 1.9.1