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Violators will be prosecuted; Fri, 27 Oct 2017 12:49:05 -0400 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v9RGn5qn48758992; Fri, 27 Oct 2017 16:49:05 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FAE62803F; Fri, 27 Oct 2017 12:48:58 -0400 (EDT) Received: from oc3304648336.ibm.com (unknown [9.70.82.190]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP id AF6C72803D; Fri, 27 Oct 2017 12:48:57 -0400 (EDT) Subject: Re: [PATCH, rs6000 V3] Add Power 8 support to vec_revb From: Carl Love To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, David Edelsohn , Bill Schmidt Date: Fri, 27 Oct 2017 16:52:00 -0000 In-Reply-To: <20171026215656.GN4406@gate.crashing.org> References: <1508772963.16660.28.camel@us.ibm.com> <20171026215656.GN4406@gate.crashing.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 x-cbid: 17102716-0052-0000-0000-00000278B0D0 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007962; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000239; SDB=6.00937288; UDB=6.00472396; IPR=6.00717550; BA=6.00005660; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017745; XFM=3.00000015; UTC=2017-10-27 16:49:07 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17102716-0053-0000-0000-000052733933 Message-Id: <1509122944.9048.57.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-10-27_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710270220 X-IsSubscribed: yes X-SW-Source: 2017-10/txt/msg02100.txt.bz2 Segher: I still have issues with the . > > +(define_mode_attr VSX_XXBR [(V16QI "q") > > + (V8HI "h") > > + (V4SI "w") > > + (V4SF "w") > > + (V2DF "d") > > + (V2DI "d") > > + (V1TI "q")]) > > So I think this is wrong for V16QI. You can use fine, but you need > to avoid generating "xxbrb" insns; instead, do a register move? xxbrq > isn't the insn you want, as far as I see. > > > +;; Swap all bytes in each element of vector > > +(define_expand "revb_" > > + [(set (match_operand:VEC_A 0 "vsx_register_operand") > > + (bswap:VEC_A (match_operand:VEC_A 1 "vsx_register_operand")))] > > + "TARGET_P9_VECTOR" > > +{ > > + rtx sel; > > So a special case here: > > if (mode == V16QImode) > { > emit_move_insn (operands[0], operands[1]); > DONE; > } Even if I put in the above special case, I still have issues with the . The updated code for the expand with the special case above is (define_expand "revb_" [(set (match_operand:VEC_A 0 "vsx_register_operand") (bswap:VEC_A (match_operand:VEC_A 1 "vsx_register_operand")))] "TARGET_P8_VECTOR" { rtx sel; if (TARGET_P9_VECTOR) if (mode == V16QImode) emit_move_insn (operands[0], operands[1]); else emit_insn (gen_p9_xxbr_ (operands[0], operands[1])); etc. The issue is the if (mode == V16QImode) does not prevent the code in the else statement from getting expanded for . I agree it will prevent the generation of the instruction but the code is still expanded and compiled. I get the error message: /home/carll/GCC/gcc-revb/gcc/config/rs6000/vsx.md:4727:62: error: ‘gen_p9_xxbrb_v16qi’ was not declared in this scope emit_insn (gen_p9_xxbr_ (operands[0], operands[1])); Because for mode v16qi still gets expanded to "b" not "q". There is no definition for "gen_p9_xxbrb_v16qi" since xxbrb is not vaild. Short of using a different expander for I don't see how to not get the expansion. Sorry if I am missing something obvious here. Carl Love