From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 64122 invoked by alias); 14 Feb 2018 20:08:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 64020 invoked by uid 89); 14 Feb 2018 20:08:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Feb 2018 20:08:41 +0000 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w1EK3kde028014 for ; Wed, 14 Feb 2018 15:08:40 -0500 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0b-001b2d01.pphosted.com with ESMTP id 2g4te13mqq-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 14 Feb 2018 15:08:39 -0500 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 14 Feb 2018 13:08:38 -0700 Received: from b03cxnp07029.gho.boulder.ibm.com (9.17.130.16) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 14 Feb 2018 13:08:36 -0700 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w1EK8ads12321096; Wed, 14 Feb 2018 13:08:36 -0700 Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 60F02136046; Wed, 14 Feb 2018 13:08:36 -0700 (MST) Received: from oc3304648336.ibm.com (unknown [9.70.82.121]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP id 1792C136040; Wed, 14 Feb 2018 13:08:36 -0700 (MST) Subject: [PATCH, rs6000] Remove non-ABI builtin support for vec_insert4b, vec_extract4b From: Carl Love To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, David Edelsohn , Bill Schmidt Date: Wed, 14 Feb 2018 20:08:00 -0000 Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 x-cbid: 18021420-0004-0000-0000-000013A8FC25 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008534; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000253; SDB=6.00989742; UDB=6.00502590; IPR=6.00769096; BA=6.00005830; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019554; XFM=3.00000015; UTC=2018-02-14 20:08:38 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18021420-0005-0000-0000-000086157294 Message-Id: <1518638915.7508.31.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-02-14_08:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802140234 X-IsSubscribed: yes X-SW-Source: 2018-02/txt/msg00864.txt.bz2 GCC maintainers: This is the second patch that removes the non-ABI vec_insert4b and vec_extract4b builtin support. It also removes the two existing test files for the non-ABI builtin instances. A runnable test file for the ABI specified builtins was added by the first patch. This patch has been tested on:   powerpc64le-unknown-linux-gnu (Power 8 LE)   powerpc64le-unknown-linux-gnu (Power 9 LE) with no regressions. Let me know if the patch looks OK or not. Thanks. The patch should also be ported to GCC 7 so we are in compliance with the ABI.                            Carl Love ----------------------------------------------------------------------- gcc/ChangeLog: 2018-02-13 Carl Love * config/rs6000/altivec.h: Remove vec_vextract4b and vec_vinsert4b. * config/rs6000/rs6000-builtin.def: Remove macro expansion for VEXTRACT4B, VINSERT4B, VINSERT4B_DI and VEXTRACT4B. * config/rs6000/rs6000.c: Remove case statements for P9V_BUILTIN_VEXTRACT4B, P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, and P9V_BUILTIN_VEC_VINSERT4B. * config/rs6000/rs6000-c.c (altivec_expand_builtin): Remove entries for P9V_BUILTIN_VEC_VEXTRACT4B and P9V_BUILTIN_VEC_VINSERT4B. * config/rs6000/vsx.md: * doc/extend.texi: Remove vec_vextract4b, non ABI definitions for vec_insert4b. gcc/testsuite/ChangeLog: 2018-02-13 Carl Love * gcc.target/powerpc/p9-vinsert4b-1.c: Remove test file for non-ABI tests. * gcc.target/powerpc/p9-vinsert4b-2.c: Remove test file for non-ABI tests. --- gcc/config/rs6000/altivec.h | 2 - gcc/config/rs6000/rs6000-builtin.def | 5 -- gcc/config/rs6000/rs6000-c.c | 25 ------- gcc/config/rs6000/rs6000.c | 5 -- gcc/config/rs6000/vsx.md | 87 ----------------------- gcc/doc/extend.texi | 11 +-- gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c | 39 ---------- gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c | 30 -------- 8 files changed, 1 insertion(+), 203 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 3bce2ae39..1e495e69c 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -433,8 +433,6 @@ #define vec_vctzd __builtin_vec_vctzd #define vec_vctzh __builtin_vec_vctzh #define vec_vctzw __builtin_vec_vctzw -#define vec_vextract4b __builtin_vec_vextract4b -#define vec_vinsert4b __builtin_vec_vinsert4b #define vec_extract4b __builtin_vec_extract4b #define vec_insert4b __builtin_vec_insert4b #define vec_vprtyb __builtin_vec_vprtyb diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 420d12e29..16fb18d53 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2226,9 +2226,6 @@ BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx) BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx) /* Insert/extract 4 byte word into a vector. */ -BU_P9V_VSX_2 (VEXTRACT4B, "vextract4b", CONST, vextract4b) -BU_P9V_VSX_3 (VINSERT4B, "vinsert4b", CONST, vinsert4b) -BU_P9V_VSX_3 (VINSERT4B_DI, "vinsert4b_di", CONST, vinsert4b_di) BU_P9V_VSX_3 (INSERT4B, "insert4b", CONST, insert4b) BU_P9V_VSX_2 (EXTRACT4B, "extract4b", CONST, extract4b) @@ -2292,13 +2289,11 @@ BU_P9V_OVERLOAD_2 (LXVL, "lxvl") BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r") BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") -BU_P9V_OVERLOAD_2 (VEXTRACT4B, "vextract4b") BU_P9V_OVERLOAD_2 (EXTRACT4B, "extract4b") /* ISA 3.0 Vector scalar overloaded 3 argument functions */ BU_P9V_OVERLOAD_3 (STXVL, "stxvl") BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r") -BU_P9V_OVERLOAD_3 (VINSERT4B, "vinsert4b") BU_P9V_OVERLOAD_3 (INSERT4B, "insert4b") /* Overloaded CMPNE support was implemented prior to Power 9, diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 56e66db98..24675b12e 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -5429,10 +5429,6 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, - RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 }, - { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, - RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 }, { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, @@ -5500,27 +5496,6 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, - RS6000_BTI_V16QI, RS6000_BTI_V4SI, - RS6000_BTI_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, - RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_V16QI, RS6000_BTI_INTDI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI }, { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f8d8b9687..e0fda500a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15728,8 +15728,6 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) case VSX_BUILTIN_VEC_EXT_V1TI: return altivec_expand_vec_ext_builtin (exp, target); - case P9V_BUILTIN_VEXTRACT4B: - case P9V_BUILTIN_VEC_VEXTRACT4B: case P9V_BUILTIN_VEC_EXTRACT4B: arg1 = CALL_EXPR_ARG (exp, 1); STRIP_NOPS (arg1); @@ -15745,9 +15743,6 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) } break; - case P9V_BUILTIN_VINSERT4B: - case P9V_BUILTIN_VINSERT4B_DI: - case P9V_BUILTIN_VEC_VINSERT4B: case P9V_BUILTIN_VEC_INSERT4B: arg2 = CALL_EXPR_ARG (exp, 2); STRIP_NOPS (arg2); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 266923f98..19c2e6029 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5245,93 +5245,6 @@ "xxinsertw %x0,%x1,%3" [(set_attr "type" "vecperm")]) -(define_expand "vextract4b" - [(set (match_operand:DI 0 "gpc_reg_operand") - (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand") - (match_operand:QI 2 "const_0_to_12_operand")] - UNSPEC_XXEXTRACTUW))] - "TARGET_P9_VECTOR" -{ - if (!VECTOR_ELT_ORDER_BIG) - operands[2] = GEN_INT (12 - INTVAL (operands[2])); -}) - -(define_insn_and_split "*vextract4b_internal" - [(set (match_operand:DI 0 "gpc_reg_operand" "=wj,r") - (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand" "wa,v") - (match_operand:QI 2 "const_0_to_12_operand" "n,n")] - UNSPEC_XXEXTRACTUW))] - "TARGET_P9_VECTOR" - "@ - xxextractuw %x0,%x1,%2 - #" - "&& reload_completed && int_reg_operand (operands[0], DImode)" - [(const_int 0)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op0_si = gen_rtx_REG (SImode, REGNO (op0)); - rtx op1_v4si = gen_rtx_REG (V4SImode, REGNO (op1)); - - emit_move_insn (op0, op2); - if (VECTOR_ELT_ORDER_BIG) - emit_insn (gen_vextuwlx (op0_si, op0_si, op1_v4si)); - else - emit_insn (gen_vextuwrx (op0_si, op0_si, op1_v4si)); - DONE; -} - [(set_attr "type" "vecperm")]) - -(define_expand "vinsert4b" - [(set (match_operand:V16QI 0 "vsx_register_operand") - (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand") - (match_operand:V16QI 2 "vsx_register_operand") - (match_operand:QI 3 "const_0_to_12_operand")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" -{ - if (!VECTOR_ELT_ORDER_BIG) - { - rtx op1 = operands[1]; - rtx v4si_tmp = gen_reg_rtx (V4SImode); - emit_insn (gen_vsx_xxpermdi_v4si_be (v4si_tmp, op1, op1, const1_rtx)); - operands[1] = v4si_tmp; - operands[3] = GEN_INT (12 - INTVAL (operands[3])); - } -}) - -(define_insn "*vinsert4b_internal" - [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand" "wa") - (match_operand:V16QI 2 "vsx_register_operand" "0") - (match_operand:QI 3 "const_0_to_12_operand" "n")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" - "xxinsertw %x0,%x1,%3" - [(set_attr "type" "vecperm")]) - -(define_expand "vinsert4b_di" - [(set (match_operand:V16QI 0 "vsx_register_operand") - (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand") - (match_operand:V16QI 2 "vsx_register_operand") - (match_operand:QI 3 "const_0_to_12_operand")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" -{ - if (!VECTOR_ELT_ORDER_BIG) - operands[3] = GEN_INT (12 - INTVAL (operands[3])); -}) - -(define_insn "*vinsert4b_di_internal" - [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand" "wj") - (match_operand:V16QI 2 "vsx_register_operand" "0") - (match_operand:QI 3 "const_0_to_12_operand" "n")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" - "xxinsertw %x0,%x1,%3" - [(set_attr "type" "vecperm")]) ;; Generate vector extract four float 32 values from left four elements ;; of eight element vector of float 16 values. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 13dbac42e..138feb70f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -19054,21 +19054,12 @@ vector unsigned short vec_vctzh (vector unsigned short); vector int vec_vctzw (vector int); vector unsigned int vec_vctzw (vector int); -long long vec_vextract4b (const vector signed char, const int); -vector unsigned long long vec_extract4b (vector unsigned char, - const int); -long long vec_extract4b (const vector signed char, const int); -long long vec_vextract4b (const vector unsigned char, const int); +vector unsigned long long vec_extract4b (vector unsigned char, const int); vector unsigned char vec_insert4b (vector signed int, vector unsigned char, const int); vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char, const int); -vector signed char vec_insert4b (vector int, vector signed char, const int); -vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char, - const int); -vector signed char vec_insert4b (long long, vector signed char, const int); -vector unsigned char vec_insert4b (long long, vector unsigned char, const int); vector unsigned int vec_parity_lsbb (vector signed int); vector unsigned int vec_parity_lsbb (vector unsigned int); diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c b/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c deleted file mode 100644 index fa1ba7547..000000000 --- a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c +++ /dev/null @@ -1,39 +0,0 @@ -/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2" } */ - -#include - -vector signed char -vins_v4si (vector int *vi, vector signed char *vc) -{ - return vec_vinsert4b (*vi, *vc, 1); -} - -vector unsigned char -vins_di (long di, vector unsigned char *vc) -{ - return vec_vinsert4b (di, *vc, 2); -} - -vector char -vins_di2 (long *p_di, vector char *vc) -{ - return vec_vinsert4b (*p_di, *vc, 3); -} - -vector unsigned char -vins_di0 (vector unsigned char *vc) -{ - return vec_vinsert4b (0, *vc, 4); -} - -long -vext (vector signed char *vc) -{ - return vec_vextract4b (*vc, 5); -} - -/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */ -/* { dg-final { scan-assembler "xxinsertw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c b/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c deleted file mode 100644 index 3b5872ebe..000000000 --- a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2" } */ - -#include - -vector signed char -ins_v4si (vector int vi, vector signed char vc) -{ - return vec_vinsert4b (vi, vc, 13); /* { dg-error "vec_vinsert4b" } */ -} - -vector unsigned char -ins_di (long di, vector unsigned char vc, long n) -{ - return vec_vinsert4b (di, vc, n); /* { dg-error "vec_vinsert4b" } */ -} - -long -vext1 (vector signed char vc) -{ - return vec_vextract4b (vc, 13); /* { dg-error "vec_vextract4b" } */ -} - -long -vextn (vector unsigned char vc, long n) -{ - return vec_vextract4b (vc, n); /* { dg-error "vec_vextract4b" } */ -} -- 2.11.0