* [PATCH 0/5] [ARC] General fixes
@ 2018-04-06 9:00 Claudiu Zissulescu
2018-04-06 9:00 ` [PATCH 1/5] [ARC] Update sleep builtin Claudiu Zissulescu
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw)
To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess
From: claziss <claziss@synopsys.com>
Hi Andrew,
Please find a the following patches which are fixing a number of issues in ARC toolchain.
//Claudiu
[ARC] Update movhi and movdi patterns.
This patch allows st w6,[b, s9] instructions to be used.
[ARC] Cleanup sdata handling.
This cleanup is required to fix a number of lto issues.
[ARC] Clear the instruction cache using syscalls.
Required by linux like systems.
[ARC] Update sleep builtin.
Update the sleep builtin.
[ARC] Fix FLS, SETI patterns.
Likewise.
gcc/config/arc/arc-protos.h | 5 -
gcc/config/arc/arc.c | 338 ++++++++-------------------
gcc/config/arc/arc.md | 65 +++---
gcc/config/arc/constraints.md | 6 +-
gcc/config/arc/linux.h | 14 ++
gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +-
gcc/testsuite/gcc.target/arc/interrupt-8.c | 5 +-
gcc/testsuite/gcc.target/arc/loop-4.c | 2 +-
gcc/testsuite/gcc.target/arc/loop-hazard-1.c | 2 +-
gcc/testsuite/gcc.target/arc/sdata-3.c | 8 +-
gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 ++
11 files changed, 164 insertions(+), 300 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c
--
1.9.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/5] [ARC] Update sleep builtin. 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu @ 2018-04-06 9:00 ` Claudiu Zissulescu 2018-04-18 17:51 ` Andrew Burgess 2018-04-06 9:00 ` [PATCH 2/5] [ARC] Fix FLS, SETI patterns Claudiu Zissulescu ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw) To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess From: claziss <claziss@synopsys.com> gcc/ 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-protos.h (check_if_valid_sleep_operand): Remove. * config/arc/arc.c (arc_expand_builtin): Sleep accepts registers and short u6 immediate. (check_if_valid_sleep_operand): Remove. * config/arc/arc.md (Sleep): Accepts registers and u6 immediates. --- gcc/config/arc/arc-protos.h | 1 - gcc/config/arc/arc.c | 26 -------------------------- gcc/config/arc/arc.md | 4 ++-- 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 75cfeda..0ba6871 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -59,7 +59,6 @@ void arc_asm_output_aligned_decl_local (FILE *, tree, const char *, unsigned HOST_WIDE_INT); extern rtx arc_return_addr_rtx (int , rtx); extern bool check_if_valid_regno_const (rtx *, int); -extern bool check_if_valid_sleep_operand (rtx *, int); extern bool arc_legitimate_constant_p (machine_mode, rtx); extern bool arc_legitimate_pic_addr_p (rtx); extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 3564696..47d3ba4 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -6573,11 +6573,6 @@ arc_expand_builtin (tree exp, fold (arg0); op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - if (!CONST_INT_P (op0) || !satisfies_constraint_L (op0)) - { - error ("builtin operand should be an unsigned 6-bit value"); - return NULL_RTX; - } gcc_assert (icode != 0); emit_insn (GEN_FCN (icode) (op0)); return NULL_RTX; @@ -6925,27 +6920,6 @@ check_if_valid_regno_const (rtx *operands, int opno) return false; } -/* Check that after all the constant folding, whether the operand to - __builtin_arc_sleep is an unsigned int of 6 bits. If not, flag an error. */ - -bool -check_if_valid_sleep_operand (rtx *operands, int opno) -{ - switch (GET_CODE (operands[opno])) - { - case CONST : - case CONST_INT : - if( UNSIGNED_INT6 (INTVAL (operands[opno]))) - return true; - /* FALLTHRU */ - default: - fatal_error (input_location, - "operand for sleep instruction must be an unsigned 6 bit compile-time constant"); - break; - } - return false; -} - /* Return true if it is ok to make a tail-call to DECL. */ static bool diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index fb34329..2ec2b48 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -4794,9 +4794,9 @@ archs4x, archs4xd, archs4xd_slow" (define_insn "sleep" - [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] + [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")] VUNSPEC_ARC_SLEEP)] - "check_if_valid_sleep_operand(operands,0)" + "" "sleep %0" [(set_attr "length" "4") (set_attr "type" "misc")]) -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/5] [ARC] Update sleep builtin. 2018-04-06 9:00 ` [PATCH 1/5] [ARC] Update sleep builtin Claudiu Zissulescu @ 2018-04-18 17:51 ` Andrew Burgess 2018-04-23 9:57 ` Claudiu Zissulescu 0 siblings, 1 reply; 16+ messages in thread From: Andrew Burgess @ 2018-04-18 17:51 UTC (permalink / raw) To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:10 +0200]: > From: claziss <claziss@synopsys.com> > > gcc/ > 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc-protos.h (check_if_valid_sleep_operand): Remove. > * config/arc/arc.c (arc_expand_builtin): Sleep accepts registers > and short u6 immediate. > (check_if_valid_sleep_operand): Remove. > * config/arc/arc.md (Sleep): Accepts registers and u6 immediates. > --- > gcc/config/arc/arc-protos.h | 1 - > gcc/config/arc/arc.c | 26 -------------------------- > gcc/config/arc/arc.md | 4 ++-- > 3 files changed, 2 insertions(+), 29 deletions(-) Looks good. Thanks, Andrew > > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 75cfeda..0ba6871 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -59,7 +59,6 @@ void arc_asm_output_aligned_decl_local (FILE *, tree, const char *, > unsigned HOST_WIDE_INT); > extern rtx arc_return_addr_rtx (int , rtx); > extern bool check_if_valid_regno_const (rtx *, int); > -extern bool check_if_valid_sleep_operand (rtx *, int); > extern bool arc_legitimate_constant_p (machine_mode, rtx); > extern bool arc_legitimate_pic_addr_p (rtx); > extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 3564696..47d3ba4 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -6573,11 +6573,6 @@ arc_expand_builtin (tree exp, > fold (arg0); > op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); > > - if (!CONST_INT_P (op0) || !satisfies_constraint_L (op0)) > - { > - error ("builtin operand should be an unsigned 6-bit value"); > - return NULL_RTX; > - } > gcc_assert (icode != 0); > emit_insn (GEN_FCN (icode) (op0)); > return NULL_RTX; > @@ -6925,27 +6920,6 @@ check_if_valid_regno_const (rtx *operands, int opno) > return false; > } > > -/* Check that after all the constant folding, whether the operand to > - __builtin_arc_sleep is an unsigned int of 6 bits. If not, flag an error. */ > - > -bool > -check_if_valid_sleep_operand (rtx *operands, int opno) > -{ > - switch (GET_CODE (operands[opno])) > - { > - case CONST : > - case CONST_INT : > - if( UNSIGNED_INT6 (INTVAL (operands[opno]))) > - return true; > - /* FALLTHRU */ > - default: > - fatal_error (input_location, > - "operand for sleep instruction must be an unsigned 6 bit compile-time constant"); > - break; > - } > - return false; > -} > - > /* Return true if it is ok to make a tail-call to DECL. */ > > static bool > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index fb34329..2ec2b48 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -4794,9 +4794,9 @@ archs4x, archs4xd, archs4xd_slow" > > > (define_insn "sleep" > - [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] > + [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")] > VUNSPEC_ARC_SLEEP)] > - "check_if_valid_sleep_operand(operands,0)" > + "" > "sleep %0" > [(set_attr "length" "4") > (set_attr "type" "misc")]) > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 1/5] [ARC] Update sleep builtin. 2018-04-18 17:51 ` Andrew Burgess @ 2018-04-23 9:57 ` Claudiu Zissulescu 0 siblings, 0 replies; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-23 9:57 UTC (permalink / raw) To: Andrew Burgess; +Cc: gcc-patches, Francois.Bedard Committed. Thank you for your review, Claudiu ________________________________________ From: Andrew Burgess [andrew.burgess@embecosm.com] Sent: Wednesday, April 18, 2018 7:51 PM To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com Subject: Re: [PATCH 1/5] [ARC] Update sleep builtin. * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:10 +0200]: > From: claziss <claziss@synopsys.com> > > gcc/ > 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc-protos.h (check_if_valid_sleep_operand): Remove. > * config/arc/arc.c (arc_expand_builtin): Sleep accepts registers > and short u6 immediate. > (check_if_valid_sleep_operand): Remove. > * config/arc/arc.md (Sleep): Accepts registers and u6 immediates. > --- > gcc/config/arc/arc-protos.h | 1 - > gcc/config/arc/arc.c | 26 -------------------------- > gcc/config/arc/arc.md | 4 ++-- > 3 files changed, 2 insertions(+), 29 deletions(-) Looks good. Thanks, Andrew > > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 75cfeda..0ba6871 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -59,7 +59,6 @@ void arc_asm_output_aligned_decl_local (FILE *, tree, const char *, > unsigned HOST_WIDE_INT); > extern rtx arc_return_addr_rtx (int , rtx); > extern bool check_if_valid_regno_const (rtx *, int); > -extern bool check_if_valid_sleep_operand (rtx *, int); > extern bool arc_legitimate_constant_p (machine_mode, rtx); > extern bool arc_legitimate_pic_addr_p (rtx); > extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 3564696..47d3ba4 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -6573,11 +6573,6 @@ arc_expand_builtin (tree exp, > fold (arg0); > op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); > > - if (!CONST_INT_P (op0) || !satisfies_constraint_L (op0)) > - { > - error ("builtin operand should be an unsigned 6-bit value"); > - return NULL_RTX; > - } > gcc_assert (icode != 0); > emit_insn (GEN_FCN (icode) (op0)); > return NULL_RTX; > @@ -6925,27 +6920,6 @@ check_if_valid_regno_const (rtx *operands, int opno) > return false; > } > > -/* Check that after all the constant folding, whether the operand to > - __builtin_arc_sleep is an unsigned int of 6 bits. If not, flag an error. */ > - > -bool > -check_if_valid_sleep_operand (rtx *operands, int opno) > -{ > - switch (GET_CODE (operands[opno])) > - { > - case CONST : > - case CONST_INT : > - if( UNSIGNED_INT6 (INTVAL (operands[opno]))) > - return true; > - /* FALLTHRU */ > - default: > - fatal_error (input_location, > - "operand for sleep instruction must be an unsigned 6 bit compile-time constant"); > - break; > - } > - return false; > -} > - > /* Return true if it is ok to make a tail-call to DECL. */ > > static bool > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index fb34329..2ec2b48 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -4794,9 +4794,9 @@ archs4x, archs4xd, archs4xd_slow" > > > (define_insn "sleep" > - [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] > + [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")] > VUNSPEC_ARC_SLEEP)] > - "check_if_valid_sleep_operand(operands,0)" > + "" > "sleep %0" > [(set_attr "length" "4") > (set_attr "type" "misc")]) > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/5] [ARC] Fix FLS, SETI patterns. 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 1/5] [ARC] Update sleep builtin Claudiu Zissulescu @ 2018-04-06 9:00 ` Claudiu Zissulescu 2018-04-18 17:57 ` Andrew Burgess 2018-04-06 9:00 ` [PATCH 4/5] [ARC] Cleanup sdata handling Claudiu Zissulescu ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw) To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess From: claziss <claziss@synopsys.com> Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md ("vunspec"): Delete it, unify all the unspec enums into a single definition. (fls): Fix predicates and printing. (seti): Likewise. --- gcc/config/arc/arc.md | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 2ec2b48..ffd9d5b 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -137,9 +137,7 @@ UNSPEC_ARC_VMPY2H UNSPEC_ARC_VMPY2HU UNSPEC_ARC_STKTIE - ]) -(define_c_enum "vunspec" [ VUNSPEC_ARC_RTIE VUNSPEC_ARC_SYNC VUNSPEC_ARC_BRK @@ -5818,21 +5816,19 @@ archs4x, archs4xd, archs4xd_slow" }) (define_insn "fls" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") - (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")] UNSPEC_ARC_FLS))] "TARGET_NORM && TARGET_V2" - "@ - fls \t%0, %1 - fls \t%0, %1" + "fls\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) (define_insn "seti" - [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] + [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")] VUNSPEC_ARC_SETI)] "TARGET_V2" - "seti %0" + "seti\\t%0" [(set_attr "length" "4") (set_attr "type" "misc")]) -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/5] [ARC] Fix FLS, SETI patterns. 2018-04-06 9:00 ` [PATCH 2/5] [ARC] Fix FLS, SETI patterns Claudiu Zissulescu @ 2018-04-18 17:57 ` Andrew Burgess 2018-04-23 10:34 ` Claudiu Zissulescu 0 siblings, 1 reply; 16+ messages in thread From: Andrew Burgess @ 2018-04-18 17:57 UTC (permalink / raw) To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:11 +0200]: > From: claziss <claziss@synopsys.com> > > Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.md ("vunspec"): Delete it, unify all the unspec > enums into a single definition. > (fls): Fix predicates and printing. > (seti): Likewise. Looks good, Thanks, Andrew > --- > gcc/config/arc/arc.md | 14 +++++--------- > 1 file changed, 5 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 2ec2b48..ffd9d5b 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -137,9 +137,7 @@ > UNSPEC_ARC_VMPY2H > UNSPEC_ARC_VMPY2HU > UNSPEC_ARC_STKTIE > - ]) > > -(define_c_enum "vunspec" [ > VUNSPEC_ARC_RTIE > VUNSPEC_ARC_SYNC > VUNSPEC_ARC_BRK > @@ -5818,21 +5816,19 @@ archs4x, archs4xd, archs4xd_slow" > }) > > (define_insn "fls" > - [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") > - (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] > + [(set (match_operand:SI 0 "register_operand" "=r,r") > + (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")] > UNSPEC_ARC_FLS))] > "TARGET_NORM && TARGET_V2" > - "@ > - fls \t%0, %1 > - fls \t%0, %1" > + "fls\\t%0,%1" > [(set_attr "length" "4,8") > (set_attr "type" "two_cycle_core,two_cycle_core")]) > > (define_insn "seti" > - [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] > + [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")] > VUNSPEC_ARC_SETI)] > "TARGET_V2" > - "seti %0" > + "seti\\t%0" > [(set_attr "length" "4") > (set_attr "type" "misc")]) > > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 2/5] [ARC] Fix FLS, SETI patterns. 2018-04-18 17:57 ` Andrew Burgess @ 2018-04-23 10:34 ` Claudiu Zissulescu 0 siblings, 0 replies; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-23 10:34 UTC (permalink / raw) To: Andrew Burgess; +Cc: gcc-patches, Francois.Bedard Committed. Thank you for your review, Claudiu ________________________________________ From: Andrew Burgess [andrew.burgess@embecosm.com] Sent: Wednesday, April 18, 2018 7:57 PM To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com Subject: Re: [PATCH 2/5] [ARC] Fix FLS, SETI patterns. * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:11 +0200]: > From: claziss <claziss@synopsys.com> > > Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.md ("vunspec"): Delete it, unify all the unspec > enums into a single definition. > (fls): Fix predicates and printing. > (seti): Likewise. Looks good, Thanks, Andrew > --- > gcc/config/arc/arc.md | 14 +++++--------- > 1 file changed, 5 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 2ec2b48..ffd9d5b 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -137,9 +137,7 @@ > UNSPEC_ARC_VMPY2H > UNSPEC_ARC_VMPY2HU > UNSPEC_ARC_STKTIE > - ]) > > -(define_c_enum "vunspec" [ > VUNSPEC_ARC_RTIE > VUNSPEC_ARC_SYNC > VUNSPEC_ARC_BRK > @@ -5818,21 +5816,19 @@ archs4x, archs4xd, archs4xd_slow" > }) > > (define_insn "fls" > - [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") > - (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] > + [(set (match_operand:SI 0 "register_operand" "=r,r") > + (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")] > UNSPEC_ARC_FLS))] > "TARGET_NORM && TARGET_V2" > - "@ > - fls \t%0, %1 > - fls \t%0, %1" > + "fls\\t%0,%1" > [(set_attr "length" "4,8") > (set_attr "type" "two_cycle_core,two_cycle_core")]) > > (define_insn "seti" > - [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] > + [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")] > VUNSPEC_ARC_SETI)] > "TARGET_V2" > - "seti %0" > + "seti\\t%0" > [(set_attr "length" "4") > (set_attr "type" "misc")]) > > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/5] [ARC] Cleanup sdata handling. 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 1/5] [ARC] Update sleep builtin Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 2/5] [ARC] Fix FLS, SETI patterns Claudiu Zissulescu @ 2018-04-06 9:00 ` Claudiu Zissulescu 2018-04-27 21:40 ` Andrew Burgess 2018-04-06 9:00 ` [PATCH 3/5] [ARC] Update movhi and movdi patterns Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 5/5] [ARC] Clear the instruction cache using syscalls Claudiu Zissulescu 4 siblings, 1 reply; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw) To: gcc-patches Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess, Claudiu Zissulescu From: Claudiu Zissulescu <claziss@gmail.com> Clean up how we handle small data load/store operations. This patch clears -flto-fat-lto-object LTO related errors. gcc/ 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-protos.h (prepare_extend_operands): Remove. (small_data_pattern): Likewise. (arc_rewrite_small_data): Likewise. * config/arc/arc.c (LEGITIMATE_SMALL_DATA_OFFSET_P): Remove. (LEGITIMATE_SMALL_DATA_ADDRESS_P): Likewise. (get_symbol_alignment): New function. (legitimate_small_data_address_p): Likewise. (legitimate_scaled_address): Update, call legitimate_small_data_address_p. (output_sdata): New static variable. (arc_print_operand): Update how we handle small data operands. (arc_print_operand_address): Likewise. (arc_legitimate_address_p): Update, use legitimate_small_data_address_p. (arc_rewrite_small_data_p): Remove. (arc_rewrite_small_data_1): Likewise. (arc_rewrite_small_data): Likewise. (small_data_pattern): Likewise. (compact_sda_memory_operand): Update to use legitimate_small_data_address_p and get_symbol_alignment. (prepare_move_operands): Don't rewite sdata pattern. (prepare_extend_operands): Remove. * config/arc/arc.md (zero_extendqihi2): Don't rewrite sdata pattern. (zero_extendqisi2): Likewise. (zero_extendhisi2): Likewise. (extendqihi2): Likewise. (extendqisi2): Likewise. (extendhisi2): Likewise. (addsi3): Likewise. (subsi3): Likewise. (andsi3): Likewise. * config/arc/constraints.md (Usd): Change it to memory constraint. gcc/testsuite 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/interrupt-8.c: Update test. * gcc.target/arc/loop-4.c: Likewise. * gcc.target/arc/loop-hazard-1.c: Likewise. * gcc.target/arc/sdata-3.c: Likewise. --- gcc/config/arc/arc-protos.h | 4 - gcc/config/arc/arc.c | 309 ++++++++------------------- gcc/config/arc/arc.md | 22 +- gcc/config/arc/constraints.md | 6 +- gcc/testsuite/gcc.target/arc/interrupt-8.c | 5 +- gcc/testsuite/gcc.target/arc/loop-4.c | 2 +- gcc/testsuite/gcc.target/arc/loop-hazard-1.c | 2 +- gcc/testsuite/gcc.target/arc/sdata-3.c | 8 +- 8 files changed, 110 insertions(+), 248 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 0ba6871..67f3b4e 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -33,8 +33,6 @@ extern void arc_print_operand (FILE *, rtx, int); extern void arc_print_operand_address (FILE *, rtx); extern void arc_final_prescan_insn (rtx_insn *, rtx *, int); extern const char *arc_output_libcall (const char *); -extern bool prepare_extend_operands (rtx *operands, enum rtx_code code, - machine_mode omode); extern int arc_output_addsi (rtx *operands, bool, bool); extern int arc_output_commutative_cond_exec (rtx *operands, bool); extern bool arc_expand_movmem (rtx *operands); @@ -65,8 +63,6 @@ extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); extern bool arc_is_longcall_p (rtx); extern bool arc_is_shortcall_p (rtx); extern bool valid_brcc_with_delay_p (rtx *); -extern bool small_data_pattern (rtx , machine_mode); -extern rtx arc_rewrite_small_data (rtx); extern bool arc_ccfsm_cond_exec_p (void); struct secondary_reload_info; extern int arc_register_move_cost (machine_mode, enum reg_class, diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 2ccdce8..2ce1744 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -96,22 +96,6 @@ HARD_REG_SET overrideregs; ? 0 \ : -(-GET_MODE_SIZE (MODE) | -4) >> 1))) -#define LEGITIMATE_SMALL_DATA_OFFSET_P(X) \ - (GET_CODE (X) == CONST \ - && GET_CODE (XEXP ((X), 0)) == PLUS \ - && GET_CODE (XEXP (XEXP ((X), 0), 0)) == SYMBOL_REF \ - && SYMBOL_REF_SMALL_P (XEXP (XEXP ((X), 0), 0)) \ - && GET_CODE (XEXP(XEXP ((X), 0), 1)) == CONST_INT \ - && INTVAL (XEXP (XEXP ((X), 0), 1)) <= g_switch_value) - -#define LEGITIMATE_SMALL_DATA_ADDRESS_P(X) \ - (GET_CODE (X) == PLUS \ - && REG_P (XEXP ((X), 0)) \ - && REGNO (XEXP ((X), 0)) == SDATA_BASE_REGNUM \ - && ((GET_CODE (XEXP ((X), 1)) == SYMBOL_REF \ - && SYMBOL_REF_SMALL_P (XEXP ((X), 1))) \ - || LEGITIMATE_SMALL_DATA_OFFSET_P (XEXP ((X), 1)))) - /* Array of valid operand punctuation characters. */ char arc_punct_chars[256]; @@ -308,6 +292,60 @@ static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT, /* Globally visible information about currently selected cpu. */ const arc_cpu_t *arc_selected_cpu; +/* Given a symbol RTX (const (symb <+ const_int>), returns its + alignment. */ + +static int +get_symbol_alignment (rtx x) +{ + tree decl = NULL_TREE; + int align = 0; + + switch (GET_CODE (x)) + { + case SYMBOL_REF: + decl = SYMBOL_REF_DECL (x); + break; + case CONST: + return get_symbol_alignment (XEXP (x, 0)); + case PLUS: + gcc_assert (CONST_INT_P (XEXP (x, 1))); + return get_symbol_alignment (XEXP (x, 0)); + default: + return 0; + } + + if (decl) + align = DECL_ALIGN (decl); + align = align / BITS_PER_UNIT; + return align; +} + +/* Return true if x is ok to be used as a small data address. */ + +static bool +legitimate_small_data_address_p (rtx x) +{ + switch (GET_CODE (x)) + { + case CONST: + return legitimate_small_data_address_p (XEXP (x, 0)); + case SYMBOL_REF: + return SYMBOL_REF_SMALL_P (x); + case PLUS: + { + bool p0 = (GET_CODE (XEXP (x, 0)) == SYMBOL_REF) + && SYMBOL_REF_SMALL_P (XEXP (x, 0)); + bool p1 = CONST_INT_P (XEXP (x, 1)) + && (INTVAL (XEXP (x, 1)) <= g_switch_value); + return p0 && p1; + } + default: + return false; + } +} + +/* TRUE if op is an scaled address. */ static bool legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) { @@ -352,14 +390,13 @@ legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) return true; return false; } + + /* Scalled addresses for sdata is done other places. */ + if (legitimate_small_data_address_p (op)) + return false; + if (CONSTANT_P (XEXP (op, 1))) - { - /* Scalled addresses for sdata is done other places. */ - if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF - && SYMBOL_REF_SMALL_P (XEXP (op, 1))) - return false; return true; - } return false; } @@ -3780,6 +3817,9 @@ arc_add_jli_section (rtx pat) reset when we output the scaled address. */ static int output_scaled = 0; +/* Set when we force sdata output. */ +static int output_sdata = 0; + /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ @@ -4132,24 +4172,24 @@ arc_print_operand (FILE *file, rtx x, int code) fputs (".as", file); output_scaled = 1; } - else if (LEGITIMATE_SMALL_DATA_ADDRESS_P (addr) - && GET_MODE_SIZE (GET_MODE (x)) > 1) + break; + case SYMBOL_REF: + case CONST: + if (legitimate_small_data_address_p (addr) + && GET_MODE_SIZE (GET_MODE (x)) > 1) { - tree decl = NULL_TREE; - int align = 0; - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) - == SYMBOL_REF) - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); - if (decl) - align = DECL_ALIGN (decl); - align = align / BITS_PER_UNIT; - if ((GET_MODE_SIZE (GET_MODE (x)) == 2) - && align && ((align & 1) == 0)) - fputs (".as", file); - if ((GET_MODE_SIZE (GET_MODE (x)) >= 4) - && align && ((align & 3) == 0)) + int align = get_symbol_alignment (addr); + int mask = 0; + switch (GET_MODE (x)) + { + case E_HImode: + mask = 1; + break; + default: + mask = 3; + break; + } + if (align && ((align & mask) == 0)) fputs (".as", file); } break; @@ -4268,6 +4308,9 @@ arc_print_operand (FILE *file, rtx x, int code) rtx addr = XEXP (x, 0); int size = GET_MODE_SIZE (GET_MODE (x)); + if (legitimate_small_data_address_p (addr)) + output_sdata = 1; + fputc ('[', file); switch (GET_CODE (addr)) @@ -4328,26 +4371,7 @@ arc_print_operand (FILE *file, rtx x, int code) || XINT (XEXP (XEXP (x, 0), 0), 1) == UNSPEC_TLS_GD))) arc_output_pic_addr_const (file, x, code); else - { - /* FIXME: Dirty way to handle @var@sda+const. Shd be handled - with asm_output_symbol_ref */ - if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) - { - x = XEXP (x, 0); - output_addr_const (file, XEXP (x, 0)); - if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF && SYMBOL_REF_SMALL_P (XEXP (x, 0))) - fprintf (file, "@sda"); - - if (GET_CODE (XEXP (x, 1)) != CONST_INT - || INTVAL (XEXP (x, 1)) >= 0) - fprintf (file, "+"); - output_addr_const (file, XEXP (x, 1)); - } - else - output_addr_const (file, x); - } - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) - fprintf (file, "@sda"); + output_addr_const (file, x); break; } } @@ -4364,10 +4388,13 @@ arc_print_operand_address (FILE *file , rtx addr) case REG : fputs (reg_names[REGNO (addr)], file); break; - case SYMBOL_REF : + case SYMBOL_REF: + if (output_sdata) + fputs ("gp,", file); output_addr_const (file, addr); - if (SYMBOL_REF_SMALL_P (addr)) - fprintf (file, "@sda"); + if (output_sdata) + fputs ("@sda", file); + output_sdata = 0; break; case PLUS : if (GET_CODE (XEXP (addr, 0)) == MULT) @@ -6188,7 +6215,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict) return true; if (legitimate_scaled_address_p (mode, x, strict)) return true; - if (LEGITIMATE_SMALL_DATA_ADDRESS_P (x)) + if (legitimate_small_data_address_p (x)) return true; if (GET_CODE (x) == CONST_INT && LARGE_INT (INTVAL (x))) return true; @@ -7991,98 +8018,9 @@ arc_in_small_data_p (const_tree decl) return false; } -/* Return true if X is a small data address that can be rewritten - as a gp+symref. */ - -static bool -arc_rewrite_small_data_p (const_rtx x) -{ - if (GET_CODE (x) == CONST) - x = XEXP (x, 0); - - if (GET_CODE (x) == PLUS) - { - if (GET_CODE (XEXP (x, 1)) == CONST_INT) - x = XEXP (x, 0); - } - - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) - { - gcc_assert (SYMBOL_REF_TLS_MODEL (x) == 0); - return true; - } - return false; -} - -/* If possible, rewrite OP so that it refers to small data using - explicit relocations. */ - -static rtx -arc_rewrite_small_data_1 (rtx op) -{ - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); - op = copy_insn (op); - subrtx_ptr_iterator::array_type array; - FOR_EACH_SUBRTX_PTR (iter, array, &op, ALL) - { - rtx *loc = *iter; - if (arc_rewrite_small_data_p (*loc)) - { - *loc = gen_rtx_PLUS (Pmode, rgp, *loc); - iter.skip_subrtxes (); - } - else if (GET_CODE (*loc) == PLUS - && rtx_equal_p (XEXP (*loc, 0), rgp)) - iter.skip_subrtxes (); - } - return op; -} - -rtx -arc_rewrite_small_data (rtx op) -{ - op = arc_rewrite_small_data_1 (op); - - /* Check if we fit small data constraints. */ - if (MEM_P (op) - && !LEGITIMATE_SMALL_DATA_ADDRESS_P (XEXP (op, 0))) - { - rtx addr = XEXP (op, 0); - rtx tmp = gen_reg_rtx (Pmode); - emit_move_insn (tmp, addr); - op = replace_equiv_address_nv (op, tmp); - } - return op; -} - -/* Return true if OP refers to small data symbols directly, not through - a PLUS. */ - -bool -small_data_pattern (rtx op, machine_mode) -{ - if (GET_CODE (op) == SEQUENCE) - return false; - - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); - subrtx_iterator::array_type array; - FOR_EACH_SUBRTX (iter, array, op, ALL) - { - const_rtx x = *iter; - if (GET_CODE (x) == PLUS - && rtx_equal_p (XEXP (x, 0), rgp)) - iter.skip_subrtxes (); - else if (arc_rewrite_small_data_p (x)) - return true; - } - return false; -} - /* Return true if OP is an acceptable memory operand for ARCompact 16-bit gp-relative load instructions. - op shd look like : [r26, symref@sda] - i.e. (mem (plus (reg 26) (symref with smalldata flag set)) - */ +*/ /* volatile cache option still to be handled. */ bool @@ -8090,7 +8028,6 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) { rtx addr; int size; - tree decl = NULL_TREE; int align = 0; int mask = 0; @@ -8110,7 +8047,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) /* Decode the address now. */ addr = XEXP (op, 0); - if (!LEGITIMATE_SMALL_DATA_ADDRESS_P (addr)) + if (!legitimate_small_data_address_p (addr)) return false; if (!short_p || size == 1) @@ -8118,14 +8055,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) /* Now check for the alignment, the short loads using gp require the addresses to be aligned. */ - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) == SYMBOL_REF) - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); - if (decl) - align = DECL_ALIGN (decl); - align = align / BITS_PER_UNIT; - + align = get_symbol_alignment (addr); switch (mode) { case E_HImode: @@ -8599,11 +8529,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) } } - /* We used to do this only for MODE_INT Modes, but addresses to floating - point variables may well be in the small data section. */ - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[0], Pmode)) - operands[0] = arc_rewrite_small_data (operands[0]); - if (mode == SImode && SYMBOLIC_CONST (operands[1])) { prepare_pic_move (operands, SImode); @@ -8613,29 +8538,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) here and references the variable directly. */ } - if (GET_CODE (operands[0]) != MEM - && !TARGET_NO_SDATA_SET - && small_data_pattern (operands[1], Pmode)) - { - /* This is to take care of address calculations involving sdata - variables. */ - operands[1] = arc_rewrite_small_data (operands[1]); - - emit_insn (gen_rtx_SET (operands[0],operands[1])); - /* ??? This note is useless, since it only restates the set itself. - We should rather use the original SYMBOL_REF. However, there is - the problem that we are lying to the compiler about these - SYMBOL_REFs to start with. symbol@sda should be encoded specially - so that we can tell it apart from an actual symbol. */ - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); - - /* Take care of the REG_EQUAL note that will be attached to mark the - output reg equal to the initial symbol_ref after this code is - executed. */ - emit_move_insn (operands[0], operands[0]); - return true; - } - if (MEM_P (operands[0]) && !(reload_in_progress || reload_completed)) { @@ -8679,31 +8581,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) return false; } -/* Prepare OPERANDS for an extension using CODE to OMODE. - Return true iff the move has been emitted. */ - -bool -prepare_extend_operands (rtx *operands, enum rtx_code code, - machine_mode omode) -{ - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) - { - /* This is to take care of address calculations involving sdata - variables. */ - operands[1] - = gen_rtx_fmt_e (code, omode, arc_rewrite_small_data (operands[1])); - emit_insn (gen_rtx_SET (operands[0], operands[1])); - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); - - /* Take care of the REG_EQUAL note that will be attached to mark the - output reg equal to the initial extension after this code is - executed. */ - emit_move_insn (operands[0], operands[0]); - return true; - } - return false; -} - /* Output a library call to a function called FNAME that has been arranged to be local to any dso. */ diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 0fc7aba..5610bab 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1771,7 +1771,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:HI 0 "dest_reg_operand" "") (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, HImode)) DONE;" + "" ) (define_insn "*zero_extendqisi2_ac" @@ -1795,7 +1795,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:SI 0 "dest_reg_operand" "") (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" + "" ) (define_insn "*zero_extendhisi2_i" @@ -1820,7 +1820,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:SI 0 "dest_reg_operand" "") (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" + "" ) ;; Sign extension instructions. @@ -1843,7 +1843,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:HI 0 "dest_reg_operand" "") (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, HImode)) DONE;" + "" ) (define_insn "*extendqisi2_ac" @@ -1863,7 +1863,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:SI 0 "dest_reg_operand" "") (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" + "" ) (define_insn "*extendhisi2_i" @@ -1884,7 +1884,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:SI 0 "dest_reg_operand" "") (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" + "" ) ;; Unary arithmetic insns @@ -2777,11 +2777,6 @@ archs4x, archs4xd, archs4xd_slow" { operands[2]=force_reg(SImode, operands[2]); } - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[2], Pmode)) - { - operands[2] = force_reg (SImode, arc_rewrite_small_data (operands[2])); - } - ") (define_expand "adddi3" @@ -2985,8 +2980,6 @@ archs4x, archs4xd, archs4xd_slow" } if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false)) operands[c] = force_reg (SImode, operands[c]); - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[c], Pmode)) - operands[c] = force_reg (SImode, arc_rewrite_small_data (operands[c])); }") ; the casesi expander might generate a sub of zero, so we have to recognize it. @@ -3342,8 +3335,7 @@ archs4x, archs4xd, archs4xd_slow" "" "if (!satisfies_constraint_Cux (operands[2])) operands[1] = force_reg (SImode, operands[1]); - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) - operands[1] = arc_rewrite_small_data (operands[1]);") + ") (define_insn "andsi3_i" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W") diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 7249107..90c736e 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -347,11 +347,7 @@ (match_test "!cmem_address (XEXP (op, 0), SImode)") (not (match_operand 0 "long_immediate_loadstore_operand")))) -; Don't use define_memory_constraint here as the relocation patching -; for small data symbols only works within a ld/st instruction and -; define_memory_constraint may result in the address being calculated -; into a register first. -(define_constraint "Usd" +(define_memory_constraint "Usd" "@internal A valid _small-data_ memory operand for ARCompact instructions" (and (match_code "mem") diff --git a/gcc/testsuite/gcc.target/arc/interrupt-8.c b/gcc/testsuite/gcc.target/arc/interrupt-8.c index 60fd87b..f2cc4c4 100644 --- a/gcc/testsuite/gcc.target/arc/interrupt-8.c +++ b/gcc/testsuite/gcc.target/arc/interrupt-8.c @@ -2,8 +2,7 @@ /* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */ /* { dg-options "-O2 -mirq-ctrl-saved=r0-r17" } */ -/* Check if the registers R0-R17 are automatically saved. GP is saved - by the compiler. */ +/* Check if the registers R0-R17 are automatically saved. */ int a; @@ -18,8 +17,6 @@ foo(void) /* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */ /* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */ /* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */ -/* { dg-final { scan-assembler "st.*gp,\\\[sp,-4\\\]" } } */ -/* { dg-final { scan-assembler "ld.*gp,\\\[sp\\\]" } } */ /* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */ /* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */ /* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/loop-4.c b/gcc/testsuite/gcc.target/arc/loop-4.c index 99a93a7..dbe5d3f 100644 --- a/gcc/testsuite/gcc.target/arc/loop-4.c +++ b/gcc/testsuite/gcc.target/arc/loop-4.c @@ -1,6 +1,6 @@ /* { dg-do assemble } */ /* { dg-do compile } */ -/* { dg-options "-Os" } */ +/* { dg-options "-Os -fbranch-count-reg" } */ void fn1(void *p1, int p2, int p3) diff --git a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c index 7c688bb..83d5fd7 100644 --- a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c +++ b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-Os" } */ +/* { dg-options "-Os -fbranch-count-reg" } */ /* This caused an assertion within arc_loop_hazard. */ diff --git a/gcc/testsuite/gcc.target/arc/sdata-3.c b/gcc/testsuite/gcc.target/arc/sdata-3.c index cdf3b6d..4df7074 100644 --- a/gcc/testsuite/gcc.target/arc/sdata-3.c +++ b/gcc/testsuite/gcc.target/arc/sdata-3.c @@ -10,9 +10,13 @@ short g_c; char g_d; #define TEST(name, optype) \ - void test_ ## name (optype x) \ + optype testLD_ ## name (optype x) \ { \ - g_ ## name += x; \ + return g_ ## name + x; \ + } \ + void testST_ ## name (optype x) \ + { \ + g_ ## name = x; \ } TEST (a, int) -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/5] [ARC] Cleanup sdata handling. 2018-04-06 9:00 ` [PATCH 4/5] [ARC] Cleanup sdata handling Claudiu Zissulescu @ 2018-04-27 21:40 ` Andrew Burgess 2018-04-30 13:18 ` Claudiu Zissulescu 0 siblings, 1 reply; 16+ messages in thread From: Andrew Burgess @ 2018-04-27 21:40 UTC (permalink / raw) To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard, Claudiu Zissulescu * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:13 +0200]: > From: Claudiu Zissulescu <claziss@gmail.com> > > Clean up how we handle small data load/store operations. This patch clears -flto-fat-lto-object LTO related errors. > > gcc/ > 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc-protos.h (prepare_extend_operands): Remove. > (small_data_pattern): Likewise. > (arc_rewrite_small_data): Likewise. > * config/arc/arc.c (LEGITIMATE_SMALL_DATA_OFFSET_P): Remove. > (LEGITIMATE_SMALL_DATA_ADDRESS_P): Likewise. > (get_symbol_alignment): New function. > (legitimate_small_data_address_p): Likewise. > (legitimate_scaled_address): Update, call > legitimate_small_data_address_p. > (output_sdata): New static variable. > (arc_print_operand): Update how we handle small data operands. > (arc_print_operand_address): Likewise. > (arc_legitimate_address_p): Update, use > legitimate_small_data_address_p. > (arc_rewrite_small_data_p): Remove. > (arc_rewrite_small_data_1): Likewise. > (arc_rewrite_small_data): Likewise. > (small_data_pattern): Likewise. > (compact_sda_memory_operand): Update to use > legitimate_small_data_address_p and get_symbol_alignment. > (prepare_move_operands): Don't rewite sdata pattern. > (prepare_extend_operands): Remove. > * config/arc/arc.md (zero_extendqihi2): Don't rewrite sdata > pattern. > (zero_extendqisi2): Likewise. > (zero_extendhisi2): Likewise. > (extendqihi2): Likewise. > (extendqisi2): Likewise. > (extendhisi2): Likewise. > (addsi3): Likewise. > (subsi3): Likewise. > (andsi3): Likewise. > * config/arc/constraints.md (Usd): Change it to memory constraint. > > gcc/testsuite > 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> > > * gcc.target/arc/interrupt-8.c: Update test. > * gcc.target/arc/loop-4.c: Likewise. > * gcc.target/arc/loop-hazard-1.c: Likewise. > * gcc.target/arc/sdata-3.c: Likewise. Looks like a good clean up. Thanks, Andrew > --- > gcc/config/arc/arc-protos.h | 4 - > gcc/config/arc/arc.c | 309 ++++++++------------------- > gcc/config/arc/arc.md | 22 +- > gcc/config/arc/constraints.md | 6 +- > gcc/testsuite/gcc.target/arc/interrupt-8.c | 5 +- > gcc/testsuite/gcc.target/arc/loop-4.c | 2 +- > gcc/testsuite/gcc.target/arc/loop-hazard-1.c | 2 +- > gcc/testsuite/gcc.target/arc/sdata-3.c | 8 +- > 8 files changed, 110 insertions(+), 248 deletions(-) > > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 0ba6871..67f3b4e 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -33,8 +33,6 @@ extern void arc_print_operand (FILE *, rtx, int); > extern void arc_print_operand_address (FILE *, rtx); > extern void arc_final_prescan_insn (rtx_insn *, rtx *, int); > extern const char *arc_output_libcall (const char *); > -extern bool prepare_extend_operands (rtx *operands, enum rtx_code code, > - machine_mode omode); > extern int arc_output_addsi (rtx *operands, bool, bool); > extern int arc_output_commutative_cond_exec (rtx *operands, bool); > extern bool arc_expand_movmem (rtx *operands); > @@ -65,8 +63,6 @@ extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); > extern bool arc_is_longcall_p (rtx); > extern bool arc_is_shortcall_p (rtx); > extern bool valid_brcc_with_delay_p (rtx *); > -extern bool small_data_pattern (rtx , machine_mode); > -extern rtx arc_rewrite_small_data (rtx); > extern bool arc_ccfsm_cond_exec_p (void); > struct secondary_reload_info; > extern int arc_register_move_cost (machine_mode, enum reg_class, > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 2ccdce8..2ce1744 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -96,22 +96,6 @@ HARD_REG_SET overrideregs; > ? 0 \ > : -(-GET_MODE_SIZE (MODE) | -4) >> 1))) > > -#define LEGITIMATE_SMALL_DATA_OFFSET_P(X) \ > - (GET_CODE (X) == CONST \ > - && GET_CODE (XEXP ((X), 0)) == PLUS \ > - && GET_CODE (XEXP (XEXP ((X), 0), 0)) == SYMBOL_REF \ > - && SYMBOL_REF_SMALL_P (XEXP (XEXP ((X), 0), 0)) \ > - && GET_CODE (XEXP(XEXP ((X), 0), 1)) == CONST_INT \ > - && INTVAL (XEXP (XEXP ((X), 0), 1)) <= g_switch_value) > - > -#define LEGITIMATE_SMALL_DATA_ADDRESS_P(X) \ > - (GET_CODE (X) == PLUS \ > - && REG_P (XEXP ((X), 0)) \ > - && REGNO (XEXP ((X), 0)) == SDATA_BASE_REGNUM \ > - && ((GET_CODE (XEXP ((X), 1)) == SYMBOL_REF \ > - && SYMBOL_REF_SMALL_P (XEXP ((X), 1))) \ > - || LEGITIMATE_SMALL_DATA_OFFSET_P (XEXP ((X), 1)))) > - > /* Array of valid operand punctuation characters. */ > char arc_punct_chars[256]; > > @@ -308,6 +292,60 @@ static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT, > /* Globally visible information about currently selected cpu. */ > const arc_cpu_t *arc_selected_cpu; > > +/* Given a symbol RTX (const (symb <+ const_int>), returns its > + alignment. */ > + > +static int > +get_symbol_alignment (rtx x) > +{ > + tree decl = NULL_TREE; > + int align = 0; > + > + switch (GET_CODE (x)) > + { > + case SYMBOL_REF: > + decl = SYMBOL_REF_DECL (x); > + break; > + case CONST: > + return get_symbol_alignment (XEXP (x, 0)); > + case PLUS: > + gcc_assert (CONST_INT_P (XEXP (x, 1))); > + return get_symbol_alignment (XEXP (x, 0)); > + default: > + return 0; > + } > + > + if (decl) > + align = DECL_ALIGN (decl); > + align = align / BITS_PER_UNIT; > + return align; > +} > + > +/* Return true if x is ok to be used as a small data address. */ > + > +static bool > +legitimate_small_data_address_p (rtx x) > +{ > + switch (GET_CODE (x)) > + { > + case CONST: > + return legitimate_small_data_address_p (XEXP (x, 0)); > + case SYMBOL_REF: > + return SYMBOL_REF_SMALL_P (x); > + case PLUS: > + { > + bool p0 = (GET_CODE (XEXP (x, 0)) == SYMBOL_REF) > + && SYMBOL_REF_SMALL_P (XEXP (x, 0)); > + bool p1 = CONST_INT_P (XEXP (x, 1)) > + && (INTVAL (XEXP (x, 1)) <= g_switch_value); > + return p0 && p1; > + } > + default: > + return false; > + } > +} > + > +/* TRUE if op is an scaled address. */ > static bool > legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) > { > @@ -352,14 +390,13 @@ legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) > return true; > return false; > } > + > + /* Scalled addresses for sdata is done other places. */ > + if (legitimate_small_data_address_p (op)) > + return false; > + > if (CONSTANT_P (XEXP (op, 1))) > - { > - /* Scalled addresses for sdata is done other places. */ > - if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF > - && SYMBOL_REF_SMALL_P (XEXP (op, 1))) > - return false; > return true; > - } > > return false; > } > @@ -3780,6 +3817,9 @@ arc_add_jli_section (rtx pat) > reset when we output the scaled address. */ > static int output_scaled = 0; > > +/* Set when we force sdata output. */ > +static int output_sdata = 0; > + > /* Print operand X (an rtx) in assembler syntax to file FILE. > CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. > For `%' followed by punctuation, CODE is the punctuation and X is null. */ > @@ -4132,24 +4172,24 @@ arc_print_operand (FILE *file, rtx x, int code) > fputs (".as", file); > output_scaled = 1; > } > - else if (LEGITIMATE_SMALL_DATA_ADDRESS_P (addr) > - && GET_MODE_SIZE (GET_MODE (x)) > 1) > + break; > + case SYMBOL_REF: > + case CONST: > + if (legitimate_small_data_address_p (addr) > + && GET_MODE_SIZE (GET_MODE (x)) > 1) > { > - tree decl = NULL_TREE; > - int align = 0; > - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); > - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) > - == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); > - if (decl) > - align = DECL_ALIGN (decl); > - align = align / BITS_PER_UNIT; > - if ((GET_MODE_SIZE (GET_MODE (x)) == 2) > - && align && ((align & 1) == 0)) > - fputs (".as", file); > - if ((GET_MODE_SIZE (GET_MODE (x)) >= 4) > - && align && ((align & 3) == 0)) > + int align = get_symbol_alignment (addr); > + int mask = 0; > + switch (GET_MODE (x)) > + { > + case E_HImode: > + mask = 1; > + break; > + default: > + mask = 3; > + break; > + } > + if (align && ((align & mask) == 0)) > fputs (".as", file); > } > break; > @@ -4268,6 +4308,9 @@ arc_print_operand (FILE *file, rtx x, int code) > rtx addr = XEXP (x, 0); > int size = GET_MODE_SIZE (GET_MODE (x)); > > + if (legitimate_small_data_address_p (addr)) > + output_sdata = 1; > + > fputc ('[', file); > > switch (GET_CODE (addr)) > @@ -4328,26 +4371,7 @@ arc_print_operand (FILE *file, rtx x, int code) > || XINT (XEXP (XEXP (x, 0), 0), 1) == UNSPEC_TLS_GD))) > arc_output_pic_addr_const (file, x, code); > else > - { > - /* FIXME: Dirty way to handle @var@sda+const. Shd be handled > - with asm_output_symbol_ref */ > - if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) > - { > - x = XEXP (x, 0); > - output_addr_const (file, XEXP (x, 0)); > - if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF && SYMBOL_REF_SMALL_P (XEXP (x, 0))) > - fprintf (file, "@sda"); > - > - if (GET_CODE (XEXP (x, 1)) != CONST_INT > - || INTVAL (XEXP (x, 1)) >= 0) > - fprintf (file, "+"); > - output_addr_const (file, XEXP (x, 1)); > - } > - else > - output_addr_const (file, x); > - } > - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) > - fprintf (file, "@sda"); > + output_addr_const (file, x); > break; > } > } > @@ -4364,10 +4388,13 @@ arc_print_operand_address (FILE *file , rtx addr) > case REG : > fputs (reg_names[REGNO (addr)], file); > break; > - case SYMBOL_REF : > + case SYMBOL_REF: > + if (output_sdata) > + fputs ("gp,", file); > output_addr_const (file, addr); > - if (SYMBOL_REF_SMALL_P (addr)) > - fprintf (file, "@sda"); > + if (output_sdata) > + fputs ("@sda", file); > + output_sdata = 0; > break; > case PLUS : > if (GET_CODE (XEXP (addr, 0)) == MULT) > @@ -6188,7 +6215,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict) > return true; > if (legitimate_scaled_address_p (mode, x, strict)) > return true; > - if (LEGITIMATE_SMALL_DATA_ADDRESS_P (x)) > + if (legitimate_small_data_address_p (x)) > return true; > if (GET_CODE (x) == CONST_INT && LARGE_INT (INTVAL (x))) > return true; > @@ -7991,98 +8018,9 @@ arc_in_small_data_p (const_tree decl) > return false; > } > > -/* Return true if X is a small data address that can be rewritten > - as a gp+symref. */ > - > -static bool > -arc_rewrite_small_data_p (const_rtx x) > -{ > - if (GET_CODE (x) == CONST) > - x = XEXP (x, 0); > - > - if (GET_CODE (x) == PLUS) > - { > - if (GET_CODE (XEXP (x, 1)) == CONST_INT) > - x = XEXP (x, 0); > - } > - > - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) > - { > - gcc_assert (SYMBOL_REF_TLS_MODEL (x) == 0); > - return true; > - } > - return false; > -} > - > -/* If possible, rewrite OP so that it refers to small data using > - explicit relocations. */ > - > -static rtx > -arc_rewrite_small_data_1 (rtx op) > -{ > - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); > - op = copy_insn (op); > - subrtx_ptr_iterator::array_type array; > - FOR_EACH_SUBRTX_PTR (iter, array, &op, ALL) > - { > - rtx *loc = *iter; > - if (arc_rewrite_small_data_p (*loc)) > - { > - *loc = gen_rtx_PLUS (Pmode, rgp, *loc); > - iter.skip_subrtxes (); > - } > - else if (GET_CODE (*loc) == PLUS > - && rtx_equal_p (XEXP (*loc, 0), rgp)) > - iter.skip_subrtxes (); > - } > - return op; > -} > - > -rtx > -arc_rewrite_small_data (rtx op) > -{ > - op = arc_rewrite_small_data_1 (op); > - > - /* Check if we fit small data constraints. */ > - if (MEM_P (op) > - && !LEGITIMATE_SMALL_DATA_ADDRESS_P (XEXP (op, 0))) > - { > - rtx addr = XEXP (op, 0); > - rtx tmp = gen_reg_rtx (Pmode); > - emit_move_insn (tmp, addr); > - op = replace_equiv_address_nv (op, tmp); > - } > - return op; > -} > - > -/* Return true if OP refers to small data symbols directly, not through > - a PLUS. */ > - > -bool > -small_data_pattern (rtx op, machine_mode) > -{ > - if (GET_CODE (op) == SEQUENCE) > - return false; > - > - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); > - subrtx_iterator::array_type array; > - FOR_EACH_SUBRTX (iter, array, op, ALL) > - { > - const_rtx x = *iter; > - if (GET_CODE (x) == PLUS > - && rtx_equal_p (XEXP (x, 0), rgp)) > - iter.skip_subrtxes (); > - else if (arc_rewrite_small_data_p (x)) > - return true; > - } > - return false; > -} > - > /* Return true if OP is an acceptable memory operand for ARCompact > 16-bit gp-relative load instructions. > - op shd look like : [r26, symref@sda] > - i.e. (mem (plus (reg 26) (symref with smalldata flag set)) > - */ > +*/ > /* volatile cache option still to be handled. */ > > bool > @@ -8090,7 +8028,6 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > { > rtx addr; > int size; > - tree decl = NULL_TREE; > int align = 0; > int mask = 0; > > @@ -8110,7 +8047,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > /* Decode the address now. */ > addr = XEXP (op, 0); > > - if (!LEGITIMATE_SMALL_DATA_ADDRESS_P (addr)) > + if (!legitimate_small_data_address_p (addr)) > return false; > > if (!short_p || size == 1) > @@ -8118,14 +8055,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > > /* Now check for the alignment, the short loads using gp require the > addresses to be aligned. */ > - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); > - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); > - if (decl) > - align = DECL_ALIGN (decl); > - align = align / BITS_PER_UNIT; > - > + align = get_symbol_alignment (addr); > switch (mode) > { > case E_HImode: > @@ -8599,11 +8529,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > } > } > > - /* We used to do this only for MODE_INT Modes, but addresses to floating > - point variables may well be in the small data section. */ > - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[0], Pmode)) > - operands[0] = arc_rewrite_small_data (operands[0]); > - > if (mode == SImode && SYMBOLIC_CONST (operands[1])) > { > prepare_pic_move (operands, SImode); > @@ -8613,29 +8538,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > here and references the variable directly. */ > } > > - if (GET_CODE (operands[0]) != MEM > - && !TARGET_NO_SDATA_SET > - && small_data_pattern (operands[1], Pmode)) > - { > - /* This is to take care of address calculations involving sdata > - variables. */ > - operands[1] = arc_rewrite_small_data (operands[1]); > - > - emit_insn (gen_rtx_SET (operands[0],operands[1])); > - /* ??? This note is useless, since it only restates the set itself. > - We should rather use the original SYMBOL_REF. However, there is > - the problem that we are lying to the compiler about these > - SYMBOL_REFs to start with. symbol@sda should be encoded specially > - so that we can tell it apart from an actual symbol. */ > - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); > - > - /* Take care of the REG_EQUAL note that will be attached to mark the > - output reg equal to the initial symbol_ref after this code is > - executed. */ > - emit_move_insn (operands[0], operands[0]); > - return true; > - } > - > if (MEM_P (operands[0]) > && !(reload_in_progress || reload_completed)) > { > @@ -8679,31 +8581,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > return false; > } > > -/* Prepare OPERANDS for an extension using CODE to OMODE. > - Return true iff the move has been emitted. */ > - > -bool > -prepare_extend_operands (rtx *operands, enum rtx_code code, > - machine_mode omode) > -{ > - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) > - { > - /* This is to take care of address calculations involving sdata > - variables. */ > - operands[1] > - = gen_rtx_fmt_e (code, omode, arc_rewrite_small_data (operands[1])); > - emit_insn (gen_rtx_SET (operands[0], operands[1])); > - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); > - > - /* Take care of the REG_EQUAL note that will be attached to mark the > - output reg equal to the initial extension after this code is > - executed. */ > - emit_move_insn (operands[0], operands[0]); > - return true; > - } > - return false; > -} > - > /* Output a library call to a function called FNAME that has been arranged > to be local to any dso. */ > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 0fc7aba..5610bab 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -1771,7 +1771,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:HI 0 "dest_reg_operand" "") > (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, HImode)) DONE;" > + "" > ) > > (define_insn "*zero_extendqisi2_ac" > @@ -1795,7 +1795,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" > + "" > ) > > (define_insn "*zero_extendhisi2_i" > @@ -1820,7 +1820,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" > + "" > ) > > ;; Sign extension instructions. > @@ -1843,7 +1843,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:HI 0 "dest_reg_operand" "") > (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, HImode)) DONE;" > + "" > ) > > (define_insn "*extendqisi2_ac" > @@ -1863,7 +1863,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" > + "" > ) > > (define_insn "*extendhisi2_i" > @@ -1884,7 +1884,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" > + "" > ) > > ;; Unary arithmetic insns > @@ -2777,11 +2777,6 @@ archs4x, archs4xd, archs4xd_slow" > { > operands[2]=force_reg(SImode, operands[2]); > } > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[2], Pmode)) > - { > - operands[2] = force_reg (SImode, arc_rewrite_small_data (operands[2])); > - } > - > ") > > (define_expand "adddi3" > @@ -2985,8 +2980,6 @@ archs4x, archs4xd, archs4xd_slow" > } > if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false)) > operands[c] = force_reg (SImode, operands[c]); > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[c], Pmode)) > - operands[c] = force_reg (SImode, arc_rewrite_small_data (operands[c])); > }") > > ; the casesi expander might generate a sub of zero, so we have to recognize it. > @@ -3342,8 +3335,7 @@ archs4x, archs4xd, archs4xd_slow" > "" > "if (!satisfies_constraint_Cux (operands[2])) > operands[1] = force_reg (SImode, operands[1]); > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) > - operands[1] = arc_rewrite_small_data (operands[1]);") > + ") > > (define_insn "andsi3_i" > [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W") > diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md > index 7249107..90c736e 100644 > --- a/gcc/config/arc/constraints.md > +++ b/gcc/config/arc/constraints.md > @@ -347,11 +347,7 @@ > (match_test "!cmem_address (XEXP (op, 0), SImode)") > (not (match_operand 0 "long_immediate_loadstore_operand")))) > > -; Don't use define_memory_constraint here as the relocation patching > -; for small data symbols only works within a ld/st instruction and > -; define_memory_constraint may result in the address being calculated > -; into a register first. > -(define_constraint "Usd" > +(define_memory_constraint "Usd" > "@internal > A valid _small-data_ memory operand for ARCompact instructions" > (and (match_code "mem") > diff --git a/gcc/testsuite/gcc.target/arc/interrupt-8.c b/gcc/testsuite/gcc.target/arc/interrupt-8.c > index 60fd87b..f2cc4c4 100644 > --- a/gcc/testsuite/gcc.target/arc/interrupt-8.c > +++ b/gcc/testsuite/gcc.target/arc/interrupt-8.c > @@ -2,8 +2,7 @@ > /* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */ > /* { dg-options "-O2 -mirq-ctrl-saved=r0-r17" } */ > > -/* Check if the registers R0-R17 are automatically saved. GP is saved > - by the compiler. */ > +/* Check if the registers R0-R17 are automatically saved. */ > > int a; > > @@ -18,8 +17,6 @@ foo(void) > /* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */ > -/* { dg-final { scan-assembler "st.*gp,\\\[sp,-4\\\]" } } */ > -/* { dg-final { scan-assembler "ld.*gp,\\\[sp\\\]" } } */ > /* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/loop-4.c b/gcc/testsuite/gcc.target/arc/loop-4.c > index 99a93a7..dbe5d3f 100644 > --- a/gcc/testsuite/gcc.target/arc/loop-4.c > +++ b/gcc/testsuite/gcc.target/arc/loop-4.c > @@ -1,6 +1,6 @@ > /* { dg-do assemble } */ > /* { dg-do compile } */ > -/* { dg-options "-Os" } */ > +/* { dg-options "-Os -fbranch-count-reg" } */ > > > void fn1(void *p1, int p2, int p3) > diff --git a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > index 7c688bb..83d5fd7 100644 > --- a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > +++ b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-Os" } */ > +/* { dg-options "-Os -fbranch-count-reg" } */ > > /* This caused an assertion within arc_loop_hazard. */ > > diff --git a/gcc/testsuite/gcc.target/arc/sdata-3.c b/gcc/testsuite/gcc.target/arc/sdata-3.c > index cdf3b6d..4df7074 100644 > --- a/gcc/testsuite/gcc.target/arc/sdata-3.c > +++ b/gcc/testsuite/gcc.target/arc/sdata-3.c > @@ -10,9 +10,13 @@ short g_c; > char g_d; > > #define TEST(name, optype) \ > - void test_ ## name (optype x) \ > + optype testLD_ ## name (optype x) \ > { \ > - g_ ## name += x; \ > + return g_ ## name + x; \ > + } \ > + void testST_ ## name (optype x) \ > + { \ > + g_ ## name = x; \ > } > > TEST (a, int) > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 4/5] [ARC] Cleanup sdata handling. 2018-04-27 21:40 ` Andrew Burgess @ 2018-04-30 13:18 ` Claudiu Zissulescu 0 siblings, 0 replies; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-30 13:18 UTC (permalink / raw) To: Andrew Burgess, Claudiu Zissulescu Cc: gcc-patches, Francois.Bedard, Claudiu Zissulescu committed. Thank you for your review, Claudiu ________________________________________ From: Andrew Burgess [andrew.burgess@embecosm.com] Sent: Friday, April 27, 2018 11:39 PM To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com; Claudiu Zissulescu Subject: Re: [PATCH 4/5] [ARC] Cleanup sdata handling. * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:13 +0200]: > From: Claudiu Zissulescu <claziss@gmail.com> > > Clean up how we handle small data load/store operations. This patch clears -flto-fat-lto-object LTO related errors. > > gcc/ > 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc-protos.h (prepare_extend_operands): Remove. > (small_data_pattern): Likewise. > (arc_rewrite_small_data): Likewise. > * config/arc/arc.c (LEGITIMATE_SMALL_DATA_OFFSET_P): Remove. > (LEGITIMATE_SMALL_DATA_ADDRESS_P): Likewise. > (get_symbol_alignment): New function. > (legitimate_small_data_address_p): Likewise. > (legitimate_scaled_address): Update, call > legitimate_small_data_address_p. > (output_sdata): New static variable. > (arc_print_operand): Update how we handle small data operands. > (arc_print_operand_address): Likewise. > (arc_legitimate_address_p): Update, use > legitimate_small_data_address_p. > (arc_rewrite_small_data_p): Remove. > (arc_rewrite_small_data_1): Likewise. > (arc_rewrite_small_data): Likewise. > (small_data_pattern): Likewise. > (compact_sda_memory_operand): Update to use > legitimate_small_data_address_p and get_symbol_alignment. > (prepare_move_operands): Don't rewite sdata pattern. > (prepare_extend_operands): Remove. > * config/arc/arc.md (zero_extendqihi2): Don't rewrite sdata > pattern. > (zero_extendqisi2): Likewise. > (zero_extendhisi2): Likewise. > (extendqihi2): Likewise. > (extendqisi2): Likewise. > (extendhisi2): Likewise. > (addsi3): Likewise. > (subsi3): Likewise. > (andsi3): Likewise. > * config/arc/constraints.md (Usd): Change it to memory constraint. > > gcc/testsuite > 2018-01-18 Claudiu Zissulescu <claziss@synopsys.com> > > * gcc.target/arc/interrupt-8.c: Update test. > * gcc.target/arc/loop-4.c: Likewise. > * gcc.target/arc/loop-hazard-1.c: Likewise. > * gcc.target/arc/sdata-3.c: Likewise. Looks like a good clean up. Thanks, Andrew > --- > gcc/config/arc/arc-protos.h | 4 - > gcc/config/arc/arc.c | 309 ++++++++------------------- > gcc/config/arc/arc.md | 22 +- > gcc/config/arc/constraints.md | 6 +- > gcc/testsuite/gcc.target/arc/interrupt-8.c | 5 +- > gcc/testsuite/gcc.target/arc/loop-4.c | 2 +- > gcc/testsuite/gcc.target/arc/loop-hazard-1.c | 2 +- > gcc/testsuite/gcc.target/arc/sdata-3.c | 8 +- > 8 files changed, 110 insertions(+), 248 deletions(-) > > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 0ba6871..67f3b4e 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -33,8 +33,6 @@ extern void arc_print_operand (FILE *, rtx, int); > extern void arc_print_operand_address (FILE *, rtx); > extern void arc_final_prescan_insn (rtx_insn *, rtx *, int); > extern const char *arc_output_libcall (const char *); > -extern bool prepare_extend_operands (rtx *operands, enum rtx_code code, > - machine_mode omode); > extern int arc_output_addsi (rtx *operands, bool, bool); > extern int arc_output_commutative_cond_exec (rtx *operands, bool); > extern bool arc_expand_movmem (rtx *operands); > @@ -65,8 +63,6 @@ extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool); > extern bool arc_is_longcall_p (rtx); > extern bool arc_is_shortcall_p (rtx); > extern bool valid_brcc_with_delay_p (rtx *); > -extern bool small_data_pattern (rtx , machine_mode); > -extern rtx arc_rewrite_small_data (rtx); > extern bool arc_ccfsm_cond_exec_p (void); > struct secondary_reload_info; > extern int arc_register_move_cost (machine_mode, enum reg_class, > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 2ccdce8..2ce1744 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -96,22 +96,6 @@ HARD_REG_SET overrideregs; > ? 0 \ > : -(-GET_MODE_SIZE (MODE) | -4) >> 1))) > > -#define LEGITIMATE_SMALL_DATA_OFFSET_P(X) \ > - (GET_CODE (X) == CONST \ > - && GET_CODE (XEXP ((X), 0)) == PLUS \ > - && GET_CODE (XEXP (XEXP ((X), 0), 0)) == SYMBOL_REF \ > - && SYMBOL_REF_SMALL_P (XEXP (XEXP ((X), 0), 0)) \ > - && GET_CODE (XEXP(XEXP ((X), 0), 1)) == CONST_INT \ > - && INTVAL (XEXP (XEXP ((X), 0), 1)) <= g_switch_value) > - > -#define LEGITIMATE_SMALL_DATA_ADDRESS_P(X) \ > - (GET_CODE (X) == PLUS \ > - && REG_P (XEXP ((X), 0)) \ > - && REGNO (XEXP ((X), 0)) == SDATA_BASE_REGNUM \ > - && ((GET_CODE (XEXP ((X), 1)) == SYMBOL_REF \ > - && SYMBOL_REF_SMALL_P (XEXP ((X), 1))) \ > - || LEGITIMATE_SMALL_DATA_OFFSET_P (XEXP ((X), 1)))) > - > /* Array of valid operand punctuation characters. */ > char arc_punct_chars[256]; > > @@ -308,6 +292,60 @@ static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT, > /* Globally visible information about currently selected cpu. */ > const arc_cpu_t *arc_selected_cpu; > > +/* Given a symbol RTX (const (symb <+ const_int>), returns its > + alignment. */ > + > +static int > +get_symbol_alignment (rtx x) > +{ > + tree decl = NULL_TREE; > + int align = 0; > + > + switch (GET_CODE (x)) > + { > + case SYMBOL_REF: > + decl = SYMBOL_REF_DECL (x); > + break; > + case CONST: > + return get_symbol_alignment (XEXP (x, 0)); > + case PLUS: > + gcc_assert (CONST_INT_P (XEXP (x, 1))); > + return get_symbol_alignment (XEXP (x, 0)); > + default: > + return 0; > + } > + > + if (decl) > + align = DECL_ALIGN (decl); > + align = align / BITS_PER_UNIT; > + return align; > +} > + > +/* Return true if x is ok to be used as a small data address. */ > + > +static bool > +legitimate_small_data_address_p (rtx x) > +{ > + switch (GET_CODE (x)) > + { > + case CONST: > + return legitimate_small_data_address_p (XEXP (x, 0)); > + case SYMBOL_REF: > + return SYMBOL_REF_SMALL_P (x); > + case PLUS: > + { > + bool p0 = (GET_CODE (XEXP (x, 0)) == SYMBOL_REF) > + && SYMBOL_REF_SMALL_P (XEXP (x, 0)); > + bool p1 = CONST_INT_P (XEXP (x, 1)) > + && (INTVAL (XEXP (x, 1)) <= g_switch_value); > + return p0 && p1; > + } > + default: > + return false; > + } > +} > + > +/* TRUE if op is an scaled address. */ > static bool > legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) > { > @@ -352,14 +390,13 @@ legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict) > return true; > return false; > } > + > + /* Scalled addresses for sdata is done other places. */ > + if (legitimate_small_data_address_p (op)) > + return false; > + > if (CONSTANT_P (XEXP (op, 1))) > - { > - /* Scalled addresses for sdata is done other places. */ > - if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF > - && SYMBOL_REF_SMALL_P (XEXP (op, 1))) > - return false; > return true; > - } > > return false; > } > @@ -3780,6 +3817,9 @@ arc_add_jli_section (rtx pat) > reset when we output the scaled address. */ > static int output_scaled = 0; > > +/* Set when we force sdata output. */ > +static int output_sdata = 0; > + > /* Print operand X (an rtx) in assembler syntax to file FILE. > CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. > For `%' followed by punctuation, CODE is the punctuation and X is null. */ > @@ -4132,24 +4172,24 @@ arc_print_operand (FILE *file, rtx x, int code) > fputs (".as", file); > output_scaled = 1; > } > - else if (LEGITIMATE_SMALL_DATA_ADDRESS_P (addr) > - && GET_MODE_SIZE (GET_MODE (x)) > 1) > + break; > + case SYMBOL_REF: > + case CONST: > + if (legitimate_small_data_address_p (addr) > + && GET_MODE_SIZE (GET_MODE (x)) > 1) > { > - tree decl = NULL_TREE; > - int align = 0; > - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); > - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) > - == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); > - if (decl) > - align = DECL_ALIGN (decl); > - align = align / BITS_PER_UNIT; > - if ((GET_MODE_SIZE (GET_MODE (x)) == 2) > - && align && ((align & 1) == 0)) > - fputs (".as", file); > - if ((GET_MODE_SIZE (GET_MODE (x)) >= 4) > - && align && ((align & 3) == 0)) > + int align = get_symbol_alignment (addr); > + int mask = 0; > + switch (GET_MODE (x)) > + { > + case E_HImode: > + mask = 1; > + break; > + default: > + mask = 3; > + break; > + } > + if (align && ((align & mask) == 0)) > fputs (".as", file); > } > break; > @@ -4268,6 +4308,9 @@ arc_print_operand (FILE *file, rtx x, int code) > rtx addr = XEXP (x, 0); > int size = GET_MODE_SIZE (GET_MODE (x)); > > + if (legitimate_small_data_address_p (addr)) > + output_sdata = 1; > + > fputc ('[', file); > > switch (GET_CODE (addr)) > @@ -4328,26 +4371,7 @@ arc_print_operand (FILE *file, rtx x, int code) > || XINT (XEXP (XEXP (x, 0), 0), 1) == UNSPEC_TLS_GD))) > arc_output_pic_addr_const (file, x, code); > else > - { > - /* FIXME: Dirty way to handle @var@sda+const. Shd be handled > - with asm_output_symbol_ref */ > - if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) > - { > - x = XEXP (x, 0); > - output_addr_const (file, XEXP (x, 0)); > - if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF && SYMBOL_REF_SMALL_P (XEXP (x, 0))) > - fprintf (file, "@sda"); > - > - if (GET_CODE (XEXP (x, 1)) != CONST_INT > - || INTVAL (XEXP (x, 1)) >= 0) > - fprintf (file, "+"); > - output_addr_const (file, XEXP (x, 1)); > - } > - else > - output_addr_const (file, x); > - } > - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) > - fprintf (file, "@sda"); > + output_addr_const (file, x); > break; > } > } > @@ -4364,10 +4388,13 @@ arc_print_operand_address (FILE *file , rtx addr) > case REG : > fputs (reg_names[REGNO (addr)], file); > break; > - case SYMBOL_REF : > + case SYMBOL_REF: > + if (output_sdata) > + fputs ("gp,", file); > output_addr_const (file, addr); > - if (SYMBOL_REF_SMALL_P (addr)) > - fprintf (file, "@sda"); > + if (output_sdata) > + fputs ("@sda", file); > + output_sdata = 0; > break; > case PLUS : > if (GET_CODE (XEXP (addr, 0)) == MULT) > @@ -6188,7 +6215,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict) > return true; > if (legitimate_scaled_address_p (mode, x, strict)) > return true; > - if (LEGITIMATE_SMALL_DATA_ADDRESS_P (x)) > + if (legitimate_small_data_address_p (x)) > return true; > if (GET_CODE (x) == CONST_INT && LARGE_INT (INTVAL (x))) > return true; > @@ -7991,98 +8018,9 @@ arc_in_small_data_p (const_tree decl) > return false; > } > > -/* Return true if X is a small data address that can be rewritten > - as a gp+symref. */ > - > -static bool > -arc_rewrite_small_data_p (const_rtx x) > -{ > - if (GET_CODE (x) == CONST) > - x = XEXP (x, 0); > - > - if (GET_CODE (x) == PLUS) > - { > - if (GET_CODE (XEXP (x, 1)) == CONST_INT) > - x = XEXP (x, 0); > - } > - > - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) > - { > - gcc_assert (SYMBOL_REF_TLS_MODEL (x) == 0); > - return true; > - } > - return false; > -} > - > -/* If possible, rewrite OP so that it refers to small data using > - explicit relocations. */ > - > -static rtx > -arc_rewrite_small_data_1 (rtx op) > -{ > - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); > - op = copy_insn (op); > - subrtx_ptr_iterator::array_type array; > - FOR_EACH_SUBRTX_PTR (iter, array, &op, ALL) > - { > - rtx *loc = *iter; > - if (arc_rewrite_small_data_p (*loc)) > - { > - *loc = gen_rtx_PLUS (Pmode, rgp, *loc); > - iter.skip_subrtxes (); > - } > - else if (GET_CODE (*loc) == PLUS > - && rtx_equal_p (XEXP (*loc, 0), rgp)) > - iter.skip_subrtxes (); > - } > - return op; > -} > - > -rtx > -arc_rewrite_small_data (rtx op) > -{ > - op = arc_rewrite_small_data_1 (op); > - > - /* Check if we fit small data constraints. */ > - if (MEM_P (op) > - && !LEGITIMATE_SMALL_DATA_ADDRESS_P (XEXP (op, 0))) > - { > - rtx addr = XEXP (op, 0); > - rtx tmp = gen_reg_rtx (Pmode); > - emit_move_insn (tmp, addr); > - op = replace_equiv_address_nv (op, tmp); > - } > - return op; > -} > - > -/* Return true if OP refers to small data symbols directly, not through > - a PLUS. */ > - > -bool > -small_data_pattern (rtx op, machine_mode) > -{ > - if (GET_CODE (op) == SEQUENCE) > - return false; > - > - rtx rgp = gen_rtx_REG (Pmode, SDATA_BASE_REGNUM); > - subrtx_iterator::array_type array; > - FOR_EACH_SUBRTX (iter, array, op, ALL) > - { > - const_rtx x = *iter; > - if (GET_CODE (x) == PLUS > - && rtx_equal_p (XEXP (x, 0), rgp)) > - iter.skip_subrtxes (); > - else if (arc_rewrite_small_data_p (x)) > - return true; > - } > - return false; > -} > - > /* Return true if OP is an acceptable memory operand for ARCompact > 16-bit gp-relative load instructions. > - op shd look like : [r26, symref@sda] > - i.e. (mem (plus (reg 26) (symref with smalldata flag set)) > - */ > +*/ > /* volatile cache option still to be handled. */ > > bool > @@ -8090,7 +8028,6 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > { > rtx addr; > int size; > - tree decl = NULL_TREE; > int align = 0; > int mask = 0; > > @@ -8110,7 +8047,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > /* Decode the address now. */ > addr = XEXP (op, 0); > > - if (!LEGITIMATE_SMALL_DATA_ADDRESS_P (addr)) > + if (!legitimate_small_data_address_p (addr)) > return false; > > if (!short_p || size == 1) > @@ -8118,14 +8055,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p) > > /* Now check for the alignment, the short loads using gp require the > addresses to be aligned. */ > - if (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (addr, 1)); > - else if (GET_CODE (XEXP (XEXP (XEXP (addr, 1), 0), 0)) == SYMBOL_REF) > - decl = SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr, 1), 0), 0)); > - if (decl) > - align = DECL_ALIGN (decl); > - align = align / BITS_PER_UNIT; > - > + align = get_symbol_alignment (addr); > switch (mode) > { > case E_HImode: > @@ -8599,11 +8529,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > } > } > > - /* We used to do this only for MODE_INT Modes, but addresses to floating > - point variables may well be in the small data section. */ > - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[0], Pmode)) > - operands[0] = arc_rewrite_small_data (operands[0]); > - > if (mode == SImode && SYMBOLIC_CONST (operands[1])) > { > prepare_pic_move (operands, SImode); > @@ -8613,29 +8538,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > here and references the variable directly. */ > } > > - if (GET_CODE (operands[0]) != MEM > - && !TARGET_NO_SDATA_SET > - && small_data_pattern (operands[1], Pmode)) > - { > - /* This is to take care of address calculations involving sdata > - variables. */ > - operands[1] = arc_rewrite_small_data (operands[1]); > - > - emit_insn (gen_rtx_SET (operands[0],operands[1])); > - /* ??? This note is useless, since it only restates the set itself. > - We should rather use the original SYMBOL_REF. However, there is > - the problem that we are lying to the compiler about these > - SYMBOL_REFs to start with. symbol@sda should be encoded specially > - so that we can tell it apart from an actual symbol. */ > - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); > - > - /* Take care of the REG_EQUAL note that will be attached to mark the > - output reg equal to the initial symbol_ref after this code is > - executed. */ > - emit_move_insn (operands[0], operands[0]); > - return true; > - } > - > if (MEM_P (operands[0]) > && !(reload_in_progress || reload_completed)) > { > @@ -8679,31 +8581,6 @@ prepare_move_operands (rtx *operands, machine_mode mode) > return false; > } > > -/* Prepare OPERANDS for an extension using CODE to OMODE. > - Return true iff the move has been emitted. */ > - > -bool > -prepare_extend_operands (rtx *operands, enum rtx_code code, > - machine_mode omode) > -{ > - if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) > - { > - /* This is to take care of address calculations involving sdata > - variables. */ > - operands[1] > - = gen_rtx_fmt_e (code, omode, arc_rewrite_small_data (operands[1])); > - emit_insn (gen_rtx_SET (operands[0], operands[1])); > - set_unique_reg_note (get_last_insn (), REG_EQUAL, operands[1]); > - > - /* Take care of the REG_EQUAL note that will be attached to mark the > - output reg equal to the initial extension after this code is > - executed. */ > - emit_move_insn (operands[0], operands[0]); > - return true; > - } > - return false; > -} > - > /* Output a library call to a function called FNAME that has been arranged > to be local to any dso. */ > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 0fc7aba..5610bab 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -1771,7 +1771,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:HI 0 "dest_reg_operand" "") > (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, HImode)) DONE;" > + "" > ) > > (define_insn "*zero_extendqisi2_ac" > @@ -1795,7 +1795,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" > + "" > ) > > (define_insn "*zero_extendhisi2_i" > @@ -1820,7 +1820,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" > + "" > ) > > ;; Sign extension instructions. > @@ -1843,7 +1843,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:HI 0 "dest_reg_operand" "") > (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, HImode)) DONE;" > + "" > ) > > (define_insn "*extendqisi2_ac" > @@ -1863,7 +1863,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" > + "" > ) > > (define_insn "*extendhisi2_i" > @@ -1884,7 +1884,7 @@ archs4x, archs4xd, archs4xd_slow" > [(set (match_operand:SI 0 "dest_reg_operand" "") > (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] > "" > - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" > + "" > ) > > ;; Unary arithmetic insns > @@ -2777,11 +2777,6 @@ archs4x, archs4xd, archs4xd_slow" > { > operands[2]=force_reg(SImode, operands[2]); > } > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[2], Pmode)) > - { > - operands[2] = force_reg (SImode, arc_rewrite_small_data (operands[2])); > - } > - > ") > > (define_expand "adddi3" > @@ -2985,8 +2980,6 @@ archs4x, archs4xd, archs4xd_slow" > } > if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false)) > operands[c] = force_reg (SImode, operands[c]); > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[c], Pmode)) > - operands[c] = force_reg (SImode, arc_rewrite_small_data (operands[c])); > }") > > ; the casesi expander might generate a sub of zero, so we have to recognize it. > @@ -3342,8 +3335,7 @@ archs4x, archs4xd, archs4xd_slow" > "" > "if (!satisfies_constraint_Cux (operands[2])) > operands[1] = force_reg (SImode, operands[1]); > - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) > - operands[1] = arc_rewrite_small_data (operands[1]);") > + ") > > (define_insn "andsi3_i" > [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W") > diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md > index 7249107..90c736e 100644 > --- a/gcc/config/arc/constraints.md > +++ b/gcc/config/arc/constraints.md > @@ -347,11 +347,7 @@ > (match_test "!cmem_address (XEXP (op, 0), SImode)") > (not (match_operand 0 "long_immediate_loadstore_operand")))) > > -; Don't use define_memory_constraint here as the relocation patching > -; for small data symbols only works within a ld/st instruction and > -; define_memory_constraint may result in the address being calculated > -; into a register first. > -(define_constraint "Usd" > +(define_memory_constraint "Usd" > "@internal > A valid _small-data_ memory operand for ARCompact instructions" > (and (match_code "mem") > diff --git a/gcc/testsuite/gcc.target/arc/interrupt-8.c b/gcc/testsuite/gcc.target/arc/interrupt-8.c > index 60fd87b..f2cc4c4 100644 > --- a/gcc/testsuite/gcc.target/arc/interrupt-8.c > +++ b/gcc/testsuite/gcc.target/arc/interrupt-8.c > @@ -2,8 +2,7 @@ > /* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */ > /* { dg-options "-O2 -mirq-ctrl-saved=r0-r17" } */ > > -/* Check if the registers R0-R17 are automatically saved. GP is saved > - by the compiler. */ > +/* Check if the registers R0-R17 are automatically saved. */ > > int a; > > @@ -18,8 +17,6 @@ foo(void) > /* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */ > -/* { dg-final { scan-assembler "st.*gp,\\\[sp,-4\\\]" } } */ > -/* { dg-final { scan-assembler "ld.*gp,\\\[sp\\\]" } } */ > /* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */ > /* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/loop-4.c b/gcc/testsuite/gcc.target/arc/loop-4.c > index 99a93a7..dbe5d3f 100644 > --- a/gcc/testsuite/gcc.target/arc/loop-4.c > +++ b/gcc/testsuite/gcc.target/arc/loop-4.c > @@ -1,6 +1,6 @@ > /* { dg-do assemble } */ > /* { dg-do compile } */ > -/* { dg-options "-Os" } */ > +/* { dg-options "-Os -fbranch-count-reg" } */ > > > void fn1(void *p1, int p2, int p3) > diff --git a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > index 7c688bb..83d5fd7 100644 > --- a/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > +++ b/gcc/testsuite/gcc.target/arc/loop-hazard-1.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-Os" } */ > +/* { dg-options "-Os -fbranch-count-reg" } */ > > /* This caused an assertion within arc_loop_hazard. */ > > diff --git a/gcc/testsuite/gcc.target/arc/sdata-3.c b/gcc/testsuite/gcc.target/arc/sdata-3.c > index cdf3b6d..4df7074 100644 > --- a/gcc/testsuite/gcc.target/arc/sdata-3.c > +++ b/gcc/testsuite/gcc.target/arc/sdata-3.c > @@ -10,9 +10,13 @@ short g_c; > char g_d; > > #define TEST(name, optype) \ > - void test_ ## name (optype x) \ > + optype testLD_ ## name (optype x) \ > { \ > - g_ ## name += x; \ > + return g_ ## name + x; \ > + } \ > + void testST_ ## name (optype x) \ > + { \ > + g_ ## name = x; \ > } > > TEST (a, int) > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/5] [ARC] Update movhi and movdi patterns. 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu ` (2 preceding siblings ...) 2018-04-06 9:00 ` [PATCH 4/5] [ARC] Cleanup sdata handling Claudiu Zissulescu @ 2018-04-06 9:00 ` Claudiu Zissulescu 2018-04-27 21:39 ` Andrew Burgess 2018-04-06 9:00 ` [PATCH 5/5] [ARC] Clear the instruction cache using syscalls Claudiu Zissulescu 4 siblings, 1 reply; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw) To: gcc-patches Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess, Claudiu Zissulescu From: Claudiu Zissulescu <claziss@gmail.com> Allow signed 6-bit short immediates into st[d] instructions. 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_split_move): Allow signed 6-bit constants as source of std instructions. * config/arc/arc.md (movsi_insn): Update pattern predicate to allow 6-bit constants as source for store instructions. (movdi_insn): Update instruction pattern to allow 6-bit constants as source for store instructions. testsuite/ 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/store-merge-1.c: New test. * gcc.target/arc/add_n-combine.c: Update test. --- gcc/config/arc/arc.c | 3 ++- gcc/config/arc/arc.md | 25 +++++++++++++------------ gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +- gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++ 4 files changed, 33 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 47d3ba4..2ccdce8 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands) if (TARGET_LL64 && ((memory_operand (operands[0], mode) - && even_register_operand (operands[1], mode)) + && (even_register_operand (operands[1], mode) + || satisfies_constraint_Cm3 (operands[1]))) || (memory_operand (operands[1], mode) && even_register_operand (operands[0], mode)))) { diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ffd9d5b..0fc7aba 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow" /* Don't use a LIMM that we could load with a single insn - we loose delay-slot filling opportunities. */ && !satisfies_constraint_I (operands[1]) - && satisfies_constraint_Usc (operands[0]))" + && satisfies_constraint_Usc (operands[0])) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], SImode))" "@ mov%? %0,%1%& ;0 mov%? %0,%1%& ;1 @@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow" ") (define_insn_and_split "*movdi_insn" - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] "register_operand (operands[0], DImode) - || register_operand (operands[1], DImode)" + || register_operand (operands[1], DImode) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], DImode))" "* { switch (which_alternative) @@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow" case 2: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[1], DImode) + && even_register_operand (operands[0], DImode)) return \"ldd%U1%V1 %0,%1%&\"; return \"#\"; case 3: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[0], DImode) + && (even_register_operand (operands[1], DImode) + || satisfies_constraint_Cm3 (operands[1]))) return \"std%U0%V0 %1,%0\"; return \"#\"; } diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c index db6454f..cd32ed3 100644 --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c @@ -45,4 +45,4 @@ void f() { a(at3.bn[bu]); } -/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ +/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c new file mode 100644 index 0000000..4bb8dcb --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* This tests checks if we use st w6,[reg] format. */ + +typedef struct { + unsigned long __val[2]; +} sigset_t; + +int sigemptyset2 (sigset_t *set) +{ + set->__val[0] = 0; + set->__val[1] = 0; + return 0; +} + +/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */ -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] [ARC] Update movhi and movdi patterns. 2018-04-06 9:00 ` [PATCH 3/5] [ARC] Update movhi and movdi patterns Claudiu Zissulescu @ 2018-04-27 21:39 ` Andrew Burgess 2018-04-30 13:17 ` Claudiu Zissulescu 0 siblings, 1 reply; 16+ messages in thread From: Andrew Burgess @ 2018-04-27 21:39 UTC (permalink / raw) To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard, Claudiu Zissulescu * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:12 +0200]: > From: Claudiu Zissulescu <claziss@gmail.com> > > Allow signed 6-bit short immediates into st[d] instructions. > > 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.c (arc_split_move): Allow signed 6-bit constants > as source of std instructions. > * config/arc/arc.md (movsi_insn): Update pattern predicate to > allow 6-bit constants as source for store instructions. > (movdi_insn): Update instruction pattern to allow 6-bit constants > as source for store instructions. > > testsuite/ > 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> > > * gcc.target/arc/store-merge-1.c: New test. > * gcc.target/arc/add_n-combine.c: Update test. Looks good thanks, Andrew > --- > gcc/config/arc/arc.c | 3 ++- > gcc/config/arc/arc.md | 25 +++++++++++++------------ > gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +- > gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++ > 4 files changed, 33 insertions(+), 14 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 47d3ba4..2ccdce8 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands) > > if (TARGET_LL64 > && ((memory_operand (operands[0], mode) > - && even_register_operand (operands[1], mode)) > + && (even_register_operand (operands[1], mode) > + || satisfies_constraint_Cm3 (operands[1]))) > || (memory_operand (operands[1], mode) > && even_register_operand (operands[0], mode)))) > { > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index ffd9d5b..0fc7aba 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow" > /* Don't use a LIMM that we could load with a single insn - we loose > delay-slot filling opportunities. */ > && !satisfies_constraint_I (operands[1]) > - && satisfies_constraint_Usc (operands[0]))" > + && satisfies_constraint_Usc (operands[0])) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], SImode))" > "@ > mov%? %0,%1%& ;0 > mov%? %0,%1%& ;1 > @@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow" > ") > > (define_insn_and_split "*movdi_insn" > - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") > - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] > + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") > + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] > "register_operand (operands[0], DImode) > - || register_operand (operands[1], DImode)" > + || register_operand (operands[1], DImode) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], DImode))" > "* > { > switch (which_alternative) > @@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow" > > case 2: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[1], DImode) > + && even_register_operand (operands[0], DImode)) > return \"ldd%U1%V1 %0,%1%&\"; > return \"#\"; > > case 3: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[0], DImode) > + && (even_register_operand (operands[1], DImode) > + || satisfies_constraint_Cm3 (operands[1]))) > return \"std%U0%V0 %1,%0\"; > return \"#\"; > } > diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c > index db6454f..cd32ed3 100644 > --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c > +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c > @@ -45,4 +45,4 @@ void f() { > a(at3.bn[bu]); > } > > -/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ > +/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c > new file mode 100644 > index 0000000..4bb8dcb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3" } */ > + > +/* This tests checks if we use st w6,[reg] format. */ > + > +typedef struct { > + unsigned long __val[2]; > +} sigset_t; > + > +int sigemptyset2 (sigset_t *set) > +{ > + set->__val[0] = 0; > + set->__val[1] = 0; > + return 0; > +} > + > +/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */ > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 3/5] [ARC] Update movhi and movdi patterns. 2018-04-27 21:39 ` Andrew Burgess @ 2018-04-30 13:17 ` Claudiu Zissulescu 0 siblings, 0 replies; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-30 13:17 UTC (permalink / raw) To: Andrew Burgess, Claudiu Zissulescu Cc: gcc-patches, Francois.Bedard, Claudiu Zissulescu committed. Thank you for your review, Claudiu ________________________________________ From: Andrew Burgess [andrew.burgess@embecosm.com] Sent: Friday, April 27, 2018 11:27 PM To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com; Claudiu Zissulescu Subject: Re: [PATCH 3/5] [ARC] Update movhi and movdi patterns. * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:12 +0200]: > From: Claudiu Zissulescu <claziss@gmail.com> > > Allow signed 6-bit short immediates into st[d] instructions. > > 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.c (arc_split_move): Allow signed 6-bit constants > as source of std instructions. > * config/arc/arc.md (movsi_insn): Update pattern predicate to > allow 6-bit constants as source for store instructions. > (movdi_insn): Update instruction pattern to allow 6-bit constants > as source for store instructions. > > testsuite/ > 2017-10-19 Claudiu Zissulescu <claziss@synopsys.com> > > * gcc.target/arc/store-merge-1.c: New test. > * gcc.target/arc/add_n-combine.c: Update test. Looks good thanks, Andrew > --- > gcc/config/arc/arc.c | 3 ++- > gcc/config/arc/arc.md | 25 +++++++++++++------------ > gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +- > gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++ > 4 files changed, 33 insertions(+), 14 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 47d3ba4..2ccdce8 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands) > > if (TARGET_LL64 > && ((memory_operand (operands[0], mode) > - && even_register_operand (operands[1], mode)) > + && (even_register_operand (operands[1], mode) > + || satisfies_constraint_Cm3 (operands[1]))) > || (memory_operand (operands[1], mode) > && even_register_operand (operands[0], mode)))) > { > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index ffd9d5b..0fc7aba 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow" > /* Don't use a LIMM that we could load with a single insn - we loose > delay-slot filling opportunities. */ > && !satisfies_constraint_I (operands[1]) > - && satisfies_constraint_Usc (operands[0]))" > + && satisfies_constraint_Usc (operands[0])) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], SImode))" > "@ > mov%? %0,%1%& ;0 > mov%? %0,%1%& ;1 > @@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow" > ") > > (define_insn_and_split "*movdi_insn" > - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") > - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] > + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") > + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] > "register_operand (operands[0], DImode) > - || register_operand (operands[1], DImode)" > + || register_operand (operands[1], DImode) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], DImode))" > "* > { > switch (which_alternative) > @@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow" > > case 2: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[1], DImode) > + && even_register_operand (operands[0], DImode)) > return \"ldd%U1%V1 %0,%1%&\"; > return \"#\"; > > case 3: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[0], DImode) > + && (even_register_operand (operands[1], DImode) > + || satisfies_constraint_Cm3 (operands[1]))) > return \"std%U0%V0 %1,%0\"; > return \"#\"; > } > diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c > index db6454f..cd32ed3 100644 > --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c > +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c > @@ -45,4 +45,4 @@ void f() { > a(at3.bn[bu]); > } > > -/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ > +/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c > new file mode 100644 > index 0000000..4bb8dcb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3" } */ > + > +/* This tests checks if we use st w6,[reg] format. */ > + > +typedef struct { > + unsigned long __val[2]; > +} sigset_t; > + > +int sigemptyset2 (sigset_t *set) > +{ > + set->__val[0] = 0; > + set->__val[1] = 0; > + return 0; > +} > + > +/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */ > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/5] [ARC] Clear the instruction cache using syscalls. 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu ` (3 preceding siblings ...) 2018-04-06 9:00 ` [PATCH 3/5] [ARC] Update movhi and movdi patterns Claudiu Zissulescu @ 2018-04-06 9:00 ` Claudiu Zissulescu 2018-04-27 21:44 ` Andrew Burgess 4 siblings, 1 reply; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-06 9:00 UTC (permalink / raw) To: gcc-patches; +Cc: Claudiu.Zissulescu, Francois.Bedard, andrew.burgess Clear the instruction cache from `beg' to `end'. This makes an inline system call to SYS_cacheflush. gcc/ 2017-03-28 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/linux.h (CLEAR_INSN_CACHE): Define. --- gcc/config/arc/linux.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h index 4e87dfe..96d548e 100644 --- a/gcc/config/arc/linux.h +++ b/gcc/config/arc/linux.h @@ -109,3 +109,17 @@ along with GCC; see the file COPYING3. If not see /* Build attribute: procedure call standard. */ #undef ATTRIBUTE_PCS #define ATTRIBUTE_PCS 3 + +/* Clear the instruction cache from `beg' to `end'. This makes an + inline system call to SYS_cacheflush. */ +#undef CLEAR_INSN_CACHE +#define CLEAR_INSN_CACHE(beg, end) \ +{ \ + register unsigned long _beg __asm ("r0") = (unsigned long) (beg); \ + register unsigned long _end __asm ("r1") = (unsigned long) (end); \ + register unsigned long _xtr __asm ("r2") = 0; \ + register unsigned long _scno __asm ("r8") = 244; \ + __asm __volatile ("trap_s 0 ; sys_cache_sync" \ + : "=r" (_beg) \ + : "0" (_beg), "r" (_end), "r" (_xtr), "r" (_scno)); \ +} -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] [ARC] Clear the instruction cache using syscalls. 2018-04-06 9:00 ` [PATCH 5/5] [ARC] Clear the instruction cache using syscalls Claudiu Zissulescu @ 2018-04-27 21:44 ` Andrew Burgess 2018-04-30 13:34 ` Claudiu Zissulescu 0 siblings, 1 reply; 16+ messages in thread From: Andrew Burgess @ 2018-04-27 21:44 UTC (permalink / raw) To: Claudiu Zissulescu; +Cc: gcc-patches, Francois.Bedard * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:14 +0200]: > Clear the instruction cache from `beg' to `end'. This makes an inline > system call to SYS_cacheflush. > > gcc/ > 2017-03-28 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/linux.h (CLEAR_INSN_CACHE): Define. Looks good. Thanks, Andrew > --- > gcc/config/arc/linux.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h > index 4e87dfe..96d548e 100644 > --- a/gcc/config/arc/linux.h > +++ b/gcc/config/arc/linux.h > @@ -109,3 +109,17 @@ along with GCC; see the file COPYING3. If not see > /* Build attribute: procedure call standard. */ > #undef ATTRIBUTE_PCS > #define ATTRIBUTE_PCS 3 > + > +/* Clear the instruction cache from `beg' to `end'. This makes an > + inline system call to SYS_cacheflush. */ > +#undef CLEAR_INSN_CACHE > +#define CLEAR_INSN_CACHE(beg, end) \ > +{ \ > + register unsigned long _beg __asm ("r0") = (unsigned long) (beg); \ > + register unsigned long _end __asm ("r1") = (unsigned long) (end); \ > + register unsigned long _xtr __asm ("r2") = 0; \ > + register unsigned long _scno __asm ("r8") = 244; \ > + __asm __volatile ("trap_s 0 ; sys_cache_sync" \ > + : "=r" (_beg) \ > + : "0" (_beg), "r" (_end), "r" (_xtr), "r" (_scno)); \ > +} > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 5/5] [ARC] Clear the instruction cache using syscalls. 2018-04-27 21:44 ` Andrew Burgess @ 2018-04-30 13:34 ` Claudiu Zissulescu 0 siblings, 0 replies; 16+ messages in thread From: Claudiu Zissulescu @ 2018-04-30 13:34 UTC (permalink / raw) To: Andrew Burgess; +Cc: gcc-patches, Francois.Bedard committed. Thank you for your review, Claudiu ________________________________________ From: Andrew Burgess [andrew.burgess@embecosm.com] Sent: Friday, April 27, 2018 11:40 PM To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com Subject: Re: [PATCH 5/5] [ARC] Clear the instruction cache using syscalls. * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2018-04-06 11:00:14 +0200]: > Clear the instruction cache from `beg' to `end'. This makes an inline > system call to SYS_cacheflush. > > gcc/ > 2017-03-28 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/linux.h (CLEAR_INSN_CACHE): Define. Looks good. Thanks, Andrew > --- > gcc/config/arc/linux.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h > index 4e87dfe..96d548e 100644 > --- a/gcc/config/arc/linux.h > +++ b/gcc/config/arc/linux.h > @@ -109,3 +109,17 @@ along with GCC; see the file COPYING3. If not see > /* Build attribute: procedure call standard. */ > #undef ATTRIBUTE_PCS > #define ATTRIBUTE_PCS 3 > + > +/* Clear the instruction cache from `beg' to `end'. This makes an > + inline system call to SYS_cacheflush. */ > +#undef CLEAR_INSN_CACHE > +#define CLEAR_INSN_CACHE(beg, end) \ > +{ \ > + register unsigned long _beg __asm ("r0") = (unsigned long) (beg); \ > + register unsigned long _end __asm ("r1") = (unsigned long) (end); \ > + register unsigned long _xtr __asm ("r2") = 0; \ > + register unsigned long _scno __asm ("r8") = 244; \ > + __asm __volatile ("trap_s 0 ; sys_cache_sync" \ > + : "=r" (_beg) \ > + : "0" (_beg), "r" (_end), "r" (_xtr), "r" (_scno)); \ > +} > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-04-30 13:18 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-04-06 9:00 [PATCH 0/5] [ARC] General fixes Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 1/5] [ARC] Update sleep builtin Claudiu Zissulescu 2018-04-18 17:51 ` Andrew Burgess 2018-04-23 9:57 ` Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 2/5] [ARC] Fix FLS, SETI patterns Claudiu Zissulescu 2018-04-18 17:57 ` Andrew Burgess 2018-04-23 10:34 ` Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 4/5] [ARC] Cleanup sdata handling Claudiu Zissulescu 2018-04-27 21:40 ` Andrew Burgess 2018-04-30 13:18 ` Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 3/5] [ARC] Update movhi and movdi patterns Claudiu Zissulescu 2018-04-27 21:39 ` Andrew Burgess 2018-04-30 13:17 ` Claudiu Zissulescu 2018-04-06 9:00 ` [PATCH 5/5] [ARC] Clear the instruction cache using syscalls Claudiu Zissulescu 2018-04-27 21:44 ` Andrew Burgess 2018-04-30 13:34 ` Claudiu Zissulescu
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