From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19040 invoked by alias); 6 Apr 2018 09:00:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 18677 invoked by uid 89); 6 Apr 2018 09:00:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: smtprelay.synopsys.com Received: from smtprelay.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Apr 2018 09:00:34 +0000 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 9CAB424E0B6A; Fri, 6 Apr 2018 02:00:29 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 3DFA63EE9; Fri, 6 Apr 2018 02:00:29 -0700 (PDT) Received: from US01WEHTC2.internal.synopsys.com (us01wehtc2.internal.synopsys.com [10.12.239.237]) by mailhost.synopsys.com (Postfix) with ESMTP id 25C393EE8; Fri, 6 Apr 2018 02:00:29 -0700 (PDT) Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by US01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 6 Apr 2018 02:00:28 -0700 Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.106) by IN01WEHTCA.internal.synopsys.com (10.144.199.103) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 6 Apr 2018 14:30:27 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCB.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 6 Apr 2018 14:30:27 +0530 From: Claudiu Zissulescu To: CC: , , , Claudiu Zissulescu Subject: [PATCH 3/5] [ARC] Update movhi and movdi patterns. Date: Fri, 06 Apr 2018 09:00:00 -0000 Message-ID: <1523005214-1611-4-git-send-email-claziss@synopsys.com> In-Reply-To: <1523005214-1611-1-git-send-email-claziss@synopsys.com> References: <1523005214-1611-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2018-04/txt/msg00297.txt.bz2 From: Claudiu Zissulescu Allow signed 6-bit short immediates into st[d] instructions. 2017-10-19 Claudiu Zissulescu * config/arc/arc.c (arc_split_move): Allow signed 6-bit constants as source of std instructions. * config/arc/arc.md (movsi_insn): Update pattern predicate to allow 6-bit constants as source for store instructions. (movdi_insn): Update instruction pattern to allow 6-bit constants as source for store instructions. testsuite/ 2017-10-19 Claudiu Zissulescu * gcc.target/arc/store-merge-1.c: New test. * gcc.target/arc/add_n-combine.c: Update test. --- gcc/config/arc/arc.c | 3 ++- gcc/config/arc/arc.md | 25 +++++++++++++------------ gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +- gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++ 4 files changed, 33 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 47d3ba4..2ccdce8 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands) if (TARGET_LL64 && ((memory_operand (operands[0], mode) - && even_register_operand (operands[1], mode)) + && (even_register_operand (operands[1], mode) + || satisfies_constraint_Cm3 (operands[1]))) || (memory_operand (operands[1], mode) && even_register_operand (operands[0], mode)))) { diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ffd9d5b..0fc7aba 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow" /* Don't use a LIMM that we could load with a single insn - we loose delay-slot filling opportunities. */ && !satisfies_constraint_I (operands[1]) - && satisfies_constraint_Usc (operands[0]))" + && satisfies_constraint_Usc (operands[0])) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], SImode))" "@ mov%? %0,%1%& ;0 mov%? %0,%1%& ;1 @@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow" ") (define_insn_and_split "*movdi_insn" - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] "register_operand (operands[0], DImode) - || register_operand (operands[1], DImode)" + || register_operand (operands[1], DImode) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], DImode))" "* { switch (which_alternative) @@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow" case 2: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[1], DImode) + && even_register_operand (operands[0], DImode)) return \"ldd%U1%V1 %0,%1%&\"; return \"#\"; case 3: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[0], DImode) + && (even_register_operand (operands[1], DImode) + || satisfies_constraint_Cm3 (operands[1]))) return \"std%U0%V0 %1,%0\"; return \"#\"; } diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c index db6454f..cd32ed3 100644 --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c @@ -45,4 +45,4 @@ void f() { a(at3.bn[bu]); } -/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ +/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c new file mode 100644 index 0000000..4bb8dcb --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* This tests checks if we use st w6,[reg] format. */ + +typedef struct { + unsigned long __val[2]; +} sigset_t; + +int sigemptyset2 (sigset_t *set) +{ + set->__val[0] = 0; + set->__val[1] = 0; + return 0; +} + +/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */ -- 1.9.1