* Re: [PATCH] RTEMS: Add LEON3/SPARC multilibs
2013-09-19 8:50 ` Eric Botcazou
2013-09-19 8:57 ` Sebastian Huber
@ 2013-11-19 12:42 ` Sebastian Huber
2013-11-23 9:48 ` Eric Botcazou
1 sibling, 1 reply; 10+ messages in thread
From: Sebastian Huber @ 2013-11-19 12:42 UTC (permalink / raw)
To: gcc-patches; +Cc: Eric Botcazou, Daniel Hellstrom, Joel Sherrill
[-- Attachment #1: Type: text/plain, Size: 3330 bytes --]
Hello Eric,
On 2013-09-19 09:23, Eric Botcazou wrote:
>> I don't expect that this will be back ported to GCC 4.8. You also need
>> >Binutils 2.24 for this.
>From a SPARC maintainership viewpoint, I'd think that this is backportable for
> the upcoming 4.8.2 release, and the patches are essentially SPARC-specific,
> but perhaps the RMs are of a different opinion here.
I back ported your list of changes from mainline to GCC 4.8. See the attached
patches. In addition to your proposed changes I had to add
2013-04-10 Steven Bosscher <steven@gcc.gnu.org>
* config/sparc/sparc.c: Include tree-pass.h.
(TARGET_MACHINE_DEPENDENT_REORG): Do not redefine.
(sparc_reorg): Rename to sparc_do_work_around_errata. Move to
head of file. Change return type. Split off gate function.
(sparc_gate_work_around_errata): New function.
(pass_work_around_errata): New pass definition.
(insert_pass_work_around_errata) New pass insert definition to
insert pass_work_around_errata just after delayed-branch scheduling.
(sparc_option_override): Insert the pass.
* config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence.
This was necessary for
2013-07-22 Eric Botcazou <ebotcazou@adacore.com>
* config.gcc (sparc*-*-*): Accept leon3 processor.
(sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.
* doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.
* config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.
* config/sparc/sparc.opt (enum processor_type): Add leon3.
(mfix-ut699): Adjust comment.
* config/sparc/sparc.h (TARGET_CPU_leon3): New define.
(CPP_CPU32_DEFAULT_SPEC): Add leon3 support.
(CPP_CPU_SPEC): Likewise.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc.c (leon3_cost): New constant.
(sparc_option_override): Add leon3 support.
(mem_ref): New function.
(sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.
(sparc_do_work_around_errata): Look into the instruction in the delay
slot and adjust accordingly. Add fix for the data cache nullify issues
of the UT699. Change insertion position for the NOP.
* config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.
(leon3_load): New reservation.
(leon_store): Bump latency to 2.
(grfpu): New automaton.
(grfpu_alu): New unit.
(grfpu_ds): Likewise.
(leon_fp_alu): Adjust.
(leon_fp_mult): Delete.
(leon_fp_div): Split into leon_fp_divs and leon_fp_divd.
(leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.
* config/sparc/sparc.md (cpu): Add leon3.
* config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.
(swapsi): Likewise.
(atomic_test_and_set): Likewise.
(ldstub): Likewise.
I cannot judge if this was good or bad. I can only perform mechanical changes
since I don't know how the compiler works.
I run the GCC test suite on the GDB SIS with RTEMS, but its hard for me to
interpret the results. I think there are no new test failures due to the back
ports.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.huber@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
[-- Attachment #2: 0001-SPARC-GCC-4.8-mfix-ut699-changes.patch --]
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From 1d85b001eb4bdf2076638f17353d6074c3e3f81c Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 28 May 2013 07:26:35 +0000
Subject: [PATCH 1/6] SPARC, GCC 4.8: -mfix-ut699 changes
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
* builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
mode if the instruction isn't available in the original mode.
* config/sparc/sparc.opt (mfix-ut699): New option.
* config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
(divdf3): Turn into expander.
(divdf3_nofix): New insn.
(divdf3_fix): Likewise.
(divsf3): Disable if -mfix-ut699.
(sqrtdf2): Turn into expander.
(sqrtdf2_nofix): New insn.
(sqrtdf2_fix): Likewise.
(sqrtsf2): Disable if -mfix-ut699.
---
gcc/builtins.c | 8 ++++++--
gcc/config/sparc/sparc.md | 42 +++++++++++++++++++++++++++++++++++++-----
gcc/config/sparc/sparc.opt | 4 ++++
gcc/doc/invoke.texi | 7 ++++++-
4 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/gcc/builtins.c b/gcc/builtins.c
index e3c32a9..c977df0 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -1958,6 +1958,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
tree fndecl = get_callee_fndecl (exp);
enum machine_mode mode;
bool errno_set = false;
+ bool try_widening = false;
tree arg;
if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))
@@ -1969,6 +1970,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
{
CASE_FLT_FN (BUILT_IN_SQRT):
errno_set = ! tree_expr_nonnegative_p (arg);
+ try_widening = true;
builtin_optab = sqrt_optab;
break;
CASE_FLT_FN (BUILT_IN_EXP):
@@ -2025,8 +2027,10 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
if (! flag_errno_math || ! HONOR_NANS (mode))
errno_set = false;
- /* Before working hard, check whether the instruction is available. */
- if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing
+ /* Before working hard, check whether the instruction is available, but try
+ to widen the mode for specific operations. */
+ if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing
+ || (try_widening && !excess_precision_type (TREE_TYPE (exp))))
&& (!errno_set || !optimize_insn_for_size_p ()))
{
rtx result = gen_reg_rtx (mode);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index b60af43..568d7dc 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -5548,7 +5548,7 @@
[(set (match_operand:DF 0 "register_operand" "=e")
(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
(float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
- "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
+ "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
"fsmuld\t%1, %2, %0"
[(set_attr "type" "fpmul")
(set_attr "fptype" "double")])
@@ -5577,20 +5577,37 @@
"fdivq\t%1, %2, %0"
[(set_attr "type" "fpdivd")])
-(define_insn "divdf3"
+(define_expand "divdf3"
[(set (match_operand:DF 0 "register_operand" "=e")
(div:DF (match_operand:DF 1 "register_operand" "e")
(match_operand:DF 2 "register_operand" "e")))]
"TARGET_FPU"
+ "")
+
+(define_insn "*divdf3_nofix"
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (div:DF (match_operand:DF 1 "register_operand" "e")
+ (match_operand:DF 2 "register_operand" "e")))]
+ "TARGET_FPU && !sparc_fix_ut699"
"fdivd\t%1, %2, %0"
[(set_attr "type" "fpdivd")
(set_attr "fptype" "double")])
+(define_insn "*divdf3_fix"
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (div:DF (match_operand:DF 1 "register_operand" "e")
+ (match_operand:DF 2 "register_operand" "e")))]
+ "TARGET_FPU && sparc_fix_ut699"
+ "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
+ [(set_attr "type" "fpdivd")
+ (set_attr "fptype" "double")
+ (set_attr "length" "2")])
+
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_FPU"
+ "TARGET_FPU && !sparc_fix_ut699"
"fdivs\t%1, %2, %0"
[(set_attr "type" "fpdivs")])
@@ -5791,18 +5808,33 @@
"fsqrtq\t%1, %0"
[(set_attr "type" "fpsqrtd")])
-(define_insn "sqrtdf2"
+(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=e")
(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
"TARGET_FPU"
+ "")
+
+(define_insn "*sqrtdf2_nofix"
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
+ "TARGET_FPU && !sparc_fix_ut699"
"fsqrtd\t%1, %0"
[(set_attr "type" "fpsqrtd")
(set_attr "fptype" "double")])
+(define_insn "*sqrtdf2_fix"
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
+ "TARGET_FPU && sparc_fix_ut699"
+ "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
+ [(set_attr "type" "fpsqrtd")
+ (set_attr "fptype" "double")
+ (set_attr "length" "2")])
+
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_FPU"
+ "TARGET_FPU && !sparc_fix_ut699"
"fsqrts\t%1, %0"
[(set_attr "type" "fpsqrts")])
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 764c652..3b50c6c 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -201,6 +201,10 @@ Target Report RejectNegative Var(sparc_fix_at697f)
Enable workaround for single erratum of AT697F processor
(corresponding to erratum #13 of AT697E processor)
+mfix-ut699
+Target Report RejectNegative Var(sparc_fix_ut699)
+Enable workarounds for the FP errata of the UT699 processor
+
Mask(LONG_DOUBLE_128)
;; Use 128-bit long double
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3b0ab91..5e3265b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -928,7 +928,7 @@ See RS/6000 and PowerPC Options.
-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
-mcbcond -mno-cbcond @gol
-mfmaf -mno-fmaf -mpopc -mno-popc @gol
--mfix-at697f}
+-mfix-at697f -mfix-ut699}
@emph{SPU Options}
@gccoptlist{-mwarn-reloc -merror-reloc @gol
@@ -19289,6 +19289,11 @@ later.
@opindex mfix-at697f
Enable the documented workaround for the single erratum of the Atmel AT697F
processor (which corresponds to erratum #13 of the AT697E processor).
+
+@item -mfix-ut699
+@opindex mfix-ut699
+Enable the documented workarounds for the floating-point errata of the UT699
+processor.
@end table
These @samp{-m} options are supported in addition to the above
--
1.7.7
[-- Attachment #3: 0002-SPARC-GCC-4.8-Errata-changes.patch --]
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From a50e2aa7ac23d6ba010751318501c23ed7485f10 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Wed, 10 Apr 2013 21:03:44 +0000
Subject: [PATCH 2/6] SPARC, GCC 4.8: Errata changes
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-04-10 Steven Bosscher <steven@gcc.gnu.org>
* config/sparc/sparc.c: Include tree-pass.h.
(TARGET_MACHINE_DEPENDENT_REORG): Do not redefine.
(sparc_reorg): Rename to sparc_do_work_around_errata. Move to
head of file. Change return type. Split off gate function.
(sparc_gate_work_around_errata): New function.
(pass_work_around_errata): New pass definition.
(insert_pass_work_around_errata) New pass insert definition to
insert pass_work_around_errata just after delayed-branch scheduling.
(sparc_option_override): Insert the pass.
* config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence.
---
gcc/config/sparc/sparc.c | 243 ++++++++++++++++++++++++++--------------------
gcc/config/sparc/t-sparc | 2 +-
2 files changed, 139 insertions(+), 106 deletions(-)
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 7e87b47..4f81b83 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -52,6 +52,7 @@ along with GCC; see the file COPYING3. If not see
#include "params.h"
#include "df.h"
#include "opts.h"
+#include "tree-pass.h"
/* Processor costs */
@@ -538,7 +539,6 @@ static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree);
static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
HOST_WIDE_INT, const_tree);
-static void sparc_reorg (void);
static struct machine_function * sparc_init_machine_status (void);
static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
static rtx sparc_tls_get_addr (void);
@@ -680,9 +680,6 @@ char sparc_hard_reg_printed[8];
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
-
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS sparc_rtx_costs
#undef TARGET_ADDRESS_COST
@@ -804,6 +801,136 @@ char sparc_hard_reg_printed[8];
struct gcc_target targetm = TARGET_INITIALIZER;
+/* We use a machine specific pass to enable workarounds for errata.
+ We need to have the (essentially) final form of the insn stream in order
+ to properly detect the various hazards. Therefore, this machine specific
+ pass runs as late as possible. The pass is inserted in the pass pipeline
+ at the end of sparc_options_override. */
+
+static bool
+sparc_gate_work_around_errata (void)
+{
+ /* The only erratum we handle for now is that of the AT697F processor. */
+ return sparc_fix_at697f != 0;
+}
+
+static unsigned int
+sparc_do_work_around_errata (void)
+{
+ rtx insn, next;
+
+ /* Now look for specific patterns in the insn stream. */
+ for (insn = get_insns (); insn; insn = next)
+ {
+ bool insert_nop = false;
+ rtx set;
+
+ /* Look for a single-word load into an odd-numbered FP register. */
+ if (NONJUMP_INSN_P (insn)
+ && (set = single_set (insn)) != NULL_RTX
+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
+ && MEM_P (SET_SRC (set))
+ && REG_P (SET_DEST (set))
+ && REGNO (SET_DEST (set)) > 31
+ && REGNO (SET_DEST (set)) % 2 != 0)
+ {
+ /* The wrong dependency is on the enclosing double register. */
+ unsigned int x = REGNO (SET_DEST (set)) - 1;
+ unsigned int src1, src2, dest;
+ int code;
+
+ /* If the insn has a delay slot, then it cannot be problematic. */
+ next = next_active_insn (insn);
+ if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
+ code = -1;
+ else
+ {
+ extract_insn (next);
+ code = INSN_CODE (next);
+ }
+
+ switch (code)
+ {
+ case CODE_FOR_adddf3:
+ case CODE_FOR_subdf3:
+ case CODE_FOR_muldf3:
+ case CODE_FOR_divdf3:
+ dest = REGNO (recog_data.operand[0]);
+ src1 = REGNO (recog_data.operand[1]);
+ src2 = REGNO (recog_data.operand[2]);
+ if (src1 != src2)
+ {
+ /* Case [1-4]:
+ ld [address], %fx+1
+ FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
+ if ((src1 == x || src2 == x)
+ && (dest == src1 || dest == src2))
+ insert_nop = true;
+ }
+ else
+ {
+ /* Case 5:
+ ld [address], %fx+1
+ FPOPd %fx, %fx, %fx */
+ if (src1 == x
+ && dest == src1
+ && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
+ insert_nop = true;
+ }
+ break;
+
+ case CODE_FOR_sqrtdf2:
+ dest = REGNO (recog_data.operand[0]);
+ src1 = REGNO (recog_data.operand[1]);
+ /* Case 6:
+ ld [address], %fx+1
+ fsqrtd %fx, %fx */
+ if (src1 == x && dest == src1)
+ insert_nop = true;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ next = NEXT_INSN (insn);
+
+ if (insert_nop)
+ emit_insn_after (gen_nop (), insn);
+ }
+ return 0;
+}
+
+struct rtl_opt_pass pass_work_around_errata =
+{
+ {
+ RTL_PASS,
+ "errata", /* name */
+ OPTGROUP_NONE, /* optinfo_flags */
+ sparc_gate_work_around_errata, /* gate */
+ sparc_do_work_around_errata, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_MACH_DEP, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_verify_rtl_sharing, /* todo_flags_finish */
+ }
+};
+
+struct register_pass_info insert_pass_work_around_errata =
+{
+ &pass_work_around_errata.pass, /* pass */
+ "dbr", /* reference_pass_name */
+ 1, /* ref_pass_instance_number */
+ PASS_POS_INSERT_AFTER /* po_op */
+};
+
+/* Helpers for TARGET_DEBUG_OPTIONS. */
static void
dump_target_flag_bits (const int flags)
{
@@ -1241,6 +1368,13 @@ sparc_option_override (void)
pessimizes for double floating-point registers. */
if (!global_options_set.x_flag_ira_share_save_slots)
flag_ira_share_save_slots = 0;
+
+ /* We register a machine specific pass to work around errata, if any.
+ The pass mut be scheduled as late as possible so that we have the
+ (essentially) final form of the insn stream to work on.
+ Registering the pass must be done at start up. It's convenient to
+ do it here. */
+ register_pass (&insert_pass_work_around_errata);
}
\f
/* Miscellaneous utilities. */
@@ -10897,107 +11031,6 @@ sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
return (vcall_offset >= -32768 || ! fixed_regs[5]);
}
-/* We use the machine specific reorg pass to enable workarounds for errata. */
-
-static void
-sparc_reorg (void)
-{
- rtx insn, next;
-
- /* The only erratum we handle for now is that of the AT697F processor. */
- if (!sparc_fix_at697f)
- return;
-
- /* We need to have the (essentially) final form of the insn stream in order
- to properly detect the various hazards. Run delay slot scheduling. */
- if (optimize > 0 && flag_delayed_branch)
- {
- cleanup_barriers ();
- dbr_schedule (get_insns ());
- }
-
- /* Now look for specific patterns in the insn stream. */
- for (insn = get_insns (); insn; insn = next)
- {
- bool insert_nop = false;
- rtx set;
-
- /* Look for a single-word load into an odd-numbered FP register. */
- if (NONJUMP_INSN_P (insn)
- && (set = single_set (insn)) != NULL_RTX
- && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
- && MEM_P (SET_SRC (set))
- && REG_P (SET_DEST (set))
- && REGNO (SET_DEST (set)) > 31
- && REGNO (SET_DEST (set)) % 2 != 0)
- {
- /* The wrong dependency is on the enclosing double register. */
- unsigned int x = REGNO (SET_DEST (set)) - 1;
- unsigned int src1, src2, dest;
- int code;
-
- /* If the insn has a delay slot, then it cannot be problematic. */
- next = next_active_insn (insn);
- if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
- code = -1;
- else
- {
- extract_insn (next);
- code = INSN_CODE (next);
- }
-
- switch (code)
- {
- case CODE_FOR_adddf3:
- case CODE_FOR_subdf3:
- case CODE_FOR_muldf3:
- case CODE_FOR_divdf3:
- dest = REGNO (recog_data.operand[0]);
- src1 = REGNO (recog_data.operand[1]);
- src2 = REGNO (recog_data.operand[2]);
- if (src1 != src2)
- {
- /* Case [1-4]:
- ld [address], %fx+1
- FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
- if ((src1 == x || src2 == x)
- && (dest == src1 || dest == src2))
- insert_nop = true;
- }
- else
- {
- /* Case 5:
- ld [address], %fx+1
- FPOPd %fx, %fx, %fx */
- if (src1 == x
- && dest == src1
- && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
- insert_nop = true;
- }
- break;
-
- case CODE_FOR_sqrtdf2:
- dest = REGNO (recog_data.operand[0]);
- src1 = REGNO (recog_data.operand[1]);
- /* Case 6:
- ld [address], %fx+1
- fsqrtd %fx, %fx */
- if (src1 == x && dest == src1)
- insert_nop = true;
- break;
-
- default:
- break;
- }
- }
- else
- next = NEXT_INSN (insn);
-
- if (insert_nop)
- emit_insn_after (gen_nop (), insn);
- }
-}
-
/* How to allocate a 'struct machine_function'. */
static struct machine_function *
diff --git a/gcc/config/sparc/t-sparc b/gcc/config/sparc/t-sparc
index d7b17fb..664f4a4 100644
--- a/gcc/config/sparc/t-sparc
+++ b/gcc/config/sparc/t-sparc
@@ -23,7 +23,7 @@ sparc.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \
$(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \
$(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \
- $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) \
+ $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) $(TREE_PASS_H) \
langhooks.h reload.h $(PARAMS_H) $(DF_H) $(OPTS_H) \
gt-sparc.h
--
1.7.7
[-- Attachment #4: 0003-SPARC-GCC-4.8-LEON3-support.patch --]
[-- Type: text/x-patch, Size: 18748 bytes --]
From efa4aefefcc771d1f0a3783519fc7c496d9a1e4b Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Mon, 22 Jul 2013 21:41:44 +0000
Subject: [PATCH 3/6] SPARC, GCC 4.8: LEON3 support
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-07-22 Eric Botcazou <ebotcazou@adacore.com>
* config.gcc (sparc*-*-*): Accept leon3 processor.
(sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.
* doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.
* config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.
* config/sparc/sparc.opt (enum processor_type): Add leon3.
(mfix-ut699): Adjust comment.
* config/sparc/sparc.h (TARGET_CPU_leon3): New define.
(CPP_CPU32_DEFAULT_SPEC): Add leon3 support.
(CPP_CPU_SPEC): Likewise.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc.c (leon3_cost): New constant.
(sparc_option_override): Add leon3 support.
(mem_ref): New function.
(sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.
(sparc_do_work_around_errata): Look into the instruction in the delay
slot and adjust accordingly. Add fix for the data cache nullify issues
of the UT699. Change insertion position for the NOP.
* config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.
(leon3_load): New reservation.
(leon_store): Bump latency to 2.
(grfpu): New automaton.
(grfpu_alu): New unit.
(grfpu_ds): Likewise.
(leon_fp_alu): Adjust.
(leon_fp_mult): Delete.
(leon_fp_div): Split into leon_fp_divs and leon_fp_divd.
(leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.
* config/sparc/sparc.md (cpu): Add leon3.
* config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.
(swapsi): Likewise.
(atomic_test_and_set): Likewise.
(ldstub): Likewise.
---
gcc/config.gcc | 22 ++++---
gcc/config/sparc/leon.md | 60 +++++++++++---------
gcc/config/sparc/sparc-opts.h | 1 +
gcc/config/sparc/sparc.c | 123 +++++++++++++++++++++++++++++++++++++----
gcc/config/sparc/sparc.h | 36 +++++++-----
gcc/config/sparc/sparc.md | 3 +-
gcc/config/sparc/sparc.opt | 5 +-
gcc/config/sparc/sync.md | 8 +-
gcc/doc/invoke.texi | 4 +-
9 files changed, 190 insertions(+), 72 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 92d57dd..d6cafa7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3587,7 +3587,7 @@ case "${target}" in
case ${val} in
"" | sparc | sparcv9 | sparc64 \
| v7 | cypress \
- | v8 | supersparc | hypersparc | leon \
+ | v8 | supersparc | hypersparc | leon | leon3 \
| sparclite | f930 | f934 | sparclite86x \
| sparclet | tsc701 \
| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
@@ -3745,15 +3745,6 @@ case ${target} in
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
- sparc-leon*-*)
- if test x$with_tune = x ; then
- with_tune=leon;
- fi
-
- # The SPARC port checks this value at compile-time.
- target_cpu_default2="TARGET_CPU_$with_cpu"
- ;;
-
sparc*-*-*)
# Some standard aliases.
case x$with_cpu in
@@ -3765,6 +3756,17 @@ case ${target} in
;;
esac
+ if test x$with_tune = x ; then
+ case ${target} in
+ *-leon-*)
+ with_tune=leon
+ ;;
+ *-leon[3-9]*)
+ with_tune=leon3
+ ;;
+ esac
+ fi
+
# The SPARC port checks this value at compile-time.
target_cpu_default2="TARGET_CPU_$with_cpu"
;;
diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md
index 6081507..b511397 100644
--- a/gcc/config/sparc/leon.md
+++ b/gcc/config/sparc/leon.md
@@ -17,40 +17,48 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; Leon is a single-issue processor.
(define_automaton "leon")
-(define_cpu_unit "leon_memory, leon_fpalu" "leon")
-(define_cpu_unit "leon_fpmds" "leon")
-(define_cpu_unit "write_buf" "leon")
+(define_cpu_unit "leon_memory" "leon")
(define_insn_reservation "leon_load" 1
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "load,sload,fpload"))
+ (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))
"leon_memory")
-(define_insn_reservation "leon_store" 1
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "store,fpstore"))
- "leon_memory+write_buf")
-
-(define_insn_reservation "leon_fp_alu" 1
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "fp,fpmove"))
- "leon_fpalu, nothing")
+;; Use a double reservation to work around the load pipeline hazard on UT699.
+(define_insn_reservation "leon3_load" 1
+ (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
+ "leon_memory*2")
-(define_insn_reservation "leon_fp_mult" 1
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "fpmul"))
- "leon_fpmds, nothing")
+(define_insn_reservation "leon_store" 2
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
+ "leon_memory*2")
-(define_insn_reservation "leon_fp_div" 16
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "fpdivs,fpdivd"))
- "leon_fpmds, nothing*15")
+;; This describes Gaisler Research's FPU
-(define_insn_reservation "leon_fp_sqrt" 23
- (and (eq_attr "cpu" "leon")
- (eq_attr "type" "fpsqrts,fpsqrtd"))
- "leon_fpmds, nothing*21")
+(define_automaton "grfpu")
+(define_cpu_unit "grfpu_alu" "grfpu")
+(define_cpu_unit "grfpu_ds" "grfpu")
+
+(define_insn_reservation "leon_fp_alu" 4
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
+ "grfpu_alu, nothing*3")
+
+(define_insn_reservation "leon_fp_divs" 16
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
+ "grfpu_ds*14, nothing*2")
+
+(define_insn_reservation "leon_fp_divd" 17
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
+ "grfpu_ds*15, nothing*2")
+
+(define_insn_reservation "leon_fp_sqrts" 24
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
+ "grfpu_ds*22, nothing*2")
+
+(define_insn_reservation "leon_fp_sqrtd" 25
+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
+ "grfpu_ds*23, nothing*2")
diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h
index 7279177..b5e9761 100644
--- a/gcc/config/sparc/sparc-opts.h
+++ b/gcc/config/sparc/sparc-opts.h
@@ -30,6 +30,7 @@ enum processor_type {
PROCESSOR_SUPERSPARC,
PROCESSOR_HYPERSPARC,
PROCESSOR_LEON,
+ PROCESSOR_LEON3,
PROCESSOR_SPARCLITE,
PROCESSOR_F930,
PROCESSOR_F934,
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 4f81b83..f602a0b 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -227,6 +227,30 @@ struct processor_costs leon_costs = {
};
static const
+struct processor_costs leon3_costs = {
+ COSTS_N_INSNS (1), /* int load */
+ COSTS_N_INSNS (1), /* int signed load */
+ COSTS_N_INSNS (1), /* int zeroed load */
+ COSTS_N_INSNS (1), /* float load */
+ COSTS_N_INSNS (1), /* fmov, fneg, fabs */
+ COSTS_N_INSNS (1), /* fadd, fsub */
+ COSTS_N_INSNS (1), /* fcmp */
+ COSTS_N_INSNS (1), /* fmov, fmovr */
+ COSTS_N_INSNS (1), /* fmul */
+ COSTS_N_INSNS (14), /* fdivs */
+ COSTS_N_INSNS (15), /* fdivd */
+ COSTS_N_INSNS (22), /* fsqrts */
+ COSTS_N_INSNS (23), /* fsqrtd */
+ COSTS_N_INSNS (5), /* imul */
+ COSTS_N_INSNS (5), /* imulX */
+ 0, /* imul bit factor */
+ COSTS_N_INSNS (35), /* idiv */
+ COSTS_N_INSNS (35), /* idivX */
+ COSTS_N_INSNS (1), /* movcc/movr */
+ 0, /* shift penalty */
+};
+
+static const
struct processor_costs sparclet_costs = {
COSTS_N_INSNS (3), /* int load */
COSTS_N_INSNS (3), /* int signed load */
@@ -801,17 +825,31 @@ char sparc_hard_reg_printed[8];
struct gcc_target targetm = TARGET_INITIALIZER;
+/* Return the memory reference contained in X if any, zero otherwise. */
+
+static rtx
+mem_ref (rtx x)
+{
+ if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)
+ x = XEXP (x, 0);
+
+ if (MEM_P (x))
+ return x;
+
+ return NULL_RTX;
+}
+
/* We use a machine specific pass to enable workarounds for errata.
We need to have the (essentially) final form of the insn stream in order
to properly detect the various hazards. Therefore, this machine specific
pass runs as late as possible. The pass is inserted in the pass pipeline
- at the end of sparc_options_override. */
+ at the end of sparc_option_override. */
static bool
sparc_gate_work_around_errata (void)
{
- /* The only erratum we handle for now is that of the AT697F processor. */
- return sparc_fix_at697f != 0;
+ /* The only errata we handle are those of the AT697F and UT699. */
+ return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
}
static unsigned int
@@ -819,14 +857,22 @@ sparc_do_work_around_errata (void)
{
rtx insn, next;
+ /* Force all instructions to be split into their final form. */
+ split_all_insns_noflow ();
+
/* Now look for specific patterns in the insn stream. */
for (insn = get_insns (); insn; insn = next)
{
bool insert_nop = false;
rtx set;
+ /* Look into the instruction in a delay slot. */
+ if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
+ insn = XVECEXP (PATTERN (insn), 0, 1);
+
/* Look for a single-word load into an odd-numbered FP register. */
- if (NONJUMP_INSN_P (insn)
+ if (sparc_fix_at697f
+ && NONJUMP_INSN_P (insn)
&& (set = single_set (insn)) != NULL_RTX
&& GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
&& MEM_P (SET_SRC (set))
@@ -841,13 +887,13 @@ sparc_do_work_around_errata (void)
/* If the insn has a delay slot, then it cannot be problematic. */
next = next_active_insn (insn);
+ if (!next)
+ break;
if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
- code = -1;
- else
- {
- extract_insn (next);
- code = INSN_CODE (next);
- }
+ continue;
+
+ extract_insn (next);
+ code = INSN_CODE (next);
switch (code)
{
@@ -893,12 +939,60 @@ sparc_do_work_around_errata (void)
break;
}
}
+
+ /* Look for a single-word load into an integer register. */
+ else if (sparc_fix_ut699
+ && NONJUMP_INSN_P (insn)
+ && (set = single_set (insn)) != NULL_RTX
+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
+ && mem_ref (SET_SRC (set)) != NULL_RTX
+ && REG_P (SET_DEST (set))
+ && REGNO (SET_DEST (set)) < 32)
+ {
+ /* There is no problem if the second memory access has a data
+ dependency on the first single-cycle load. */
+ rtx x = SET_DEST (set);
+
+ /* If the insn has a delay slot, then it cannot be problematic. */
+ next = next_active_insn (insn);
+ if (!next)
+ break;
+ if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
+ continue;
+
+ /* Look for a second memory access to/from an integer register. */
+ if ((set = single_set (next)) != NULL_RTX)
+ {
+ rtx src = SET_SRC (set);
+ rtx dest = SET_DEST (set);
+ rtx mem;
+
+ /* LDD is affected. */
+ if ((mem = mem_ref (src)) != NULL_RTX
+ && REG_P (dest)
+ && REGNO (dest) < 32
+ && !reg_mentioned_p (x, XEXP (mem, 0)))
+ insert_nop = true;
+
+ /* STD is *not* affected. */
+ else if ((mem = mem_ref (dest)) != NULL_RTX
+ && GET_MODE_SIZE (GET_MODE (mem)) <= 4
+ && (src == const0_rtx
+ || (REG_P (src)
+ && REGNO (src) < 32
+ && REGNO (src) != REGNO (x)))
+ && !reg_mentioned_p (x, XEXP (mem, 0)))
+ insert_nop = true;
+ }
+ }
+
else
next = NEXT_INSN (insn);
if (insert_nop)
- emit_insn_after (gen_nop (), insn);
+ emit_insn_before (gen_nop (), next);
}
+
return 0;
}
@@ -1015,6 +1109,7 @@ sparc_option_override (void)
{ TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
{ TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
{ TARGET_CPU_leon, PROCESSOR_LEON },
+ { TARGET_CPU_leon3, PROCESSOR_LEON3 },
{ TARGET_CPU_sparclite, PROCESSOR_F930 },
{ TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
{ TARGET_CPU_sparclet, PROCESSOR_TSC701 },
@@ -1029,7 +1124,7 @@ sparc_option_override (void)
};
const struct cpu_default *def;
/* Table of values for -m{cpu,tune}=. This must match the order of
- the PROCESSOR_* enumeration. */
+ the enum processor_type in sparc-opts.h. */
static struct cpu_table {
const char *const name;
const int disable;
@@ -1043,6 +1138,7 @@ sparc_option_override (void)
{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
/* LEON */
{ "leon", MASK_ISA, MASK_V8|MASK_FPU },
+ { "leon3", MASK_ISA, MASK_V8|MASK_FPU },
{ "sparclite", MASK_ISA, MASK_SPARCLITE },
/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
@@ -1291,6 +1387,9 @@ sparc_option_override (void)
case PROCESSOR_LEON:
sparc_costs = &leon_costs;
break;
+ case PROCESSOR_LEON3:
+ sparc_costs = &leon3_costs;
+ break;
case PROCESSOR_SPARCLET:
case PROCESSOR_TSC701:
sparc_costs = &sparclet_costs;
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index c6122c1..202d23c 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -136,21 +136,22 @@ extern enum cmodel sparc_cmodel;
#define TARGET_CPU_supersparc 2
#define TARGET_CPU_hypersparc 3
#define TARGET_CPU_leon 4
-#define TARGET_CPU_sparclite 5
-#define TARGET_CPU_f930 5 /* alias */
-#define TARGET_CPU_f934 5 /* alias */
-#define TARGET_CPU_sparclite86x 6
-#define TARGET_CPU_sparclet 7
-#define TARGET_CPU_tsc701 7 /* alias */
-#define TARGET_CPU_v9 8 /* generic v9 implementation */
-#define TARGET_CPU_sparcv9 8 /* alias */
-#define TARGET_CPU_sparc64 8 /* alias */
-#define TARGET_CPU_ultrasparc 9
-#define TARGET_CPU_ultrasparc3 10
-#define TARGET_CPU_niagara 11
-#define TARGET_CPU_niagara2 12
-#define TARGET_CPU_niagara3 13
-#define TARGET_CPU_niagara4 14
+#define TARGET_CPU_leon3 5
+#define TARGET_CPU_sparclite 6
+#define TARGET_CPU_f930 6 /* alias */
+#define TARGET_CPU_f934 6 /* alias */
+#define TARGET_CPU_sparclite86x 7
+#define TARGET_CPU_sparclet 8
+#define TARGET_CPU_tsc701 8 /* alias */
+#define TARGET_CPU_v9 9 /* generic v9 implementation */
+#define TARGET_CPU_sparcv9 9 /* alias */
+#define TARGET_CPU_sparc64 9 /* alias */
+#define TARGET_CPU_ultrasparc 10
+#define TARGET_CPU_ultrasparc3 11
+#define TARGET_CPU_niagara 12
+#define TARGET_CPU_niagara2 13
+#define TARGET_CPU_niagara3 14
+#define TARGET_CPU_niagara4 15
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
@@ -232,7 +233,8 @@ extern enum cmodel sparc_cmodel;
#define ASM_CPU32_DEFAULT_SPEC ""
#endif
-#if TARGET_CPU_DEFAULT == TARGET_CPU_leon
+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3
#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
#define ASM_CPU32_DEFAULT_SPEC ""
#endif
@@ -282,6 +284,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
%{mcpu=leon:-D__leon__ -D__sparc_v8__} \
+%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
%{mcpu=v9:-D__sparc_v9__} \
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
@@ -330,6 +333,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=supersparc:-Av8} \
%{mcpu=hypersparc:-Av8} \
%{mcpu=leon:-Av8} \
+%{mcpu=leon3:-Av8} \
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 568d7dc..737cff0 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -206,7 +206,7 @@
;; 'f' for all DF/TFmode values, including those that are specific to the v8.
;; Attribute for cpu type.
-;; These must match the values for enum processor_type in sparc.h.
+;; These must match the values of the enum processor_type in sparc-opts.h.
(define_attr "cpu"
"v7,
cypress,
@@ -214,6 +214,7 @@
supersparc,
hypersparc,
leon,
+ leon3,
sparclite,
f930,
f934,
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 3b50c6c..016e699 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -146,6 +146,9 @@ EnumValue
Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
EnumValue
+Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
+
+EnumValue
Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
EnumValue
@@ -203,7 +206,7 @@ Enable workaround for single erratum of AT697F processor
mfix-ut699
Target Report RejectNegative Var(sparc_fix_ut699)
-Enable workarounds for the FP errata of the UT699 processor
+Enable workarounds for the errata of the UT699 processor
Mask(LONG_DOUBLE_128)
;; Use 128-bit long double
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 1c1b977..2f21f81 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -220,7 +220,7 @@
(match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "const_int_operand" "")]
- "TARGET_V8 || TARGET_V9"
+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
{
enum memmodel model = (enum memmodel) INTVAL (operands[3]);
@@ -236,7 +236,7 @@
UNSPECV_SWAP))
(set (match_dup 1)
(match_operand:SI 2 "register_operand" "0"))]
- "TARGET_V8 || TARGET_V9"
+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
"swap\t%1, %0"
[(set_attr "type" "multi")])
@@ -244,7 +244,7 @@
[(match_operand:QI 0 "register_operand" "")
(match_operand:QI 1 "memory_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
- ""
+ "!sparc_fix_ut699"
{
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
rtx ret;
@@ -268,6 +268,6 @@
(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
UNSPECV_LDSTUB))
(set (match_dup 1) (const_int -1))]
- ""
+ "!sparc_fix_ut699"
"ldstub\t%1, %0"
[(set_attr "type" "multi")])
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5e3265b..11b3760 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19292,8 +19292,8 @@ processor (which corresponds to erratum #13 of the AT697E processor).
@item -mfix-ut699
@opindex mfix-ut699
-Enable the documented workarounds for the floating-point errata of the UT699
-processor.
+Enable the documented workarounds for the floating-point errata and the data
+cache nullify errata of the UT699 processor.
@end table
These @samp{-m} options are supported in addition to the above
--
1.7.7
[-- Attachment #5: 0004-SPARC-GCC-4.8-LEON3-documentation.patch --]
[-- Type: text/x-patch, Size: 2735 bytes --]
From 1360311d94063d405c5d63c7ba7a7d6a3b6b73e0 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 23 Jul 2013 18:11:07 +0000
Subject: [PATCH 4/6] SPARC, GCC 4.8: LEON3 documentation
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-07-23 Eric Botcazou <ebotcazou@adacore.com>
* doc/invoke.texi (SPARC Options): Document new leon3 processor value.
---
gcc/doc/invoke.texi | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 11b3760..6b597b0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19133,10 +19133,10 @@ the rules of the ABI@.
Set the instruction set, register set, and instruction scheduling parameters
for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
-@samp{leon}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x},
-@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc},
-@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3},
-and @samp{niagara4}.
+@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934},
+@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
+@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
+@samp{niagara3} and @samp{niagara4}.
Native Solaris and GNU/Linux toolchains also support the value @samp{native},
which selects the best architecture option for the host processor.
@@ -19155,7 +19155,7 @@ implementations.
cypress
@item v8
-supersparc, hypersparc, leon
+supersparc, hypersparc, leon, leon3
@item sparclite
f930, f934, sparclite86x
@@ -19217,10 +19217,11 @@ option @option{-mcpu=@var{cpu_type}} does.
The same values for @option{-mcpu=@var{cpu_type}} can be used for
@option{-mtune=@var{cpu_type}}, but the only useful values are those
that select a particular CPU implementation. Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{f930}, @samp{f934},
-@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3},
-@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. With
-native Solaris and GNU/Linux toolchains, @samp{native} can also be used.
+@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930},
+@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
+@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and
+@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native}
+can also be used.
@item -mv8plus
@itemx -mno-v8plus
--
1.7.7
[-- Attachment #6: 0005-SPARC-GCC-4.8-LEON-and-LEON3-atomic-ops-support.patch --]
[-- Type: text/x-patch, Size: 8826 bytes --]
From 1e40bd5abe3966317d6f38a16e5250f8fbc9934c Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 19 Nov 2013 09:53:02 +0100
Subject: [PATCH 5/6] SPARC, GCC 4.8: LEON and LEON3 atomic ops support
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-08-09 Eric Botcazou <ebotcazou@adacore.com>
* configure.ac: Add GAS check for LEON instructions on SPARC.
* configure: Regenerate.
* config.in: Likewise.
* config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the
sparc*-*-* block.
* config/sparc/sparc.opt (LEON, LEON3): New masks.
* config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG
for LEON or LEON3.
(ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3.
(AS_LEON_FLAG): New macro.
* config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon
and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined.
Deal with LEON and LEON3 for the memory model.
* config/sparc/sync.md (atomic_compare_and_swap<mode>): Enable if LEON3
(atomic_compare_and_swap<mode>_1): Likewise.
(*atomic_compare_and_swap<mode>_1): Likewise.
---
gcc/config.gcc | 15 +++++++++++----
gcc/config.in | 6 ++++++
gcc/config/sparc/sparc.c | 12 +++++++++---
gcc/config/sparc/sparc.h | 12 +++++++++---
gcc/config/sparc/sparc.opt | 6 ++++++
gcc/config/sparc/sync.md | 7 ++++---
gcc/configure | 37 +++++++++++++++++++++++++++++++++++++
gcc/configure.ac | 13 +++++++++++++
8 files changed, 95 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index d6cafa7..5607ed9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2963,11 +2963,18 @@ if test x$with_cpu = x ; then
with_cpu=8540
fi
;;
- sparc-leon*-*)
- with_cpu=v8;
- ;;
sparc*-*-*)
- with_cpu="`echo ${target} | sed 's/-.*$//'`"
+ case ${target} in
+ *-leon-*)
+ with_cpu=leon
+ ;;
+ *-leon[3-9]*)
+ with_cpu=leon3
+ ;;
+ *)
+ with_cpu="`echo ${target} | sed 's/-.*$//'`"
+ ;;
+ esac
;;
esac
diff --git a/gcc/config.in b/gcc/config.in
index 3df6af9..42140c3 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -375,6 +375,12 @@
#endif
+/* Define if your assembler supports LEON instructions. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_LEON
+#endif
+
+
/* Define if the assembler won't complain about a line such as # 0 "" 2. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_LINE_ZERO
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index f602a0b..7dce38c 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1136,9 +1136,8 @@ sparc_option_override (void)
/* TI TMS390Z55 supersparc */
{ "supersparc", MASK_ISA, MASK_V8 },
{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
- /* LEON */
- { "leon", MASK_ISA, MASK_V8|MASK_FPU },
- { "leon3", MASK_ISA, MASK_V8|MASK_FPU },
+ { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
+ { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
{ "sparclite", MASK_ISA, MASK_SPARCLITE },
/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
@@ -1298,6 +1297,9 @@ sparc_option_override (void)
#ifndef HAVE_AS_SPARC4
& ~MASK_CBCOND
#endif
+#ifndef HAVE_AS_LEON
+ & ~(MASK_LEON | MASK_LEON3)
+#endif
);
/* If -mfpu or -mno-fpu was explicitly used, don't override with
@@ -1426,6 +1428,10 @@ sparc_option_override (void)
/* Choose the most relaxed model for the processor. */
else if (TARGET_V9)
sparc_memory_model = SMM_RMO;
+ else if (TARGET_LEON3)
+ sparc_memory_model = SMM_TSO;
+ else if (TARGET_LEON)
+ sparc_memory_model = SMM_SC;
else if (TARGET_V8)
sparc_memory_model = SMM_PSO;
else
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 202d23c..d96c1b6 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -236,7 +236,7 @@ extern enum cmodel sparc_cmodel;
#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
|| TARGET_CPU_DEFAULT == TARGET_CPU_leon3
#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
-#define ASM_CPU32_DEFAULT_SPEC ""
+#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
#endif
#endif
@@ -332,8 +332,8 @@ extern enum cmodel sparc_cmodel;
%{mcpu=v8:-Av8} \
%{mcpu=supersparc:-Av8} \
%{mcpu=hypersparc:-Av8} \
-%{mcpu=leon:-Av8} \
-%{mcpu=leon3:-Av8} \
+%{mcpu=leon:" AS_LEON_FLAG "} \
+%{mcpu=leon3:" AS_LEON_FLAG "} \
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
@@ -1758,6 +1758,12 @@ extern int sparc_indent_opcode;
#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
#endif
+#ifdef HAVE_AS_LEON
+#define AS_LEON_FLAG "-Aleon"
+#else
+#define AS_LEON_FLAG "-Av8"
+#endif
+
/* We use gcc _mcount for profiling. */
#define NO_PROFILE_COUNTERS 0
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 016e699..3ccd54f 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -211,6 +211,12 @@ Enable workarounds for the errata of the UT699 processor
Mask(LONG_DOUBLE_128)
;; Use 128-bit long double
+Mask(LEON)
+;; Generate code for LEON
+
+Mask(LEON3)
+;; Generate code for LEON3
+
Mask(SPARCLITE)
;; Generate code for SPARClite
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 2f21f81..130f521 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -161,7 +161,8 @@
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; mod_s
(match_operand:SI 7 "const_int_operand" "")] ;; mod_f
- "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
+ "(TARGET_V9 || TARGET_LEON3)
+ && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
{
sparc_expand_compare_and_swap (operands);
DONE;
@@ -176,7 +177,7 @@
[(match_operand:I48MODE 2 "register_operand" "")
(match_operand:I48MODE 3 "register_operand" "")]
UNSPECV_CAS))])]
- "TARGET_V9"
+ "TARGET_V9 || TARGET_LEON3"
"")
(define_insn "*atomic_compare_and_swap<mode>_1"
@@ -187,7 +188,7 @@
[(match_operand:I48MODE 2 "register_operand" "r")
(match_operand:I48MODE 3 "register_operand" "0")]
UNSPECV_CAS))]
- "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
+ "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)"
"cas<modesuffix>\t%1, %2, %0"
[(set_attr "type" "multi")])
diff --git a/gcc/configure b/gcc/configure
index ed89d09..4d0f177 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -24263,6 +24263,43 @@ if test $gcc_cv_as_sparc_sparc4 = yes; then
$as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h
fi
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5
+$as_echo_n "checking assembler for LEON instructions... " >&6; }
+if test "${gcc_cv_as_sparc_leon+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ gcc_cv_as_sparc_leon=no
+ if test x$gcc_cv_as != x; then
+ $as_echo '.text
+ .register %g2, #scratch
+ .register %g3, #scratch
+ .align 4
+ smac %g2, %g3, %g1
+ umac %g2, %g3, %g1
+ cas [%g2], %g3, %g1' > conftest.s
+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }
+ then
+ gcc_cv_as_sparc_leon=yes
+ else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+ fi
+ rm -f conftest.o conftest.s
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_leon" >&5
+$as_echo "$gcc_cv_as_sparc_leon" >&6; }
+if test $gcc_cv_as_sparc_leon = yes; then
+
+$as_echo "#define HAVE_AS_LEON 1" >>confdefs.h
+
+fi
;;
i[34567]86-*-* | x86_64-*-*)
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 39d8efb..26abd17 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3611,6 +3611,19 @@ foo:
kasumi_fi_xor %f46, %f48, %f50, %f52],,
[AC_DEFINE(HAVE_AS_SPARC4, 1,
[Define if your assembler supports SPARC4 instructions.])])
+
+ gcc_GAS_CHECK_FEATURE([LEON instructions],
+ gcc_cv_as_sparc_leon,,
+ [-Aleon],
+ [.text
+ .register %g2, #scratch
+ .register %g3, #scratch
+ .align 4
+ smac %g2, %g3, %g1
+ umac %g2, %g3, %g1
+ cas [[%g2]], %g3, %g1],,
+ [AC_DEFINE(HAVE_AS_LEON, 1,
+ [Define if your assembler supports LEON instructions.])])
;;
changequote(,)dnl
--
1.7.7
[-- Attachment #7: 0006-SPARC-GCC-4.8-Add-LEON3-multilibs-for-RTEMS.patch --]
[-- Type: text/x-patch, Size: 969 bytes --]
From cdce11fa563813f7229840aa0038162c229f597b Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 19 Nov 2013 09:53:26 +0100
Subject: [PATCH 6/6] SPARC, GCC 4.8: Add LEON3 multilibs for RTEMS
gcc/ChangeLog
2013-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backport from mainline
2013-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
* config/sparc/t-rtems: Add leon3 multilibs.
---
gcc/config/sparc/t-rtems | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems
index 63d0217..f1a3d84 100644
--- a/gcc/config/sparc/t-rtems
+++ b/gcc/config/sparc/t-rtems
@@ -17,6 +17,6 @@
# <http://www.gnu.org/licenses/>.
#
-MULTILIB_OPTIONS = msoft-float mcpu=v8
-MULTILIB_DIRNAMES = soft v8
+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3
+MULTILIB_DIRNAMES = soft v8 leon3
MULTILIB_MATCHES = msoft-float=mno-fpu
--
1.7.7
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