From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id F3ABD3858425 for ; Fri, 13 Jan 2023 22:04:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F3ABD3858425 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C37DFEC; Fri, 13 Jan 2023 14:05:10 -0800 (PST) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A4A683F71A; Fri, 13 Jan 2023 14:04:27 -0800 (PST) Message-ID: <152afa11-c167-5583-7d5b-4709c5777acf@foss.arm.com> Date: Fri, 13 Jan 2023 22:04:26 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [GCC][PATCH 13/15, v5] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature. Content-Language: en-GB To: "Richard Earnshaw (lists)" , Jakub Jelinek , Srinath Parvathaneni Cc: gcc Patches , Kyrylo Tkachov , Richard.Sandiford@arm.com References: <2b3432d1-587e-4c2e-4297-327ffbe6ad1d@arm.com> From: Richard Earnshaw In-Reply-To: <2b3432d1-587e-4c2e-4297-327ffbe6ad1d@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3488.5 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 13/01/2023 21:58, Richard Earnshaw (lists) via Gcc-patches wrote: > On 13/01/2023 18:02, Jakub Jelinek via Gcc-patches wrote: >> On Fri, Jan 13, 2023 at 05:44:15PM +0000, Srinath Parvathaneni via >> Gcc-patches wrote: >>> Hello, >>> >>> This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo >>> hard-register and also >>> updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" >>> directives accordingly. >>> This patch also adds support to emit ".pacspval" directive when "pac >>> ip, lr, sp" instruction >>> in generated in the assembly. >>> >>> RA_AUTH_CODE register number is 107 and it's dwarf register number is >>> 143. >> >> I'm afraid increasing number of DWARF registers is ABI incompatible >> change. >> E.g. libgcc __frame_state_for function fills in: >> typedef struct frame_state >> { >>    void *cfa; >>    void *eh_ptr; >>    long cfa_offset; >>    long args_size; >>    long reg_or_offset[PRE_GCC3_DWARF_FRAME_REGISTERS+1]; >>    unsigned short cfa_reg; >>    unsigned short retaddr_column; >>    char saved[PRE_GCC3_DWARF_FRAME_REGISTERS+1]; >> } frame_state; >> >> structure, where PRE_GCC3_DWARF_FRAME_REGISTERS defaults to >> __LIBGCC_DWARF_FRAME_REGISTERS__, which is defined to >> DWARF_FRAME_REGISTERS, which defaults to FIRST_PSEUDO_REGISTER. >> So, changing FIRST_PSEUDO_REGISTER is an ABI change unless you arrange >> for >> PRE_GCC3_DWARF_FRAME_REGISTERS to be defined to the old value. >> >>     Jakub >> > > So where's the red flag that warns about this? > > I also note that Richard Sandiford made a similar type of change for > AArch64 in r10-4195 (183bfdafc6f1f98711c5400498a7268cc1441096) and > nothing was said about that at the time. > > It seems incredibly fragile to me to have some ABI based off the number > of machine registers. > > R. Also, the Arm port does not use dwarf based unwinding, so is this really relevant? R.