From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91560 invoked by alias); 9 Jul 2018 16:39:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 91332 invoked by uid 89); 9 Jul 2018 16:39:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_FAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Jul 2018 16:39:24 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcZC2-0003FS-3c for gcc-patches@gcc.gnu.org; Mon, 09 Jul 2018 12:39:23 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42130 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcZC1-0003Ed-PX for gcc-patches@gcc.gnu.org; Mon, 09 Jul 2018 12:39:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C7E51713; Mon, 9 Jul 2018 09:39:15 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.23]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D5F883F589; Mon, 9 Jul 2018 09:39:14 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw , richard.earnshaw@arm.com Subject: [PATCH 5/7] AArch64 - disable CB[N]Z TB[N]Z when tracking speculation Date: Mon, 09 Jul 2018 16:39:00 -0000 Message-Id: <1531154299-28349-6-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.7.4" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 X-SW-Source: 2018-07/txt/msg00430.txt.bz2 This is a multi-part message in MIME format. --------------2.7.4 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 935 The CB[N]Z and TB[N]Z instructions do not expose the comparison through the condition code flags. This makes it impossible to track speculative execution through such a branch. We can handle this relatively easily by simply disabling the patterns in this case. A side effect of this is that the split patterns for the atomic operations need to also avoid generating these instructions. They mostly have simple fall-backs for this already. * config/aarch64/aarch64.md (cb1): Disable when aarch64_track_speculation is true. (tb1): Likewise. * config/aarch64/aarch64.c (aarch64_split_compare_regs): Do not generate CB[N]Z when tracking speculation. (aarch64_split_compare_and_swap): Likewise. (aarch64_split_atomic_op): Likewise. --- gcc/config/aarch64/aarch64.c | 33 ++++++++++++++++++++++++++++++--- gcc/config/aarch64/aarch64.md | 6 +++--- 2 files changed, 33 insertions(+), 6 deletions(-) --------------2.7.4 Content-Type: text/x-patch; name="0005-AArch64-disable-CB-N-Z-TB-N-Z-when-tracking-speculat.patch" Content-Disposition: attachment; filename="0005-AArch64-disable-CB-N-Z-TB-N-Z-when-tracking-speculat.patch" Content-Transfer-Encoding: quoted-printable Content-length: 3218 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 01f35f8..da96afd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -14465,7 +14465,16 @@ aarch64_split_compare_and_swap (rtx operands[]) =20 if (strong_zero_p) { - x =3D gen_rtx_NE (VOIDmode, rval, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg =3D aarch64_gen_compare_reg (NE, rval, const0_rtx); + x =3D gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x =3D gen_rtx_NE (VOIDmode, rval, const0_rtx); + x =3D gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -14483,7 +14492,16 @@ aarch64_split_compare_and_swap (rtx operands[]) =20 if (!is_weak) { - x =3D gen_rtx_NE (VOIDmode, scratch, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg =3D aarch64_gen_compare_reg (NE, scratch, const0_rtx); + x =3D gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x =3D gen_rtx_NE (VOIDmode, scratch, const0_rtx); + x =3D gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label1), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -14819,7 +14837,16 @@ aarch64_split_atomic_op (enum rtx_code code, rtx o= ld_out, rtx new_out, rtx mem, aarch64_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out), model_rtx); =20 - x =3D gen_rtx_NE (VOIDmode, cond, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg =3D aarch64_gen_compare_reg (NE, cond, const0_rtx); + x =3D gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x =3D gen_rtx_NE (VOIDmode, cond, const0_rtx); + x =3D gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c135ada..259a07d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -690,7 +690,7 @@ (define_insn "*cb1" (const_int 0)) (label_ref (match_operand 1 "" "")) (pc)))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) =3D=3D 8) return aarch64_gen_far_branch (operands, 1, "Lcb", "\\t%0= , "); @@ -720,7 +720,7 @@ (define_insn "*tb1" (label_ref (match_operand 2 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) =3D=3D 8) { @@ -756,7 +756,7 @@ (define_insn "*cb1" (label_ref (match_operand 1 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) =3D=3D 8) { --------------2.7.4--