From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by sourceware.org (Postfix) with ESMTP id 823F13858403 for ; Wed, 15 Sep 2021 15:35:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 823F13858403 Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-83-1s9KgrcMNaKQPTk4roQ_Ig-1; Wed, 15 Sep 2021 11:35:44 -0400 X-MC-Unique: 1s9KgrcMNaKQPTk4roQ_Ig-1 Received: by mail-qk1-f199.google.com with SMTP id d202-20020a3768d3000000b003d30722c98fso4016678qkc.10 for ; Wed, 15 Sep 2021 08:35:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=r8IHvrvwoOy4aGB6/oBeEfk/DDEVkplNaqF7PWgWTac=; b=QSUoA59YHcsXDRnjMaVzACKDS2jNvFOaufOMYyoCEE8BXK3veglLJPK/iuFnOKv8tq gpnbQwMLw5G2/mh4a6MZvROiYr3nip1xLFEjqWYAS8eYVKqp3XPi0IvPzOlq9XcSO/9k HKX7KPfqD07rKc9hN85Z24JQH8PumavfpDDR3nUJo65Taww/0sUONy0amM2vh6KzoY0y raceteG//9/pYUYFIyyGjGHEVBD/sEZLeHUubJbj3e4l0Z7Q7qwtKIC8eN91VFyxOsGJ PNJWnlzqsw0h61BrPv97Z5ZEZALhqRAGw0yYd4rX4CIVq9ilktGsKmWqD6rtwgAAIb2W Ba+w== X-Gm-Message-State: AOAM530vBtrdDg3EwDz5aLiqPs+KeKCVhp0R1s0Zrx6aeFyQlwp+z/ud ICY7QOUjwFQp6A346OZhXLWYoftjwzJFjTnNnFlxr82IkG8AL7qxg/7GMyXR0zyBof6fs1O8wfw R/WQub+uvWuxiweoY3g== X-Received: by 2002:ac8:7003:: with SMTP id x3mr442561qtm.284.1631720143545; Wed, 15 Sep 2021 08:35:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCNnvHyrPK8UiXajs/H7pWWkHgL1o1Xyp7ul0Odtwn4DmUubc998LMeCwo7tFytO85hvkezg== X-Received: by 2002:ac8:7003:: with SMTP id x3mr442542qtm.284.1631720143297; Wed, 15 Sep 2021 08:35:43 -0700 (PDT) Received: from [192.168.1.149] (130-44-159-43.s11817.c3-0.arl-cbr1.sbo-arl.ma.cable.rcncustomer.com. [130.44.159.43]) by smtp.gmail.com with ESMTPSA id h70sm264599qke.54.2021.09.15.08.35.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Sep 2021 08:35:42 -0700 (PDT) Subject: Re: [PATCH RFC] c++: implement C++17 hardware interference size To: =?UTF-8?Q?Martin_Li=c5=a1ka?= , Christophe LYON , gcc-patches@gcc.gnu.org, "Richard Earnshaw (lists)" References: <36407ef6-ea30-6663-62b8-05ae37667ce9@redhat.com> <20210910131625.159525-1-jason@redhat.com> <511b262a-5187-108d-7047-16d2d87e5667@foss.st.com> From: Jason Merrill Message-ID: <15a866aa-1868-c647-5ff0-4fb02f60c8ee@redhat.com> Date: Wed, 15 Sep 2021 11:35:41 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, NICE_REPLY_A, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Sep 2021 15:35:46 -0000 On 9/15/21 8:31 AM, Martin Liška wrote: > On 9/14/21 09:56, Christophe LYON via Gcc-patches wrote: >> So adjustment is needed for both arm and aarch64 targets > > Hello. > > I noticed the same problem and I've got a patch candidate for it. > > What do you think about it? I've now silenced the warning for internal default values, but they're still worth discussion. For arm, I think it would make sense to use 32 for constructive for the generic target, but perhaps we think the older chips aren't worth constraining new code for? In which case, perhaps param_l1_cache_line_size should also default to 64 for the generic target. For aarch64, it seems even more questionable that param_l1_cache_line_size is 32 for the generic target; are there any aarch64 CPUs with a 32B L1 cache line? Jason