From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80735 invoked by alias); 3 Mar 2016 18:10:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80715 invoked by uid 89); 3 Mar 2016 18:10:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=thomaspreudhommefossarmcom, thomas.preudhomme@foss.arm.com, thomaspreudhommearmcom, thomas.preudhomme@arm.com X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 Mar 2016 18:10:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B764049; Thu, 3 Mar 2016 10:09:48 -0800 (PST) Received: from e108577-lin.localnet (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 943813F25E; Thu, 3 Mar 2016 10:10:44 -0800 (PST) From: Thomas Preudhomme To: Ramana Radhakrishnan Cc: gcc-patches , Richard Earnshaw , Ramana Radhakrishnan , Kyrylo Tkachov Subject: Re: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0 Date: Thu, 03 Mar 2016 18:10:00 -0000 Message-ID: <1603382.ae66nuf4zY@e108577-lin> User-Agent: KMail/4.13.3 (Linux/3.13.0-79-generic; KDE/4.13.3; x86_64; ; ) In-Reply-To: <5977152.ypptlNxk28@e108577-lin> References: <000001d137e1$b2956700$17c03500$@foss.arm.com> <5977152.ypptlNxk28@e108577-lin> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-IsSubscribed: yes X-SW-Source: 2016-03/txt/msg00286.txt.bz2 On Thursday 03 March 2016 15:32:27 Thomas Preudhomme wrote: > On Thursday 03 March 2016 09:44:31 Ramana Radhakrishnan wrote: > > On Thu, Mar 3, 2016 at 9:40 AM, Thomas Preudhomme > > > > wrote: > > > On Friday 15 January 2016 12:45:04 Ramana Radhakrishnan wrote: > > >> On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme > > >> > > >> wrote: > > >> > During reorg pass, thumb1_reorg () is tasked with rewriting mov rd, > > >> > rn > > >> > to > > >> > subs rd, rn, 0 to avoid a comparison against 0 instruction before > > >> > doing > > >> > a > > >> > conditional branch based on it. The actual avoiding of cmp is done in > > >> > cbranchsi4_insn instruction C output template. When the condition is > > >> > met, > > >> > the source register (rn) is also propagated into the comparison in > > >> > place > > >> > the destination register (rd). > > >> > > > >> > However, right now thumb1_reorg () only look for a mov followed by a > > >> > cbranchsi but does not check whether the comparison in cbranchsi is > > >> > against the constant 0. This is not safe because a non clobbering > > >> > instruction could exist between the mov and the comparison that > > >> > modifies > > >> > the source register. This is what happens here with a post increment > > >> > of > > >> > the source register after the mov, which skip the &a[i] == &a[1] > > >> > comparison for iteration i == 1. > > >> > > > >> > This patch fixes the issue by checking that the comparison is against > > >> > constant 0. > > >> > > > >> > ChangeLog entry is as follow: > > >> > > > >> > > > >> > *** gcc/ChangeLog *** > > >> > > > >> > 2015-12-07 Thomas Preud'homme > > >> > > > >> > * config/arm/arm.c (thumb1_reorg): Check that the comparison > > >> > is > > >> > against the constant 0. > > >> > > >> OK. > > >> > > >> Ramana > > >> > > >> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > > >> > index 42bf272..49c0a06 100644 > > >> > --- a/gcc/config/arm/arm.c > > >> > +++ b/gcc/config/arm/arm.c > > >> > @@ -17195,7 +17195,7 @@ thumb1_reorg (void) > > >> > > > >> > FOR_EACH_BB_FN (bb, cfun) > > >> > > > >> > { > > >> > > > >> > rtx dest, src; > > >> > > > >> > - rtx pat, op0, set = NULL; > > >> > + rtx cmp, op0, op1, set = NULL; > > >> > > > >> > rtx_insn *prev, *insn = BB_END (bb); > > >> > bool insn_clobbered = false; > > >> > > > >> > @@ -17208,8 +17208,13 @@ thumb1_reorg (void) > > >> > > > >> > continue; > > >> > > > >> > /* Get the register with which we are comparing. */ > > >> > > > >> > - pat = PATTERN (insn); > > >> > - op0 = XEXP (XEXP (SET_SRC (pat), 0), 0); > > >> > + cmp = XEXP (SET_SRC (PATTERN (insn)), 0); > > >> > + op0 = XEXP (cmp, 0); > > >> > + op1 = XEXP (cmp, 1); > > >> > + > > >> > + /* Check that comparison is against ZERO. */ > > >> > + if (!CONST_INT_P (op1) || INTVAL (op1) != 0) > > >> > + continue; > > >> > > > >> > /* Find the first flag setting insn before INSN in basic block > > >> > BB. > > >> > */ > > >> > gcc_assert (insn != BB_HEAD (bb)); > > >> > > > >> > @@ -17249,7 +17254,7 @@ thumb1_reorg (void) > > >> > > > >> > PATTERN (prev) = gen_rtx_SET (dest, src); > > >> > INSN_CODE (prev) = -1; > > >> > /* Set test register in INSN to dest. */ > > >> > > > >> > - XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest); > > >> > + XEXP (cmp, 0) = copy_rtx (dest); > > >> > > > >> > INSN_CODE (insn) = -1; > > >> > > > >> > } > > >> > > > >> > } > > >> > > > >> > Testsuite shows no regression when run for arm-none-eabi with > > >> > -mcpu=cortex-m0 -mthumb > > > > > > The patch applies cleanly on gcc-5-branch and also show no regression > > > when > > > run for arm-none-eabi with -mcpu=cortex-m0 -mthumb. Is it ok to > > > backport? > > > > This deserves a testcase. > > The original patch don't have one initially because it fixes a fail of an > existing testcase (loop-2b.c). However, the test pass on gcc 5 due to > difference in code generation. I'm currently trying to come up with a > testcase and will get back at you. Sadly I did not manage to come up with a testcase that works on GCC 5. One need to reproduce a sequence of the form: (set B A) (insn clobbering A that is not a set, ie store with post increment) (conditional branch between A and something else) In that case, thumb1_reorg changes the set into (set B (minus A 0)) which is safe but also replace A by B in the conditional insn which is unsafe in the above situation. The problem I am having is to make GCC generate a move instruction because it's always optimized away. Using local register variable is not an option because the move should be between regular registers. Any idea to construct a testcase? Best regards, Thomas