From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by sourceware.org (Postfix) with ESMTPS id 171B5384B806 for ; Mon, 16 Nov 2020 18:57:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 171B5384B806 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=philipp.tomsich@vrull.eu Received: by mail-lj1-x244.google.com with SMTP id b17so21321056ljf.12 for ; Mon, 16 Nov 2020 10:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pwpOv+2PRAgKj7cgNSHPP4/AiTwfsOK3erL7itXOUHM=; b=R8H0i70Q9pu0QyMZrqB2dGmoeOFhKhKdfHnJOaOaWIP1JsxDbDyI5K1fBOg8v0/58n Ef6jVpLw0lVflwYF8L7MqFbf+M7z8cpHQiWdacELzPzC8GXwwXGbAzEKF4kFsjz0uCAo xAxpaMiRASCChLjqtbN8d8g0jWfOAzM0dcyVMa6exSiQ6ahpxD/qGZbQvFJviS8/WzC2 Ttro3o44hymfwi43qKIt0dwVnDUp0QRnFT/4czWHM/Smah6Ol85n6SvP99JB8KWeVgJq SjQ+2K7nnpemCXdTsr4wYG/1IcE3TuN/WNls0aoN2PZFOdXwSlpGTuRSpcu2GiKWIPHi ZpOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pwpOv+2PRAgKj7cgNSHPP4/AiTwfsOK3erL7itXOUHM=; b=G/u/dqXH1sQn0JP2AitUA7vNWLW/5p2gqyxBXgckJEcaewnxS8xTZPmxL77CA1QreK du40U1nC8i9rGROUZebRhSyG4+MxVqgcza4mQhwxOuvGgX4V2vtHWLv3mfWO/qxrOS31 eAypeiBICodna7WzK+KbIPb2aBznrKUNPPyxk+X+DA4DXh2y1XyEON3BhLrsr2uF01wv uTV6nIhiYkQnaMMkm70gTYrmrbJzUUyd82AiVn64dbD1e6qu2t0ht/6eWtUOHIVa2TzI vCO06T68hFaU4A5KUAGB5M6Z63YnNHcqWl1RNrhvhEiYq83jzYmu7zcaEFZFD8wjTMTY 14bQ== X-Gm-Message-State: AOAM531Kd4tmLWjBJ2THeFyUxkuyt1Fv/ZCR9DOSHXziViKnC4XnoY1r y6J9WtNgdRAP6vC+XHMBq0zJktLwSxCiIL38 X-Google-Smtp-Source: ABdhPJwT3iJSEOThee6t4qb32YZWYx9CSGbyaGh82/YzvKQRGPU5WAVH1diA4DlH0EyjiS/cV4KTHg== X-Received: by 2002:a2e:9798:: with SMTP id y24mr275027lji.341.1605553061521; Mon, 16 Nov 2020 10:57:41 -0800 (PST) Received: from centos7.localdomain (static.214.61.181.135.clients.your-server.de. [135.181.61.214]) by smtp.gmail.com with ESMTPSA id v1sm2886718lfq.210.2020.11.16.10.57.41 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Nov 2020 10:57:41 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Philipp Tomsich , Jim Wilson Subject: [PATCH v1 2/2] RISC-V: Adjust predicates for immediate shift operands Date: Mon, 16 Nov 2020 19:57:07 +0100 Message-Id: <1605553027-5331-2-git-send-email-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1605553027-5331-1-git-send-email-philipp.tomsich@vrull.eu> References: <1605553027-5331-1-git-send-email-philipp.tomsich@vrull.eu> X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Nov 2020 18:57:44 -0000 From: Philipp Tomsich In case a negative shift operand makes it through into the backend, it will be treated as unsigned and truncated (using a mask) to fit into the range 0..31 (for SImode) and 0..63 (for DImode). Consider the following output illustrating the issue and shows how the shift amount is truncated): #(insn 16 15 53 (set (reg:DI 10 a0 [orig:72 ] [72]) # (sign_extend:DI (ashift:SI (reg:SI 15 a5 [orig:73 a ] [73]) # (const_int -1 [0xffffffffffffffff])))) "isolated.c":3:13 168 {*ashlsi3_extend} # (expr_list:REG_DEAD (reg:SI 15 a5 [orig:73 a ] [73]) # (nil))) slliw a0,a5,31 #, , a # 16 [c=8 l=4] *ashlsi3_extend This change adjusts the predicates to allow immediate shifts for the supported ranges 0..31 and 0..63, respectively, only. As immediates outside of these ranges can no longer pass the constraint-check, the implementation of the patterns emitting the respective shift can also be simplified. Larger shift amounts will now be forced along a path resulting in a non-immediate shift. A new testcase is added to check that non-immediate shift instructions are emitted. gcc/ChangeLog: * config/riscv/predicates.md (riscv_shift_imm_si, riscv_shift_si, riscv_shift_imm_di, riscv_shift_di): New. * config/riscv/riscv.md: Use 'riscv_shift_si' and 'riscv_shift_di' in definition of shift instructions; remove (now unnecessary) truncation of immediates. gcc/testsuite/ChangeLog: * gcc.target/riscv/shift-negative-amount.c: New. --- gcc/ChangeLog | 5 +++++ gcc/config/riscv/predicates.md | 16 ++++++++++++++++ gcc/config/riscv/riscv.md | 21 ++++----------------- gcc/testsuite/ChangeLog | 4 ++++ .../gcc.target/riscv/shift-negative-amount.c | 14 ++++++++++++++ 5 files changed, 43 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/shift-negative-amount.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b8b9beb..6ca8ee0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-11-16 Philipp Tomsich + * config/riscv/predicates.md (riscv_shift_imm_si, riscv_shift_si, + riscv_shift_imm_di, riscv_shift_di): New. + * config/riscv/riscv.md: Use 'riscv_shift_si' and 'riscv_shift_di' + in definition of shift instructions; remove (now unnecessary) + truncation of immediates. * vr-values.h (simplify_using_ranges): Declare. * vr-values.c (simplify_lshift_using_ranges): New function. (simplify): Use simplify_lshift_using_ranges for LSHIFT_EXPR. diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index f764fe7..fb35871 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -27,6 +27,22 @@ (ior (match_operand 0 "const_arith_operand") (match_operand 0 "register_operand"))) +(define_predicate "riscv_shift_imm_si" + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32"))) + +(define_predicate "riscv_shift_si" + (ior (match_operand 0 "riscv_shift_imm_si") + (match_operand 0 "register_operand"))) + +(define_predicate "riscv_shift_imm_di" + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64"))) + +(define_predicate "riscv_shift_di" + (ior (match_operand 0 "riscv_shift_imm_di") + (match_operand 0 "register_operand"))) + (define_predicate "lui_operand" (and (match_code "const_int") (match_test "LUI_OPERAND (INTVAL (op))"))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f15bad3..7b34839 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1574,13 +1574,9 @@ [(set (match_operand:SI 0 "register_operand" "= r") (any_shift:SI (match_operand:SI 1 "register_operand" " r") - (match_operand:QI 2 "arith_operand" " rI")))] + (match_operand:QI 2 "riscv_shift_si" " rI")))] "" { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) - & (GET_MODE_BITSIZE (SImode) - 1)); - return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; } [(set_attr "type" "shift") @@ -1629,13 +1625,9 @@ [(set (match_operand:DI 0 "register_operand" "= r") (any_shift:DI (match_operand:DI 1 "register_operand" " r") - (match_operand:QI 2 "arith_operand" " rI")))] + (match_operand:QI 2 "riscv_shift_di" " rI")))] "TARGET_64BIT" { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) - & (GET_MODE_BITSIZE (DImode) - 1)); - return "%i2\t%0,%1,%2"; } [(set_attr "type" "shift") @@ -1685,14 +1677,9 @@ [(set (match_operand:DI 0 "register_operand" "= r") (sign_extend:DI (any_shift:SI (match_operand:SI 1 "register_operand" " r") - (match_operand:QI 2 "arith_operand" " rI"))))] + (match_operand:QI 2 "riscv_shift_si" " rI"))))] "TARGET_64BIT" -{ - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return "%i2w\t%0,%1,%2"; -} + "%i2w\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "mode" "SI")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a748ff6..1efe87d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-11-16 Philipp Tomsich + + * gcc.target/riscv/shift-negative-amount.c: New. + 2020-11-13 Joseph Myers * gcc.dg/binary-constants-2.c, gcc.dg/binary-constants-3.c, diff --git a/gcc/testsuite/gcc.target/riscv/shift-negative-amount.c b/gcc/testsuite/gcc.target/riscv/shift-negative-amount.c new file mode 100644 index 0000000..0db5e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-negative-amount.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-tree-vrp" } */ + +int shift1 (int a, int b, int c) +{ + return (a << ((b && c) - 1)); +} + +long int shift2 (long int a, long int b, long int c) +{ + return (a << ((b && c) - 1)); +} +/* { dg-final { scan-assembler "sllw" } } */ +/* { dg-final { scan-assembler "sll" } } */ -- 1.8.3.1