From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id 9CF973972C16 for ; Fri, 11 Dec 2020 18:37:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 9CF973972C16 Received: by mail-wr1-x435.google.com with SMTP id q18so2504879wrn.1 for ; Fri, 11 Dec 2020 10:37:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=3Drfcr4KP4O4Ve7lqhYPRkZKut3/3nsGmAd5aegcjuU=; b=JeLD1BgMb32WtG3pa1DWo3feknSMHrd7GfZi35qbFiMKQcwad75AJ2OJFRKR8aH/2q +Budw9u0ZIxxAQTFt9oPJ9OtNppX/xAAmkWTWCQx/YQK1PQJ4TFVen4y+IeRJeo47Li1 SHyhKKFPPgO0jNCewUgKyXYDeZ1JJE9jw2BBTak8OzH7sli7QmOyE+kMQM1WAsRjg5bX ZYwPFRdIqEt36gMjpb+bAFYA7g5hMZsedsCFFNdRUhpb4NCYngxj2CLjLqJCtQwtW+VX rodBmBxzOgKs+XT5AAXR38NxWg6I2qE1rOV/+DK4hx8XLimG87zsKpbE7Yf2re3TGLSU vcRw== X-Gm-Message-State: AOAM531cRJZfSSptfp/Z2VWe/TbHKtYpL9HX7DrihXNE3BddJBb4pKDO m3S3SpJeHPefIBWKJ+B9tycMzMAltUYWGs/R X-Google-Smtp-Source: ABdhPJztsoOWMLjmfcC5aQ0CnwUEGGpbKyKC4n73nbadqY82NCf+QMJF8Pv80EESGZWK4AFBtCGmIg== X-Received: by 2002:adf:ed12:: with SMTP id a18mr15360004wro.5.1607711832088; Fri, 11 Dec 2020 10:37:12 -0800 (PST) Received: from localhost.localdomain (static.42.136.251.148.clients.your-server.de. [148.251.136.42]) by smtp.gmail.com with ESMTPSA id k18sm18588685wrd.45.2020.12.11.10.37.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Dec 2020 10:37:11 -0800 (PST) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 1/4] arm: Auto-vectorization for MVE: veor Date: Fri, 11 Dec 2020 18:37:07 +0000 Message-Id: <1607711830-9213-1-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Dec 2020 18:37:15 -0000 This patch enables MVE veorq instructions for auto-vectorization. MVE veorq insns in mve.md are modified to use xor instead of unspec expression to support xor3. The xor3 expander is added to vec-common.md 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U. (VEORQ): Remove. * config/arm/mve.md (mve_veorq_u): New entry for veor instruction using expression xor. (mve_veorq_s): New expander. (mve_veorq_f): Use 'xor' code instead of unspec. * config/arm/neon.md (xor3): Renamed into xor3_neon. * config/arm/unspecs.md (VEORQ_S, VEORQ_U, VEORQ_F): Remove. * config/arm/vec-common.md (xor3): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-veor.c: Add tests for veor. --- gcc/config/arm/iterators.md | 3 +- gcc/config/arm/mve.md | 22 ++++++---- gcc/config/arm/neon.md | 2 +- gcc/config/arm/unspecs.md | 3 -- gcc/config/arm/vec-common.md | 7 ++++ gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 61 ++++++++++++++++++++++++++++ 6 files changed, 84 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-veor.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 5fcb7af..0195275 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1237,7 +1237,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") - (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") + (VCMPNEQ_N_U "u") (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") @@ -1507,7 +1507,6 @@ (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) -(define_int_iterator VEORQ [VEORQ_U VEORQ_S]) (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4b2e46a..10512ad 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1207,17 +1207,24 @@ (define_insn "mve_vcmpneq_n_" ;; ;; [veorq_u, veorq_s]) ;; -(define_insn "mve_veorq_" +(define_insn "mve_veorq_u" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VEORQ)) + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "veor %q0, %q1, %q2" + "veor\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_veorq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vhaddq_n_u, vhaddq_n_s]) @@ -2404,9 +2411,8 @@ (define_insn "mve_vcvttq_f16_f32v8hf" (define_insn "mve_veorq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VEORQ_F)) + (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "veor %q0, %q1, %q2" diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 669c34d..e1263b0 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -747,7 +747,7 @@ (define_insn "bic3_neon" [(set_attr "type" "neon_logic")] ) -(define_insn "xor3" +(define_insn "xor3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w") (match_operand:VDQ 2 "s_register_operand" "w")))] diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index c2076c9..fe240e8 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -608,7 +608,6 @@ (define_c_enum "unspec" [ VCMPEQQ_S VCMPEQQ_N_S VCMPNEQ_N_S - VEORQ_S VHADDQ_S VHADDQ_N_S VHSUBQ_S @@ -653,7 +652,6 @@ (define_c_enum "unspec" [ VCMPEQQ_U VCMPEQQ_N_U VCMPNEQ_N_U - VEORQ_U VHADDQ_U VHADDQ_N_U VHSUBQ_U @@ -736,7 +734,6 @@ (define_c_enum "unspec" [ VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F - VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 8d9c89c..030ed82 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -186,3 +186,10 @@ (define_expand "ior3" (match_operand:VDQ 2 "neon_logic_op2" "")))] "ARM_HAVE__ARITH" ) + +(define_expand "xor3" + [(set (match_operand:VDQ 0 "s_register_operand" "") + (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:VDQ 2 "s_register_operand" "")))] + "ARM_HAVE__ARITH" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c new file mode 100644 index 0000000..321961f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c @@ -0,0 +1,61 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \ + int i; \ + for (i=0; i