From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by sourceware.org (Postfix) with ESMTPS id E7067397307B for ; Fri, 11 Dec 2020 18:37:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E7067397307B Received: by mail-wr1-x433.google.com with SMTP id r14so10037268wrn.0 for ; Fri, 11 Dec 2020 10:37:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=wE6ZzrWn0KqW2Hoe5ILgWxTd56/XGLrIj7QxkSJ9tRE=; b=ScJBGE8NA074DrEtiy3lRZHty2V0VoGyYyffGpGu6f1SM8wqxg79lcO1uAqehsSTQF VrJw4qAximCU8P8hEa8u03uwXfHdTPmjrclCD2qIuUytcHU8VxWDXYPch28+6beJm25y iCqY3agD20rSmXQv/fRCLVv5Zh67+DV9xMdBQuM3ueaRatRgcWxuOvPXZ8WMkhsF0wof 87lQbuAoTU5aQlppIbmTYVT8Gt/j6pJOCrRWm/GPpwungU/kji84WqnKg2KFtwvEBUhj /ftDdeCAVrNXyPxPZiUDADsWSnZe2t3g7T4mMC22JbuokEYeESYPVupCgrT+oE0+X59f fjOw== X-Gm-Message-State: AOAM533rMX2clst1U5JgyEw9o4dv+pd+FLU/RwLtNSSOxYw3IZNMVi5x ElLaWfoD668qGVZvTm7CyQoX8MTuwE7dl6NF X-Google-Smtp-Source: ABdhPJxLJykuEEmlTy25Iaz5cJEThdnn000Bd1QkVJm7eOxpP9GxTk876V2lKDd+xc9S3AbytY0qrQ== X-Received: by 2002:adf:e710:: with SMTP id c16mr15583582wrm.295.1607711834591; Fri, 11 Dec 2020 10:37:14 -0800 (PST) Received: from localhost.localdomain (static.42.136.251.148.clients.your-server.de. [148.251.136.42]) by smtp.gmail.com with ESMTPSA id k18sm18588685wrd.45.2020.12.11.10.37.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Dec 2020 10:37:14 -0800 (PST) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 4/4] arm: Auto-vectorization for MVE: vneg Date: Fri, 11 Dec 2020 18:37:10 +0000 Message-Id: <1607711830-9213-4-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607711830-9213-1-git-send-email-christophe.lyon@linaro.org> References: <1607711830-9213-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Dec 2020 18:37:17 -0000 This patch enables MVE vneg instructions for auto-vectorization. MVE vnegq insns in mve.md are modified to use 'neg' instead of unspec expression. The neg2 expander is added to vec-common.md. Existing patterns in neon.md are prefixed with neon_. It's not clear why we have different patterns for VDQW and VH in neon.md, when WDQWH handles both, and patterns with VDQ have provision for attributes for FP modes. Another question is why 2 always sets neon_abs type when it also handles neon_neq cases. 2020-12-11 Christophe Lyon gcc/ * config/arm/mve.md (mve_vnegq_f): Use 'neg' instead of unspec. (mve_vnegq_s): Likewise. * config/arm/neon.md (neg2): Rename into neon_neg2. (2): Rename into neon_2. (neon_v): Call gen_neon_2. (vashr3): Call gen_neon_neg2. (vlshr3): Call gen_neon_neg2. (neon_vneg): Call gen_neon_neg2. * config/arm/unspecs.md (VNEGQ_F, VNEGQ_S): Remove. * config/arm/vec-common.md (neg2): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vneg.c: Add tests for vneg. --- gcc/config/arm/mve.md | 6 ++-- gcc/config/arm/neon.md | 12 +++---- gcc/config/arm/unspecs.md | 2 -- gcc/config/arm/vec-common.md | 6 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 49 ++++++++++++++++++++++++++++ 5 files changed, 63 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vneg.c diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 86d7fc6..b4c5a1e2 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -271,8 +271,7 @@ (define_insn "mve_vrev64q_f" (define_insn "mve_vnegq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] - VNEGQ_F)) + (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vneg.f%# %q0, %q1" @@ -422,8 +421,7 @@ (define_insn "mve_vqabsq_s" (define_insn "mve_vnegq_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VNEGQ_S)) + (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" "vneg.s%# %q0, %q1" diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index f58d4f5..d2e92ba 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -775,7 +775,7 @@ (define_insn "abs2" (const_string "neon_abs")))] ) -(define_insn "neg2" +(define_insn "neon_neg2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -786,7 +786,7 @@ (define_insn "neg2" (const_string "neon_neg")))] ) -(define_insn "2" +(define_insn "neon_2" [(set (match_operand:VH 0 "s_register_operand" "=w") (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))] "TARGET_NEON_FP16INST" @@ -800,7 +800,7 @@ (define_expand "neon_v" (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))] "TARGET_NEON_FP16INST" { - emit_insn (gen_2 (operands[0], operands[1])); + emit_insn (gen_neon_2 (operands[0], operands[1])); DONE; }) @@ -952,7 +952,7 @@ (define_expand "vashr3" if (s_register_operand (operands[2], mode)) { rtx neg = gen_reg_rtx (mode); - emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_neon_neg2 (neg, operands[2])); emit_insn (gen_ashl3_signed (operands[0], operands[1], neg)); } else @@ -969,7 +969,7 @@ (define_expand "vlshr3" if (s_register_operand (operands[2], mode)) { rtx neg = gen_reg_rtx (mode); - emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_neon_neg2 (neg, operands[2])); emit_insn (gen_ashl3_unsigned (operands[0], operands[1], neg)); } else @@ -2953,7 +2953,7 @@ (define_expand "neon_vneg" (match_operand:VDQW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_neg2 (operands[0], operands[1])); + emit_insn (gen_neon_neg2 (operands[0], operands[1])); DONE; }) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e581645..ef64989 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -530,7 +530,6 @@ (define_c_enum "unspec" [ VRNDMQ_F VRNDAQ_F VREV64Q_F - VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F @@ -549,7 +548,6 @@ (define_c_enum "unspec" [ VREV64Q_S VREV64Q_U VQABSQ_S - VNEGQ_S VDUPQ_N_U VDUPQ_N_S VCLZQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 37ff518..2d0932b 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -199,3 +199,9 @@ (define_expand "one_cmpl2" (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] "ARM_HAVE__ARITH" ) + +(define_expand "neg2" + [(set (match_operand:VDQWH 0 "s_register_operand" "") + (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] + "ARM_HAVE__ARITH" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c new file mode 100644 index 0000000..afd0d60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c @@ -0,0 +1,49 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3" } */ + +#include +#include + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ + int i; \ + for (i=0; i