From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by sourceware.org (Postfix) with ESMTPS id 8D84B3851C1D for ; Fri, 30 Apr 2021 14:09:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8D84B3851C1D Received: by mail-wm1-x32e.google.com with SMTP id g65so8783499wmg.2 for ; Fri, 30 Apr 2021 07:09:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=DcItrUaXhpURFVZb7JbNxa9GzbNFC26yXoyz7fkkbis=; b=g8u23SF25xWKeS/NGddHQ/KaALlAq3rbKk7NHxj/1jQa4xtGwMtgAnAWN80XfVQd6g Vz56I+Zb68qGLxircV9kfTwMzdpMcg4BLfFCdu0qfpz8XLxKhFCKOCea+31XjEVAKS20 GzWiVT4bxL8Qj8C2izwJ8oVrHlK1zhyFu7MSzyHY9rl15FtPcIZbPGH6qQYf3+9aRGS6 GRe3vfeYgifnxZlxKVgf+O6/TZVu7EORKVGn+U9M4JJOSUxqUAOPrc+P0sLx10Yk48/j XFDdMwxcxs+olIQoLG0WqnsHs6Z77VF5JT+WCg3746AylP3du/KbRMY5iA1Pd3v/nIf2 iMlw== X-Gm-Message-State: AOAM532IahkAxHzkSG9h/ggqvCukMV3W8jS0Si5/wWs4aTTVRIpRXWTd T18Np9HE9nmS5v6BbP9X+g1czwS9kZqslgaG X-Google-Smtp-Source: ABdhPJyNczpSOAi/zV4V8LmOF/lPjgoqo+os6uM+dBqOJBszROQhAn34TESlSc/siD59mUm7kAYGXg== X-Received: by 2002:a1c:4c07:: with SMTP id z7mr6337001wmf.96.1619791793205; Fri, 30 Apr 2021 07:09:53 -0700 (PDT) Received: from localhost.localdomain (static.42.136.251.148.clients.your-server.de. [148.251.136.42]) by smtp.gmail.com with ESMTPSA id o9sm2345756wmh.19.2021.04.30.07.09.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Apr 2021 07:09:52 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/9] arm: MVE: Factorize all vcmp* integer patterns Date: Fri, 30 Apr 2021 14:09:45 +0000 Message-Id: <1619791790-628-4-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619791790-628-1-git-send-email-christophe.lyon@linaro.org> References: <1619791790-628-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Apr 2021 14:09:56 -0000 After removing the signed and unsigned suffixes in the previous patches, we can now factorize the vcmp* patterns: there is no longer an asymmetry where operators do not have the same set of signed and unsigned variants. The will make maintenance easier. MVE has a different set of vector comparison operators than Neon, so we have to introduce dedicated iterators. 2021-03-01 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_COMPARISONS): New. (mve_cmp_op): New. (mve_cmp_type): New. * config/arm/mve.md (mve_vcmpq_): New, merge all mve_vcmp patterns. (mve_vcmpneq_, mve_vcmpcsq_n_, mve_vcmpcsq_) (mve_vcmpeqq_n_, mve_vcmpeqq_, mve_vcmpgeq_n_) (mve_vcmpgeq_, mve_vcmpgtq_n_, mve_vcmpgtq_) (mve_vcmphiq_n_, mve_vcmphiq_, mve_vcmpleq_n_) (mve_vcmpleq_, mve_vcmpltq_n_, mve_vcmpltq_) (mve_vcmpneq_n_, mve_vcmpltq_n_, mve_vcmpltq_) (mve_vcmpneq_n_): Remove. --- gcc/config/arm/iterators.md | 8 ++ gcc/config/arm/mve.md | 250 ++++---------------------------------------- 2 files changed, 27 insertions(+), 231 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 0aba93f..29347f7 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -285,6 +285,8 @@ (define_code_iterator GTUGEU [gtu geu]) ;; Comparisons for vc (define_code_iterator COMPARISONS [eq gt ge le lt]) +;; Comparisons for MVE +(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne]) ;; A list of ... (define_code_iterator IOR_XOR [ior xor]) @@ -336,8 +338,14 @@ (define_code_attr arith_shift_insn (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") (gtu "gt") (geu "ge")]) +(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") + (gtu "hi") (geu "cs") (ne "ne")]) + (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) +(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s") + (gtu "u") (geu "u") (ne "i")]) + (define_code_attr vfml_op [(plus "a") (minus "s")]) (define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index e9f095d..40baff7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -836,17 +836,30 @@ (define_insn "mve_vaddlvq_p_v4si" (set_attr "length""8")]) ;; -;; [vcmpneq_]) +;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_]) ;; -(define_insn "mve_vcmpneq_" +(define_insn "mve_vcmpq_" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPNEQ)) + (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" + "vcmp.%# , %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_]) +;; +(define_insn "mve_vcmpq_n_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE" - "vcmp.i%# ne, %q1, %q2" + "vcmp.%# , %q1, %2" [(set_attr "type" "mve_move") ]) @@ -1005,231 +1018,6 @@ (define_expand "cadd3" ) ;; -;; [vcmpcsq_n_]) -;; -(define_insn "mve_vcmpcsq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPCSQ_N_U)) - ] - "TARGET_HAVE_MVE" - "vcmp.u%# cs, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpcsq_]) -;; -(define_insn "mve_vcmpcsq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPCSQ_U)) - ] - "TARGET_HAVE_MVE" - "vcmp.u%# cs, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpeqq_n_]) -;; -(define_insn "mve_vcmpeqq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPEQQ_N)) - ] - "TARGET_HAVE_MVE" - "vcmp.i%# eq, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpeqq_]) -;; -(define_insn "mve_vcmpeqq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPEQQ)) - ] - "TARGET_HAVE_MVE" - "vcmp.i%# eq, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgeq_n_]) -;; -(define_insn "mve_vcmpgeq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPGEQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# ge, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgeq_]) -;; -(define_insn "mve_vcmpgeq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPGEQ_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# ge, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgtq_n_]) -;; -(define_insn "mve_vcmpgtq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPGTQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# gt, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgtq_]) -;; -(define_insn "mve_vcmpgtq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPGTQ_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# gt, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmphiq_n_]) -;; -(define_insn "mve_vcmphiq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPHIQ_N_U)) - ] - "TARGET_HAVE_MVE" - "vcmp.u%# hi, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmphiq_]) -;; -(define_insn "mve_vcmphiq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPHIQ_U)) - ] - "TARGET_HAVE_MVE" - "vcmp.u%# hi, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpleq_n_]) -;; -(define_insn "mve_vcmpleq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPLEQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# le, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpleq_]) -;; -(define_insn "mve_vcmpleq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPLEQ_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# le, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpltq_n_]) -;; -(define_insn "mve_vcmpltq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPLTQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# lt, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpltq_]) -;; -(define_insn "mve_vcmpltq_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCMPLTQ_S)) - ] - "TARGET_HAVE_MVE" - "vcmp.s%# lt, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpneq_n_]) -;; -(define_insn "mve_vcmpneq_n_" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPNEQ_N)) - ] - "TARGET_HAVE_MVE" - "vcmp.i%# ne, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; ;; [veorq_u, veorq_s]) ;; (define_insn "mve_veorq_u" -- 2.7.4