* [PATCH] [COMMITTED] Fix PR aarch64/104474: ICE with vector float initializers and non-consts.
@ 2022-02-10 0:48 apinski
0 siblings, 0 replies; only message in thread
From: apinski @ 2022-02-10 0:48 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
The problem here is that the aarch64 back-end was placing const0_rtx
into the constant vector RTL even if the mode was a floating point mode.
The fix is instead to use CONST0_RTX and pass the mode to select the
correct zero (either const_int or const_double).
Committed as obvious after a bootstrap/test on aarch64-linux-gnu with
no regressions.
PR target/104474
gcc/ChangeLog:
* config/aarch64/aarch64.cc
(aarch64_sve_expand_vector_init_handle_trailing_constants):
Use CONST0_RTX instead of const0_rtx for the non-constant elements.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr104474-1.c: New test.
* gcc.target/aarch64/sve/pr104474-2.c: New test.
* gcc.target/aarch64/sve/pr104474-3.c: New test.
---
gcc/config/aarch64/aarch64.cc | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c | 9 +++++++++
gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c | 9 +++++++++
gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c | 9 +++++++++
4 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 8dc6d55e0f2..828ee472be2 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -21164,7 +21164,7 @@ aarch64_sve_expand_vector_init_handle_trailing_constants
{
rtx x = builder.elt (i + nelts_reqd - n_trailing_constants);
if (!valid_for_const_vector_p (elem_mode, x))
- x = const0_rtx;
+ x = CONST0_RTX (elem_mode);
v.quick_push (x);
}
rtx const_vec = v.build ();
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c
new file mode 100644
index 00000000000..9e5bfe64467
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mcpu=neoverse-512tvb -frounding-math -msve-vector-bits=512" } */
+
+typedef float __attribute__((__vector_size__ (64))) F;
+
+F
+foo (void)
+{
+ return (F){68435453, 0, 0, 0, 0, 0, 0, 5, 0, 431144844};
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c
new file mode 100644
index 00000000000..02a4b6a8fdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mcpu=neoverse-512tvb -msve-vector-bits=512" } */
+
+typedef float __attribute__((__vector_size__ (64))) F;
+
+F
+foo (float t)
+{
+ return (F){t, 0, 0, 0, 0, 0, 0, 5, 0, t};
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c
new file mode 100644
index 00000000000..7bed0142968
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mcpu=neoverse-v1 -frounding-math -msve-vector-bits=256" } */
+
+typedef _Float16 __attribute__((__vector_size__ (32))) F;
+
+F
+foo (void)
+{
+ return (F){0, 6270, 0, 0, 0, 0, 0, 0, 3229, 0, 40};
+}
--
2.27.0
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