From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-b.sr.ht (mail-b.sr.ht [173.195.146.151]) by sourceware.org (Postfix) with ESMTPS id 6F6523857401 for ; Tue, 28 Jun 2022 01:26:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6F6523857401 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 747EA11EF31 for ; Tue, 28 Jun 2022 01:26:08 +0000 (UTC) From: ~antoyo Date: Sun, 26 Jun 2022 18:49:15 -0400 Subject: [PATCH gcc 1/1] target: Fix asm generation for AVX builtins when using -masm=intel [PR106095] Message-ID: <165637956824.13615.7247999336313533072-1@git.sr.ht> X-Mailer: git.sr.ht Reply-to: ~antoyo In-Reply-To: <165637956824.13615.7247999336313533072-0@git.sr.ht> To: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DATE_IN_PAST_24_48, FREEMAIL_FORGED_REPLYTO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 01:26:12 -0000 From: Antoni Boucher gcc/ChangeLog: PR target/106095 * config/i386/sse.md: Fix asm generation. gcc/testsuite/ChangeLog: PR target/106095 * gcc.target/i386/pr106095.c: Add test using those AVX builtins. --- gcc/config/i386/sse.md | 10 ++--- gcc/testsuite/gcc.target/i386/pr106095.c | 47 ++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr106095.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8cd0f617bf3..f2f72e8fb05 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -8859,7 +8859,7 @@ "@ cvtsd2ss\t{%2, %0|%0, %2} cvtsd2ss\t{%2, %0|%0, %q2} - vcvtsd2ss\t{%2, %1, %0|%0, = %1, %q2}" + vcvtsd2ss\t{%2, %1, %0|%0, = %1, %q2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssecvt") (set_attr "athlon_decode" "vector,double,*") @@ -8903,7 +8903,7 @@ "@ cvtss2sd\t{%2, %0|%0, %2} cvtss2sd\t{%2, %0|%0, %k2} - vcvtss2sd\t{%2, %1, %0|%0, %1, %k2}" + vcvtss2sd\t{%2, %1, %0|%0, %1, %k2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssecvt") (set_attr "amdfam10_decode" "vector,double,*") @@ -14406,8 +14406,8 @@ "TARGET_AVX512VL" { if (GET_MODE_SIZE (GET_MODE_INNER (mode)) =3D=3D 4) - return "vpmov\t{%1, %0%{%2%}|%0%{%2%}, %t1}"; - return "vpmov\t{%1, %0%{%2%}|%0%{%2%}, %g1}"; + return "vpmov\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + return "vpmov\t{%1, %0%{%2%}|%0%{%2%}, %1}"; } [(set_attr "type" "ssemov") (set_attr "memory" "store") @@ -14506,7 +14506,7 @@ (match_dup 0) (match_operand:QI 2 "register_operand" "Yk")))] "TARGET_AVX512VL" - "vpmovqw\t{%1, %0%{%2%}|%0%{%2%}, %g1}" + "vpmovqw\t{%1, %0%{%2%}|%0%{%2%}, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "store") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/gcc.target/i386/pr106095.c b/gcc/testsuite/gcc.tar= get/i386/pr106095.c new file mode 100644 index 00000000000..dfa6136500f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106095.c @@ -0,0 +1,47 @@ +/* PR gcc/106095 */ +/* { dg-do assemble } */ +/* { dg-options "-mavx512vl -masm=3Dintel" } */ +/* { dg-require-effective-target masm_intel } */ + +#include +#include + +typedef int v4si __attribute__ ((vector_size (16))); +typedef long long v2di __attribute__ ((vector_size (16))); +typedef long long v4di __attribute__ ((vector_size (32))); +typedef double v2df __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); + +void bug1(void) { + v4si ints4 =3D {0, 1, 2, 3}; + unsigned long long *addr =3D malloc(sizeof(*addr)); + __builtin_ia32_pmovdw128mem_mask(addr, ints4, 0); +} + +int bug2(void) { + v2df a =3D {0.0, 0.0}; + v4sf b =3D {0.0, 0.0, 0.0, 0.0}; + v2df src =3D {0.0, 0.0}; + v2df res =3D __builtin_ia32_cvtss2sd_mask_round(a, b, src, 0, _MM_FROUND= _NO_EXC); + return (int)res[0]; +} + +int bug3(void) { + v4sf a =3D {0.0, 0.0, 0.0, 0.0}; + v2df b =3D {0.0, 0.0}; + v4sf src =3D {0.0, 0.0, 0.0, 0.0}; + v4sf res =3D __builtin_ia32_cvtsd2ss_mask_round(a, b, src, 0, _MM_FROUND= _NO_EXC); + return (int)res[0]; +} + +int bug4(void) { + v4di ints4 =3D {0, 1, 2, 3}; + unsigned long long *addr =3D malloc(sizeof(*addr)); + __builtin_ia32_pmovqw256mem_mask(addr, ints4, 0); +} + +int bug5(void) { + v2di ints4 =3D {0, 1}; + unsigned int *addr =3D malloc(sizeof(*addr)); + __builtin_ia32_pmovqw128mem_mask(addr, ints4, 0); +} --=20 2.34.2