From: <apinski@marvell.com>
To: <gcc-patches@gcc.gnu.org>
Cc: Andrew Pinski <apinski@marvell.com>
Subject: [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand
Date: Thu, 18 Aug 2022 15:03:52 -0700 [thread overview]
Message-ID: <1660860233-11175-10-git-send-email-apinski@marvell.com> (raw)
In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com>
From: Andrew Pinski <apinski@marvell.com>
Like a previous patch, just add constraints for predicates
not_single_bit_mask_operand and single_bit_mask_operand.
OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DbS): New constraint.
(DnS): New constraint.
* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
(*bclr<mode>): Likewise.
(*binvi<mode>): Likewise.
---
gcc/config/riscv/bitmanip.md | 6 +++---
gcc/config/riscv/constraints.md | 10 ++++++++++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d362f526e79..026299d6703 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -300,7 +300,7 @@ (define_insn "*bset<mode>_1_mask"
(define_insn "*bseti<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(ior:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
@@ -317,7 +317,7 @@ (define_insn "*bclr<mode>"
(define_insn "*bclri<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "not_single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
"TARGET_ZBS"
"bclri\t%0,%1,%T2"
[(set_attr "type" "bitmanip")])
@@ -334,7 +334,7 @@ (define_insn "*binv<mode>"
(define_insn "*binvi<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(xor:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"binvi\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 444870ad060..2873d533cb5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -72,6 +72,16 @@ (define_constraint "DsD"
(and (match_code "const_int")
(match_test "ival == 63")))
+(define_constraint "DbS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (ival)")))
+
+(define_constraint "DnS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
--
2.27.0
next prev parent reply other threads:[~2022-08-18 22:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
2022-08-22 8:47 ` Kito Cheng
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
2022-08-18 22:03 ` apinski [this message]
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
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