From: <apinski@marvell.com>
To: <gcc-patches@gcc.gnu.org>
Cc: Andrew Pinski <apinski@marvell.com>
Subject: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
Date: Thu, 18 Aug 2022 15:03:53 -0700 [thread overview]
Message-ID: <1660860233-11175-11-git-send-email-apinski@marvell.com> (raw)
In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com>
From: Andrew Pinski <apinski@marvell.com>
The constraints should be n instead of i. Also there
needs to a check for out of bounds zero_extract for
*bexti.
gcc/ChangeLog:
PR target/106632
PR target/106588
* config/riscv/bitmanip.md (*shNadduw): Use n constraint
instead of i.
(*slliuw): Likewise.
(*bexti): Likewise. Also add a check for operands[2] to be less
than the mode bitsize.
---
gcc/config/riscv/bitmanip.md | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 026299d6703..ecf5b51b533 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -44,7 +44,7 @@ (define_insn "*shNadduw"
(plus:DI
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "imm123_operand" "Ds3"))
- (match_operand 3 "immediate_operand" ""))
+ (match_operand 3 "immediate_operand" "n"))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT && TARGET_ZBA
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
@@ -110,7 +110,7 @@ (define_insn "*slliuw"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "I"))
- (match_operand 3 "immediate_operand" "")))]
+ (match_operand 3 "immediate_operand" "n")))]
"TARGET_64BIT && TARGET_ZBA
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
"slli.uw\t%0,%1,%2"
@@ -354,6 +354,7 @@ (define_insn "*bexti"
(zero_extract:X (match_operand:X 1 "register_operand" "r")
(const_int 1)
(match_operand 2 "immediate_operand" "i")))]
- "TARGET_ZBS"
+ (match_operand 2 "immediate_operand" "n")))]
+ "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
"bexti\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
--
2.27.0
next prev parent reply other threads:[~2022-08-18 22:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
2022-08-22 8:47 ` Kito Cheng
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
2022-08-18 22:03 ` apinski [this message]
2022-08-22 9:09 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
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