* [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
` (9 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
This moves the iterators out from riscv.md to iterators.md
like most modern backends.
I have not moved the iterators from the other .md files yet.
OK? Build and tested on riscv64-linux-gnu and riscv32-linux-gnu.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/riscv.md
(GPR): Move to new file.
(P, X, BR): Likewise.
(MOVE32, MOVE64, SHORT): Likewise.
(HISI, SUPERQI, SUBX): Likewise.
(ANYI, ANYF, SOFTF): Likewise.
(size, load, default_load): Likewise.
(softload, store, softstore): Likewise.
(reg, fmt, ifmt, amo): Likewise.
(UNITMODE, HALFMODE): Likewise.
(RINT, rint_pattern, rint_rm): Likewise.
(QUIET_COMPARISON, quiet_pattern, QUIET_PATTERN): Likewise.
(any_extend, any_shiftrt, any_shift): Likewise.
(any_bitwise): Likewise.
(any_div, any_mod): Likewise.
(any_gt, any_ge, any_lt, any_le): Likewise.
(u, su): Likewise.
(optab, insn): Likewise.
* config/riscv/iterators.md: New file.
---
gcc/config/riscv/iterators.md | 212 ++++++++++++++++++++++++++++++++++
1 file changed, 212 insertions(+)
create mode 100644 gcc/config/riscv/iterators.md
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
new file mode 100644
index 00000000000..351aa7f3cea
--- /dev/null
+++ b/gcc/config/riscv/iterators.md
@@ -0,0 +1,212 @@
+;; Iterators for the machine description for RISC-V
+;; Copyright (C) 2011-2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; -------------------------------------------------------------------
+;; Mode Iterators
+;; -------------------------------------------------------------------
+
+;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
+;; from the same template.
+(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
+
+;; This mode iterator allows :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
+;; Likewise, but for XLEN-sized quantities.
+(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
+
+;; Branches operate on XLEN-sized quantities, but for RV64 we accept
+;; QImode values so we can force zero-extension.
+(define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")])
+
+;; 32-bit moves for which we provide move patterns.
+(define_mode_iterator MOVE32 [SI])
+
+;; 64-bit modes for which we provide move patterns.
+(define_mode_iterator MOVE64 [DI DF])
+
+;; Iterator for sub-32-bit integer modes.
+(define_mode_iterator SHORT [QI HI])
+
+;; Iterator for HImode constant generation.
+(define_mode_iterator HISI [HI SI])
+
+;; Iterator for QImode extension patterns.
+(define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")])
+
+;; Iterator for hardware integer modes narrower than XLEN.
+(define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])
+
+;; Iterator for hardware-supported integer modes.
+(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
+
+;; Iterator for hardware-supported floating-point modes.
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_DOUBLE_FLOAT")
+ (HF "TARGET_ZFH")])
+
+;; Iterator for floating-point modes that can be loaded into X registers.
+(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
+
+
+;; -------------------------------------------------------------------
+;; Mode attributes
+;; -------------------------------------------------------------------
+
+
+;; This attribute gives the length suffix for a sign- or zero-extension
+;; instruction.
+(define_mode_attr size [(QI "b") (HI "h")])
+
+;; Mode attributes for loads.
+(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (HF "flh") (DF "fld")])
+
+;; Instruction names for integer loads that aren't explicitly sign or zero
+;; extended. See riscv_output_move and LOAD_EXTEND_OP.
+(define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
+
+;; Mode attribute for FP loads into integer registers.
+(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
+
+;; Instruction names for stores.
+(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") (SF "fsw") (DF "fsd")])
+
+;; Instruction names for FP stores from integer registers.
+(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
+
+;; This attribute gives the best constraint to use for registers of
+;; a given mode.
+(define_mode_attr reg [(SI "d") (DI "d") (CC "d")])
+
+;; This attribute gives the format suffix for floating-point operations.
+(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")])
+
+;; This attribute gives the integer suffix for floating-point conversions.
+(define_mode_attr ifmt [(SI "w") (DI "l")])
+
+;; This attribute gives the format suffix for atomic memory operations.
+(define_mode_attr amo [(SI "w") (DI "d")])
+
+;; This attribute gives the upper-case mode name for one unit of a
+;; floating-point mode.
+(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
+
+;; This attribute gives the integer mode that has half the size of
+;; the controlling mode.
+(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
+
+;; -------------------------------------------------------------------
+;; Code Iterators
+;; -------------------------------------------------------------------
+
+;; This code iterator allows signed and unsigned widening multiplications
+;; to use the same template.
+(define_code_iterator any_extend [sign_extend zero_extend])
+
+;; This code iterator allows the two right shift instructions to be
+;; generated from the same template.
+(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
+
+;; This code iterator allows the three shift instructions to be generated
+;; from the same template.
+(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
+
+;; This code iterator allows the three bitwise instructions to be generated
+;; from the same template.
+(define_code_iterator any_bitwise [and ior xor])
+
+;; This code iterator allows unsigned and signed division to be generated
+;; from the same template.
+(define_code_iterator any_div [div udiv mod umod])
+
+;; This code iterator allows unsigned and signed modulus to be generated
+;; from the same template.
+(define_code_iterator any_mod [mod umod])
+
+;; These code iterators allow the signed and unsigned scc operations to use
+;; the same template.
+(define_code_iterator any_gt [gt gtu])
+(define_code_iterator any_ge [ge geu])
+(define_code_iterator any_lt [lt ltu])
+(define_code_iterator any_le [le leu])
+
+;; -------------------------------------------------------------------
+;; Code Attributes
+;; -------------------------------------------------------------------
+
+
+;; <u> expands to an empty string when doing a signed operation and
+;; "u" when doing an unsigned operation.
+(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (gt "") (gtu "u")
+ (ge "") (geu "u")
+ (lt "") (ltu "u")
+ (le "") (leu "u")])
+
+;; <su> is like <u>, but the signed form expands to "s" rather than "".
+(define_code_attr su [(sign_extend "s") (zero_extend "u")])
+
+;; <optab> expands to the name of the optab for a particular code.
+(define_code_attr optab [(ashift "ashl")
+ (ashiftrt "ashr")
+ (lshiftrt "lshr")
+ (div "div")
+ (mod "mod")
+ (udiv "udiv")
+ (umod "umod")
+ (ge "ge")
+ (le "le")
+ (gt "gt")
+ (lt "lt")
+ (ior "ior")
+ (xor "xor")
+ (and "and")
+ (plus "add")
+ (minus "sub")])
+
+;; <insn> expands to the name of the insn that implements a particular code.
+(define_code_attr insn [(ashift "sll")
+ (ashiftrt "sra")
+ (lshiftrt "srl")
+ (div "div")
+ (mod "rem")
+ (udiv "divu")
+ (umod "remu")
+ (ior "or")
+ (xor "xor")
+ (and "and")
+ (plus "add")
+ (minus "sub")])
+
+;; -------------------------------------------------------------------
+;; Int Iterators.
+;; -------------------------------------------------------------------
+
+;; Iterator and attributes for floating-point rounding instructions.
+(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND])
+(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")])
+(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")])
+
+;; Iterator and attributes for quiet comparisons.
+(define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
+(define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")])
+(define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") (UNSPEC_FLE_QUIET "LE")])
+
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 02/10] [RISCV] Move iterators from bitmanip.md to iterators.md
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
Just like the previous patch this move all of the iterators
of bitmanip.md to iterators.md. All modern backends put the
iterators in iterators.md for easier access.
OK? Built and tested for riscv32-linux-gnu with --with-arch=rv32imafdc_zba_zbb_zbc_zbs.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/bitmanip.md
(bitmanip_bitwise, bitmanip_minmax, clz_ctz_pcna, tbitmanip_optab,
bitmanip_insn, shiftm1: Move to ...
* config/riscv/iterators.md: Here.
---
gcc/config/riscv/bitmanip.md | 25 -------------------------
gcc/config/riscv/iterators.md | 27 ++++++++++++++++++++++++++-
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d1570ce8508..3329dd54eb6 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -17,31 +17,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-(define_code_iterator bitmanip_bitwise [and ior])
-
-(define_code_iterator bitmanip_minmax [smin umin smax umax])
-
-(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
-
-(define_code_attr bitmanip_optab [(smin "smin")
- (smax "smax")
- (umin "umin")
- (umax "umax")
- (clz "clz")
- (ctz "ctz")
- (popcount "popcount")])
-
-
-(define_code_attr bitmanip_insn [(smin "min")
- (smax "max")
- (umin "minu")
- (umax "maxu")
- (clz "clz")
- (ctz "ctz")
- (popcount "cpop")])
-
-(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
-
;; ZBA extension.
(define_insn "*zero_extendsidi2_bitmanip"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 351aa7f3cea..54590f43193 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -113,6 +113,9 @@ (define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
;; the controlling mode.
(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
+; bitmanip mode attribute
+(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+
;; -------------------------------------------------------------------
;; Code Iterators
;; -------------------------------------------------------------------
@@ -148,11 +151,17 @@ (define_code_iterator any_ge [ge geu])
(define_code_iterator any_lt [lt ltu])
(define_code_iterator any_le [le leu])
+; bitmanip code iterators
+(define_code_iterator bitmanip_bitwise [and ior])
+
+(define_code_iterator bitmanip_minmax [smin umin smax umax])
+
+(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
+
;; -------------------------------------------------------------------
;; Code Attributes
;; -------------------------------------------------------------------
-
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
(define_code_attr u [(sign_extend "") (zero_extend "u")
@@ -196,6 +205,22 @@ (define_code_attr insn [(ashift "sll")
(plus "add")
(minus "sub")])
+; bitmanip code attributes
+(define_code_attr bitmanip_optab [(smin "smin")
+ (smax "smax")
+ (umin "umin")
+ (umax "umax")
+ (clz "clz")
+ (ctz "ctz")
+ (popcount "popcount")])
+(define_code_attr bitmanip_insn [(smin "min")
+ (smax "max")
+ (umin "minu")
+ (umax "maxu")
+ (clz "clz")
+ (ctz "ctz")
+ (popcount "cpop")])
+
;; -------------------------------------------------------------------
;; Int Iterators.
;; -------------------------------------------------------------------
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 03/10] [RISCV] Move iterators from sync.md to iterators.md
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
Like the previous two patches this moves the iterators
that are in sync.md to iterators.md.
OK? build and tested for riscv64-linux-gnu.
gcc/ChangeLog:
* config/riscv/sync.md (any_atomic, atomic_optab): Move to ...
* config/riscv/iterators.md: Here.
---
gcc/config/riscv/iterators.md | 7 +++++++
gcc/config/riscv/sync.md | 4 ----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 54590f43193..6c8a6d2dd59 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -151,6 +151,9 @@ (define_code_iterator any_ge [ge geu])
(define_code_iterator any_lt [lt ltu])
(define_code_iterator any_le [le leu])
+; atomics code iterator
+(define_code_iterator any_atomic [plus ior xor and])
+
; bitmanip code iterators
(define_code_iterator bitmanip_bitwise [and ior])
@@ -205,6 +208,10 @@ (define_code_attr insn [(ashift "sll")
(plus "add")
(minus "sub")])
+; atomics code attribute
+(define_code_attr atomic_optab
+ [(plus "add") (ior "or") (xor "xor") (and "and")])
+
; bitmanip code attributes
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 86b41e6b00a..7deb290d9dc 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -27,10 +27,6 @@ (define_c_enum "unspec" [
UNSPEC_MEMORY_BARRIER
])
-(define_code_iterator any_atomic [plus ior xor and])
-(define_code_attr atomic_optab
- [(plus "add") (ior "or") (xor "xor") (and "and")])
-
;; Memory barriers.
(define_expand "mem_thread_fence"
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (2 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
To make it easier to find operands modifiers while in the md
file, add the list of modifiers to the top of the md file.
This is similar to i386 target.
OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Make a mention to
keep the list in riscv.md in sync with this list.
* config/riscv/riscv.md: Add list of modifiers as comments.
---
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 184 ++++----------------------------------
2 files changed, 18 insertions(+), 170 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7c120eaa8e3..189be5e4e6f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3730,7 +3730,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
- 'T' Print shift-index of inverted single-bit mask OP. */
+ 'T' Print shift-index of inverted single-bit mask OP.
+
+ Note please keep this list and the list in riscv.md in sync. */
static void
riscv_print_operand (FILE *file, rtx op, int letter)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f4a5ff07fe4..aad2836d179 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -19,6 +19,20 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+
+;; Keep this list and the one above riscv_print_operand in sync.
+;; The special asm out single letter directives following a '%' are:
+;; h -- Print the high-part relocation associated with OP, after stripping
+;; any outermost HIGH.
+;; R -- Print the low-part relocation associated with OP.
+;; C -- Print the integer branch condition for comparison OP.
+;; A -- Print the atomic operation suffix for memory model OP.
+;; F -- Print a FENCE if the memory model requires a release.
+;; z -- Print x0 if OP is zero, otherwise print OP normally.
+;; i -- Print i if the operand is not a register.
+;; S -- Print shift-index of single-bit mask OP.
+;; T -- Print shift-index of inverted single-bit mask OP.
+
(define_c_enum "unspec" [
;; Override return address for exception handling.
UNSPEC_EH_RETURN
@@ -107,6 +121,7 @@ (define_constants
(include "predicates.md")
(include "constraints.md")
+(include "iterators.md")
;; ....................
;;
@@ -269,175 +284,6 @@ (define_attr "tune"
(define_asm_attributes
[(set_attr "type" "multi")])
-;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
-;; from the same template.
-(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
-
-;; This mode iterator allows :P to be used for patterns that operate on
-;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-
-;; Likewise, but for XLEN-sized quantities.
-(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
-
-;; Branches operate on XLEN-sized quantities, but for RV64 we accept
-;; QImode values so we can force zero-extension.
-(define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")])
-
-;; 32-bit moves for which we provide move patterns.
-(define_mode_iterator MOVE32 [SI])
-
-;; 64-bit modes for which we provide move patterns.
-(define_mode_iterator MOVE64 [DI DF])
-
-;; Iterator for sub-32-bit integer modes.
-(define_mode_iterator SHORT [QI HI])
-
-;; Iterator for HImode constant generation.
-(define_mode_iterator HISI [HI SI])
-
-;; Iterator for QImode extension patterns.
-(define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")])
-
-;; Iterator for hardware integer modes narrower than XLEN.
-(define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])
-
-;; Iterator for hardware-supported integer modes.
-(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
-
-;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")
- (HF "TARGET_ZFH")])
-
-;; Iterator for floating-point modes that can be loaded into X registers.
-(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
-
-;; This attribute gives the length suffix for a sign- or zero-extension
-;; instruction.
-(define_mode_attr size [(QI "b") (HI "h")])
-
-;; Mode attributes for loads.
-(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") (SF "flw") (DF "fld")])
-
-;; Instruction names for integer loads that aren't explicitly sign or zero
-;; extended. See riscv_output_move and LOAD_EXTEND_OP.
-(define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
-
-;; Mode attribute for FP loads into integer registers.
-(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
-
-;; Instruction names for stores.
-(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") (SF "fsw") (DF "fsd")])
-
-;; Instruction names for FP stores from integer registers.
-(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
-
-;; This attribute gives the best constraint to use for registers of
-;; a given mode.
-(define_mode_attr reg [(SI "d") (DI "d") (CC "d")])
-
-;; This attribute gives the format suffix for floating-point operations.
-(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")])
-
-;; This attribute gives the integer suffix for floating-point conversions.
-(define_mode_attr ifmt [(SI "w") (DI "l")])
-
-;; This attribute gives the format suffix for atomic memory operations.
-(define_mode_attr amo [(SI "w") (DI "d")])
-
-;; This attribute gives the upper-case mode name for one unit of a
-;; floating-point mode.
-(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
-
-;; This attribute gives the integer mode that has half the size of
-;; the controlling mode.
-(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
-
-;; Iterator and attributes for floating-point rounding instructions.
-(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND])
-(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")])
-(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")])
-
-;; Iterator and attributes for quiet comparisons.
-(define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
-(define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")])
-(define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") (UNSPEC_FLE_QUIET "LE")])
-
-;; This code iterator allows signed and unsigned widening multiplications
-;; to use the same template.
-(define_code_iterator any_extend [sign_extend zero_extend])
-
-;; This code iterator allows the two right shift instructions to be
-;; generated from the same template.
-(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
-
-;; This code iterator allows the three shift instructions to be generated
-;; from the same template.
-(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
-
-;; This code iterator allows the three bitwise instructions to be generated
-;; from the same template.
-(define_code_iterator any_bitwise [and ior xor])
-
-;; This code iterator allows unsigned and signed division to be generated
-;; from the same template.
-(define_code_iterator any_div [div udiv mod umod])
-
-;; This code iterator allows unsigned and signed modulus to be generated
-;; from the same template.
-(define_code_iterator any_mod [mod umod])
-
-;; These code iterators allow the signed and unsigned scc operations to use
-;; the same template.
-(define_code_iterator any_gt [gt gtu])
-(define_code_iterator any_ge [ge geu])
-(define_code_iterator any_lt [lt ltu])
-(define_code_iterator any_le [le leu])
-
-;; <u> expands to an empty string when doing a signed operation and
-;; "u" when doing an unsigned operation.
-(define_code_attr u [(sign_extend "") (zero_extend "u")
- (gt "") (gtu "u")
- (ge "") (geu "u")
- (lt "") (ltu "u")
- (le "") (leu "u")])
-
-;; <su> is like <u>, but the signed form expands to "s" rather than "".
-(define_code_attr su [(sign_extend "s") (zero_extend "u")])
-
-;; <optab> expands to the name of the optab for a particular code.
-(define_code_attr optab [(ashift "ashl")
- (ashiftrt "ashr")
- (lshiftrt "lshr")
- (div "div")
- (mod "mod")
- (udiv "udiv")
- (umod "umod")
- (ge "ge")
- (le "le")
- (gt "gt")
- (lt "lt")
- (ior "ior")
- (xor "xor")
- (and "and")
- (plus "add")
- (minus "sub")])
-
-;; <insn> expands to the name of the insn that implements a particular code.
-(define_code_attr insn [(ashift "sll")
- (ashiftrt "sra")
- (lshiftrt "srl")
- (div "div")
- (mod "rem")
- (udiv "divu")
- (umod "remu")
- (ior "or")
- (xor "xor")
- (and "and")
- (plus "add")
- (minus "sub")])
-
;; Ghost instructions produce no real code and introduce no hazards.
;; They exist purely to express an effect on dataflow.
(define_insn_reservation "ghost" 0
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (3 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
To make things easier and more maintainable, we need to
add support printing out w if TARGET_64BIT so this patch
adds %~ to do that, similar how the x86 backend uses %~
to print out i/f for TARGET_AVX2. We could have chosen any
punctuation symbol but ~ looks the closest to w.
OK? Build and tested for riscv64-linux-gnu and riscv32-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand):
Handle '~'.
(riscv_print_operand_punct_valid_p): New function
(TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define.
* config/riscv/bitmanip.md (<bitmanip_optab>si2/clz_ctz_pcnt):
Use %~ instead of conditional the pattern on TARGET_64BIT.
(rotrsi3): Likewise.
(rotlsi3): Likewise.
* config/riscv/riscv.md: Add ~ to the list of modifiers.
(addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT.
(subsi3): Likewise.
(negsi2): Likewise.
(mulsi3): Likewise.
(optab>si3/any_div): Likewise.
(*add<mode>hi3): Likewise.
(<optab>si3/any_shift): Likewise.
---
gcc/config/riscv/bitmanip.md | 6 +++---
gcc/config/riscv/riscv.cc | 19 +++++++++++++++++++
gcc/config/riscv/riscv.md | 15 ++++++++-------
3 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 3329dd54eb6..ebd6eee1a22 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -143,7 +143,7 @@ (define_insn "<bitmanip_optab>si2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
+ "<bitmanip_insn>%~\t%0,%1"
[(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
@@ -201,7 +201,7 @@ (define_insn "rotrsi3"
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "arith_operand" "rI")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
+ "ror%i2%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
(define_insn "rotrdi3"
@@ -225,7 +225,7 @@ (define_insn "rotlsi3"
(rotate:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
+ "rol%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
(define_insn "rotldi3"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 189be5e4e6f..22d0f6d604c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3731,12 +3731,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
'T' Print shift-index of inverted single-bit mask OP.
+ '~' Print w if TARGET_64BIT is true; otherwise not print anything.
Note please keep this list and the list in riscv.md in sync. */
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
+ /* `~` does not take an operand so op will be null
+ Check for before accessing op.
+ */
+ if (letter == '~')
+ {
+ if (TARGET_64BIT)
+ fputc('w', file);
+ return;
+ }
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
@@ -3812,6 +3822,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
}
}
+/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */
+static bool
+riscv_print_operand_punct_valid_p (unsigned char code)
+{
+ return (code == '~');
+}
+
/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
static void
@@ -5900,6 +5917,8 @@ riscv_init_libfuncs (void)
#define TARGET_PRINT_OPERAND riscv_print_operand
#undef TARGET_PRINT_OPERAND_ADDRESS
#define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
+#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
+#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index aad2836d179..30cd07dc6f5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -32,6 +32,7 @@
;; i -- Print i if the operand is not a register.
;; S -- Print shift-index of single-bit mask OP.
;; T -- Print shift-index of inverted single-bit mask OP.
+;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything.
(define_c_enum "unspec" [
;; Override return address for exception handling.
@@ -312,7 +313,7 @@ (define_insn "addsi3"
(plus:SI (match_operand:SI 1 "register_operand" " r,r")
(match_operand:SI 2 "arith_operand" " r,I")))]
""
- { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
+ "add%i2%~\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -452,7 +453,7 @@ (define_insn "subsi3"
(minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ")
(match_operand:SI 2 "register_operand" " r")))]
""
- { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; }
+ "sub%~\t%0,%z1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -568,7 +569,7 @@ (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" " r")))]
""
- { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; }
+ "neg%~\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -613,7 +614,7 @@ (define_insn "mulsi3"
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_MUL"
- { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
+ "mul%~\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -883,7 +884,7 @@ (define_insn "<optab>si3"
(any_div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_DIV"
- { return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2"; }
+ "<insn>%i2%~\t%0,%1,%2"
[(set_attr "type" "idiv")
(set_attr "mode" "SI")])
@@ -1605,7 +1606,7 @@ (define_insn "*add<mode>hi3"
(plus:HI (match_operand:HISI 1 "register_operand" " r,r")
(match_operand:HISI 2 "arith_operand" " r,I")))]
""
- { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
+ "add%i2%~\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "HI")])
@@ -1787,7 +1788,7 @@ (define_insn "<optab>si3"
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (SImode) - 1));
- return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2";
+ return "<insn>%i2%~\t%0,%1,%2";
}
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (4 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
@ 2022-08-18 22:03 ` apinski
2022-08-22 8:47 ` Kito Cheng
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
` (4 subsequent siblings)
10 siblings, 1 reply; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
This simplifies the code by adding a predicate and a constraint for 1/2/3.
The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
which they use there.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (Ds3): New constraint.
* config/riscv/predicates.md (imm123_operand): New predicate.
* config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
(*shNadduw): Likewise.
---
gcc/config/riscv/bitmanip.md | 8 +++-----
gcc/config/riscv/constraints.md | 6 ++++++
gcc/config/riscv/predicates.md | 5 +++++
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ebd6eee1a22..73a36f7751b 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip"
(define_insn "*shNadd"
[(set (match_operand:X 0 "register_operand" "=r")
(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "imm123_operand" "Ds3"))
(match_operand:X 3 "register_operand" "r")))]
- "TARGET_ZBA
- && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
+ "TARGET_ZBA"
"sh%2add\t%0,%1,%3"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<X:MODE>")])
@@ -44,11 +43,10 @@ (define_insn "*shNadduw"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:QI 2 "immediate_operand" "I"))
+ (match_operand:QI 2 "imm123_operand" "Ds3"))
(match_operand 3 "immediate_operand" ""))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT && TARGET_ZBA
- && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
"sh%2add.uw\t%0,%1,%4"
[(set_attr "type" "bitmanip")
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb..61b84875fd9 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -54,6 +54,12 @@ (define_constraint "L"
(and (match_code "const_int")
(match_test "LUI_OPERAND (ival)")))
+(define_constraint "Ds3"
+ "@internal
+ 1, 2 or 3 immediate"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, 1, 3)")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 79e0c1d5589..2af7f661d6f 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -244,6 +244,11 @@ (define_predicate "imm5_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) < 5")))
+;; A const_int for sh1add/sh2add/sh3add
+(define_predicate "imm123_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
+
;; A CONST_INT operand that consists of a single run of consecutive set bits.
(define_predicate "consecutive_bits_operand"
(match_code "const_int")
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
@ 2022-08-22 8:47 ` Kito Cheng
0 siblings, 0 replies; 15+ messages in thread
From: Kito Cheng @ 2022-08-22 8:47 UTC (permalink / raw)
To: apinski; +Cc: GCC Patches
I know using more precise constraints might result in better code gen
in some situations, but I am Curious what's the difference between the
using pattern condition and constraints/predicates in this case? Is
there any performance or code gen difference?
On Fri, Aug 19, 2022 at 6:07 AM apinski--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Andrew Pinski <apinski@marvell.com>
>
> This simplifies the code by adding a predicate and a constraint for 1/2/3.
> The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
> which they use there.
>
> OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.
>
> Thanks,
> Andrew Pinski
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md (Ds3): New constraint.
> * config/riscv/predicates.md (imm123_operand): New predicate.
> * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
> (*shNadduw): Likewise.
> ---
> gcc/config/riscv/bitmanip.md | 8 +++-----
> gcc/config/riscv/constraints.md | 6 ++++++
> gcc/config/riscv/predicates.md | 5 +++++
> 3 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index ebd6eee1a22..73a36f7751b 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip"
> (define_insn "*shNadd"
> [(set (match_operand:X 0 "register_operand" "=r")
> (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> - (match_operand:QI 2 "immediate_operand" "I"))
> + (match_operand:QI 2 "imm123_operand" "Ds3"))
> (match_operand:X 3 "register_operand" "r")))]
> - "TARGET_ZBA
> - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
> + "TARGET_ZBA"
> "sh%2add\t%0,%1,%3"
> [(set_attr "type" "bitmanip")
> (set_attr "mode" "<X:MODE>")])
> @@ -44,11 +43,10 @@ (define_insn "*shNadduw"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (plus:DI
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> - (match_operand:QI 2 "immediate_operand" "I"))
> + (match_operand:QI 2 "imm123_operand" "Ds3"))
> (match_operand 3 "immediate_operand" ""))
> (match_operand:DI 4 "register_operand" "r")))]
> "TARGET_64BIT && TARGET_ZBA
> - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> "sh%2add.uw\t%0,%1,%4"
> [(set_attr "type" "bitmanip")
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index bafa4188ccb..61b84875fd9 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -54,6 +54,12 @@ (define_constraint "L"
> (and (match_code "const_int")
> (match_test "LUI_OPERAND (ival)")))
>
> +(define_constraint "Ds3"
> + "@internal
> + 1, 2 or 3 immediate"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, 1, 3)")))
> +
> ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
> ;; not available in RV32.
> (define_constraint "G"
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 79e0c1d5589..2af7f661d6f 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -244,6 +244,11 @@ (define_predicate "imm5_operand"
> (and (match_code "const_int")
> (match_test "INTVAL (op) < 5")))
>
> +;; A const_int for sh1add/sh2add/sh3add
> +(define_predicate "imm123_operand"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
> +
> ;; A CONST_INT operand that consists of a single run of consecutive set bits.
> (define_predicate "consecutive_bits_operand"
> (match_code "const_int")
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (5 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
A constraint here just makes it easier to understand what the
operands are.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64).
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DsS): New constraint.
(DsD): New constraint.
* config/riscv/iterators.md (shiftm1c): New iterator.
* config/riscv/bitmanip.md (*bset<mode>_mask):
Use shiftm1c.
(*bset<mode>_1_mask): Likewise.
---
gcc/config/riscv/bitmanip.md | 4 ++--
gcc/config/riscv/constraints.md | 12 ++++++++++++
gcc/config/riscv/iterators.md | 1 +
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 73a36f7751b..d362f526e79 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -273,7 +273,7 @@ (define_insn "*bset<mode>_mask"
(ior:X (ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 2 "register_operand" "r")
- (match_operand 3 "<X:shiftm1>" "i")) 0))
+ (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
(match_operand:X 1 "register_operand" "r")))]
"TARGET_ZBS"
"bset\t%0,%1,%2"
@@ -292,7 +292,7 @@ (define_insn "*bset<mode>_1_mask"
(ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+ (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
"TARGET_ZBS"
"bset\t%0,x0,%1"
[(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 61b84875fd9..444870ad060 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -60,6 +60,18 @@ (define_constraint "Ds3"
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 1, 3)")))
+(define_constraint "DsS"
+ "@internal
+ 31 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 31")))
+
+(define_constraint "DsD"
+ "@internal
+ 63 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 63")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 6c8a6d2dd59..be0d5390307 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -115,6 +115,7 @@ (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
; bitmanip mode attribute
(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
;; -------------------------------------------------------------------
;; Code Iterators
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (6 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
` (2 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
The problem here is two fold. With RISCV32, 32bit
const_int are always signed extended to 64bit in HWI.
So that means for SINGLE_BIT_MASK_OPERAND, it should
mask off the upper bits to see it is a single bit
for !TARGET_64BIT.
Plus there are a few locations which forget to call
trunc_int_for_mode when generating a SImode constant
so they are not sign extended correctly for HWI.
The predicates single_bit_mask_operand and
not_single_bit_mask_operand need get the same handling
as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64.
Thanks,
Andrew Pinski
gcc/ChangeLog:
PR target/106586
* config/riscv/predicates.md (single_bit_mask_operand):
Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi.
(not_single_bit_mask_operand): Likewise.
* config/riscv/riscv.cc (riscv_build_integer_1): Don't special case
1<<31 for 32bits as it is already handled.
Call trunc_int_for_mode on the upper part after the subtraction.
(riscv_move_integer): Call trunc_int_for_mode before generating
the integer just make sure the constant has been sign extended
corectly.
(riscv_emit_int_compare): Call trunc_int_for_mode after doing the
addition for the new rhs.
* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT,
then mask off the upper 32bits of the HWI as it will be sign extended.
---
gcc/config/riscv/predicates.md | 4 ++--
gcc/config/riscv/riscv.cc | 12 +++++++++---
gcc/config/riscv/riscv.h | 4 +++-
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 2af7f661d6f..862e72b0983 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -226,11 +226,11 @@ (define_special_predicate "gpr_save_operation"
;; Predicates for the ZBS extension.
(define_predicate "single_bit_mask_operand"
(and (match_code "const_int")
- (match_test "pow2p_hwi (INTVAL (op))")))
+ (match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))")))
(define_predicate "not_single_bit_mask_operand"
(and (match_code "const_int")
- (match_test "pow2p_hwi (~INTVAL (op))")))
+ (match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))")))
(define_predicate "const31_operand"
(and (match_code "const_int")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 22d0f6d604c..026c69ce40d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -432,7 +432,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
sign-extended (negative) representation (-1 << 31) for the
value, if we want to build (1 << 31) in SImode. This will
then expand to an LUI instruction. */
- if (mode == SImode && value == (HOST_WIDE_INT_1U << 31))
+ if (TARGET_64BIT && mode == SImode && value == (HOST_WIDE_INT_1U << 31))
codes[0].value = (HOST_WIDE_INT_M1U << 31);
return 1;
@@ -445,7 +445,11 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
&& (mode != HImode
|| value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1)))
{
- alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode);
+ HOST_WIDE_INT upper_part = value - low_part;
+ if (mode != VOIDmode)
+ upper_part = trunc_int_for_mode (value - low_part, mode);
+
+ alt_cost = 1 + riscv_build_integer_1 (alt_codes, upper_part, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = PLUS;
@@ -1550,6 +1554,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
x = riscv_split_integer (value, mode);
else
{
+ codes[0].value = trunc_int_for_mode (codes[0].value, mode);
/* Apply each binary operation to X. */
x = GEN_INT (codes[0].value);
@@ -1559,7 +1564,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
x = riscv_emit_set (temp, x);
else
x = force_reg (mode, x);
-
+ codes[i].value = trunc_int_for_mode (codes[i].value, mode);
x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
}
}
@@ -2651,6 +2656,7 @@ riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1)
continue;
new_rhs = rhs + (increment ? 1 : -1);
+ new_rhs = trunc_int_for_mode (new_rhs, GET_MODE (*op0));
if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs)
&& (rhs < 0) == (new_rhs < 0))
{
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4b07c5487c6..5394776eb50 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -535,7 +535,9 @@ enum reg_class
/* If this is a single bit mask, then we can load it with bseti. Special
handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
#define SINGLE_BIT_MASK_OPERAND(VALUE) \
- (pow2p_hwi (VALUE))
+ (pow2p_hwi (TARGET_64BIT \
+ ? (VALUE) \
+ : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
/* Stack layout; function entry, exit and calling. */
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (7 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
@ 2022-08-18 22:03 ` apinski
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
10 siblings, 0 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
Like a previous patch, just add constraints for predicates
not_single_bit_mask_operand and single_bit_mask_operand.
OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DbS): New constraint.
(DnS): New constraint.
* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
(*bclr<mode>): Likewise.
(*binvi<mode>): Likewise.
---
gcc/config/riscv/bitmanip.md | 6 +++---
gcc/config/riscv/constraints.md | 10 ++++++++++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d362f526e79..026299d6703 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -300,7 +300,7 @@ (define_insn "*bset<mode>_1_mask"
(define_insn "*bseti<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(ior:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
@@ -317,7 +317,7 @@ (define_insn "*bclr<mode>"
(define_insn "*bclri<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "not_single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
"TARGET_ZBS"
"bclri\t%0,%1,%T2"
[(set_attr "type" "bitmanip")])
@@ -334,7 +334,7 @@ (define_insn "*binv<mode>"
(define_insn "*binvi<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(xor:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"binvi\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 444870ad060..2873d533cb5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -72,6 +72,16 @@ (define_constraint "DsD"
(and (match_code "const_int")
(match_test "ival == 63")))
+(define_constraint "DbS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (ival)")))
+
+(define_constraint "DnS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (8 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
@ 2022-08-18 22:03 ` apinski
2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
10 siblings, 2 replies; 15+ messages in thread
From: apinski @ 2022-08-18 22:03 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Pinski
From: Andrew Pinski <apinski@marvell.com>
The constraints should be n instead of i. Also there
needs to a check for out of bounds zero_extract for
*bexti.
gcc/ChangeLog:
PR target/106632
PR target/106588
* config/riscv/bitmanip.md (*shNadduw): Use n constraint
instead of i.
(*slliuw): Likewise.
(*bexti): Likewise. Also add a check for operands[2] to be less
than the mode bitsize.
---
gcc/config/riscv/bitmanip.md | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 026299d6703..ecf5b51b533 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -44,7 +44,7 @@ (define_insn "*shNadduw"
(plus:DI
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "imm123_operand" "Ds3"))
- (match_operand 3 "immediate_operand" ""))
+ (match_operand 3 "immediate_operand" "n"))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT && TARGET_ZBA
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
@@ -110,7 +110,7 @@ (define_insn "*slliuw"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "I"))
- (match_operand 3 "immediate_operand" "")))]
+ (match_operand 3 "immediate_operand" "n")))]
"TARGET_64BIT && TARGET_ZBA
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
"slli.uw\t%0,%1,%2"
@@ -354,6 +354,7 @@ (define_insn "*bexti"
(zero_extract:X (match_operand:X 1 "register_operand" "r")
(const_int 1)
(match_operand 2 "immediate_operand" "i")))]
- "TARGET_ZBS"
+ (match_operand 2 "immediate_operand" "n")))]
+ "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
"bexti\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
--
2.27.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
@ 2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
1 sibling, 0 replies; 15+ messages in thread
From: Kito Cheng @ 2022-08-22 9:09 UTC (permalink / raw)
To: apinski; +Cc: GCC Patches
On Fri, Aug 19, 2022 at 6:08 AM apinski--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Andrew Pinski <apinski@marvell.com>
>
> The constraints should be n instead of i. Also there
> needs to a check for out of bounds zero_extract for
> *bexti.
>
> gcc/ChangeLog:
>
> PR target/106632
> PR target/106588
> * config/riscv/bitmanip.md (*shNadduw): Use n constraint
> instead of i.
> (*slliuw): Likewise.
> (*bexti): Likewise. Also add a check for operands[2] to be less
> than the mode bitsize.
> ---
> gcc/config/riscv/bitmanip.md | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index 026299d6703..ecf5b51b533 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -44,7 +44,7 @@ (define_insn "*shNadduw"
> (plus:DI
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> (match_operand:QI 2 "imm123_operand" "Ds3"))
> - (match_operand 3 "immediate_operand" ""))
> + (match_operand 3 "immediate_operand" "n"))
> (match_operand:DI 4 "register_operand" "r")))]
> "TARGET_64BIT && TARGET_ZBA
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> @@ -110,7 +110,7 @@ (define_insn "*slliuw"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> (match_operand:QI 2 "immediate_operand" "I"))
> - (match_operand 3 "immediate_operand" "")))]
> + (match_operand 3 "immediate_operand" "n")))]
> "TARGET_64BIT && TARGET_ZBA
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> "slli.uw\t%0,%1,%2"
> @@ -354,6 +354,7 @@ (define_insn "*bexti"
> (zero_extract:X (match_operand:X 1 "register_operand" "r")
> (const_int 1)
> (match_operand 2 "immediate_operand" "i")))]
Seems something wrong during generating this patch, this line should be removed.
> - "TARGET_ZBS"
> + (match_operand 2 "immediate_operand" "n")))]
> + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
> "bexti\t%0,%1,%2"
> [(set_attr "type" "bitmanip")])
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 9:09 ` Kito Cheng
@ 2022-08-22 20:44 ` Palmer Dabbelt
1 sibling, 0 replies; 15+ messages in thread
From: Palmer Dabbelt @ 2022-08-22 20:44 UTC (permalink / raw)
To: gcc-patches; +Cc: gcc-patches, apinski
On Thu, 18 Aug 2022 15:03:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> From: Andrew Pinski <apinski@marvell.com>
>
> The constraints should be n instead of i. Also there
> needs to a check for out of bounds zero_extract for
> *bexti.
>
> gcc/ChangeLog:
>
> PR target/106632
> PR target/106588
> * config/riscv/bitmanip.md (*shNadduw): Use n constraint
> instead of i.
> (*slliuw): Likewise.
> (*bexti): Likewise. Also add a check for operands[2] to be less
> than the mode bitsize.
> ---
> gcc/config/riscv/bitmanip.md | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index 026299d6703..ecf5b51b533 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -44,7 +44,7 @@ (define_insn "*shNadduw"
> (plus:DI
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> (match_operand:QI 2 "imm123_operand" "Ds3"))
> - (match_operand 3 "immediate_operand" ""))
> + (match_operand 3 "immediate_operand" "n"))
> (match_operand:DI 4 "register_operand" "r")))]
> "TARGET_64BIT && TARGET_ZBA
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> @@ -110,7 +110,7 @@ (define_insn "*slliuw"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> (match_operand:QI 2 "immediate_operand" "I"))
> - (match_operand 3 "immediate_operand" "")))]
> + (match_operand 3 "immediate_operand" "n")))]
> "TARGET_64BIT && TARGET_ZBA
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> "slli.uw\t%0,%1,%2"
> @@ -354,6 +354,7 @@ (define_insn "*bexti"
> (zero_extract:X (match_operand:X 1 "register_operand" "r")
> (const_int 1)
> (match_operand 2 "immediate_operand" "i")))]
> - "TARGET_ZBS"
> + (match_operand 2 "immediate_operand" "n")))]
> + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
> "bexti\t%0,%1,%2"
> [(set_attr "type" "bitmanip")])
I think something went off the rails on that last chunk and it should
look more like
@@ -353,7 +353,7 @@
[(set (match_operand:X 0 "register_operand" "=r")
(zero_extract:X (match_operand:X 1 "register_operand" "r")
(const_int 1)
- (match_operand 2 "immediate_operand" "i")))]
- "TARGET_ZBS"
+ (match_operand 2 "immediate_operand" "n")))]
+ "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
"bexti\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
with that I get no new failures on trunk with all of these (though I'm
still only testing the Linux multilibs for now).
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/10] [RISCV] Fix/improve the RISCV backend
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
` (9 preceding siblings ...)
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
@ 2022-08-22 20:44 ` Palmer Dabbelt
10 siblings, 0 replies; 15+ messages in thread
From: Palmer Dabbelt @ 2022-08-22 20:44 UTC (permalink / raw)
To: gcc-patches; +Cc: gcc-patches, apinski
On Thu, 18 Aug 2022 15:03:43 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> From: Andrew Pinski <apinski@marvell.com>
>
> This set of patches fixes a few RISCV issues and does a few
> cleanups. Including moving all of the iterators to iterators.md like
> many newer backends.
> It also fixes a few PRs which I filed including the RISCV32 issue
> with ZBS enabled.
>
> Thanks,
> Andrew Pinski
>
> Andrew Pinski (10):
> [RISCV] Move iterators from riscv.md to iterators.md
> [RISCV] Move iterators from bitmanip.md to iterators.md
> [RISCV] Move iterators from sync.md to iterators.md
> [RISCV] Add the list of operand modifiers to riscv.md too
> [RISCV] Add %~ to print w if TARGET_64BIT and use it
> [RISCV] Use constraints/predicates instead of checking const_int
> directly for shNadd patterns
> [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask
> [RISCV] Fix PR 106586: riscv32 vs ZBS
> [RISCV] Add constraints for
> not_single_bit_mask_operand/single_bit_mask_operand
> [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
>
> gcc/config/riscv/bitmanip.md | 56 ++------
> gcc/config/riscv/constraints.md | 28 ++++
> gcc/config/riscv/iterators.md | 245 ++++++++++++++++++++++++++++++++
> gcc/config/riscv/predicates.md | 9 +-
> gcc/config/riscv/riscv.cc | 35 ++++-
> gcc/config/riscv/riscv.h | 4 +-
> gcc/config/riscv/riscv.md | 199 +++-----------------------
> gcc/config/riscv/sync.md | 4 -
> 8 files changed, 352 insertions(+), 228 deletions(-)
> create mode 100644 gcc/config/riscv/iterators.md
Aside from the minor issue I pointed out in my reply to 10, these all
look good to me. Thanks!
^ permalink raw reply [flat|nested] 15+ messages in thread