From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 77762389942F for ; Tue, 15 Nov 2022 05:01:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 77762389942F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=marvell.com Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AF50TqL011567 for ; Mon, 14 Nov 2022 21:01:54 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=kn15b/Kb2r8yfq1cXNJNpoc+xg5CW3gLC2xqcvZ8QnA=; b=UhA8Rrq+lZTdo+jw9RvUO14PeEq7YV/g8H+ze5TunTOeQu0HxwqoXloE61Hn1rm+ZH2W LNkQgUOpRj9mJ7TbuVZWsVMzNpuUsFsdEj/NM66XDYcgUPUnr6++jePFIw8fEhHZuaQm avChxrB9vu4QmoPyxcJb2H3FHwSg3KKpGPhZNiqY1HFub1JwyJBUJM6nQGYgq3KVqP9F LbrDY9OWB2jF1k9RQMBdc+wZEAKKMwQxYeqTL6g/PiIOtW6RNcOvitdrYK0Bm2CT5QSQ YiMZkdlYcT/qESIoesMkizPCgacmAcM8Zu0Q/ijHMc0rWSLGES0RLVts3mY2nFJw29Wl ZA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3kv487g057-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 14 Nov 2022 21:01:54 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Nov 2022 21:01:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Nov 2022 21:01:52 -0800 Received: from linux.marvell.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 889F63F7060; Mon, 14 Nov 2022 21:01:52 -0800 (PST) From: To: CC: Andrew Pinski Subject: [PATCH] Remove Score documentation Date: Mon, 14 Nov 2022 21:01:48 -0800 Message-ID: <1668488508-10524-1-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: dh6apMWG09yXXQNpf7XoqExtF7G6KoxQ X-Proofpoint-ORIG-GUID: dh6apMWG09yXXQNpf7XoqExtF7G6KoxQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-14_15,2022-11-11_01,2022-06-22_01 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Andrew Pinski Score target support was removed in r5-3909-g3daa7bbf791203 but it looks like some of the documentation was missed. This removes it. Committed as obvious after a "make html". Thanks, Andrew gcc/ChangeLog: * doc/invoke.texi: Remove Score option section. --- gcc/doc/invoke.texi | 52 ---------------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ef88f2a..55e8a14 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1316,13 +1316,6 @@ See RS/6000 and PowerPC Options. -mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol -mhotpatch=@var{halfwords},@var{halfwords}} -@emph{Score Options} -@gccoptlist{-meb -mel @gol --mnhwloop @gol --muls @gol --mmac @gol --mscore5 -mscore5u -mscore7 -mscore7d} - @emph{SH Options} @gccoptlist{-m1 -m2 -m2e @gol -m2a-nofpu -m2a-single-only -m2a-single -m2a @gol @@ -19726,7 +19719,6 @@ platform. * RS/6000 and PowerPC Options:: * RX Options:: * S/390 and zSeries Options:: -* Score Options:: * SH Options:: * Solaris 2 Options:: * SPARC Options:: @@ -30424,50 +30416,6 @@ This option can be overridden for individual functions with the @code{hotpatch} attribute. @end table -@node Score Options -@subsection Score Options -@cindex Score Options - -These options are defined for Score implementations: - -@table @gcctabopt -@item -meb -@opindex meb -Compile code for big-endian mode. This is the default. - -@item -mel -@opindex mel -Compile code for little-endian mode. - -@item -mnhwloop -@opindex mnhwloop -Disable generation of @code{bcnz} instructions. - -@item -muls -@opindex muls -Enable generation of unaligned load and store instructions. - -@item -mmac -@opindex mmac -Enable the use of multiply-accumulate instructions. Disabled by default. - -@item -mscore5 -@opindex mscore5 -Specify the SCORE5 as the target architecture. - -@item -mscore5u -@opindex mscore5u -Specify the SCORE5U of the target architecture. - -@item -mscore7 -@opindex mscore7 -Specify the SCORE7 as the target architecture. This is the default. - -@item -mscore7d -@opindex mscore7d -Specify the SCORE7D as the target architecture. -@end table - @node SH Options @subsection SH Options -- 1.8.3.1