From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 4B3B8387088C for ; Thu, 27 Aug 2020 20:47:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4B3B8387088C Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RKiQxO133719; Thu, 27 Aug 2020 16:47:24 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 336m4hg27v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:47:24 -0400 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 07RKjOUW142689; Thu, 27 Aug 2020 16:47:23 -0400 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 336m4hg273-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:47:23 -0400 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 07RKks2S009783; Thu, 27 Aug 2020 20:47:22 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma05wdc.us.ibm.com with ESMTP id 332uw7vs2b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 20:47:22 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07RKlGn364880986 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Aug 2020 20:47:16 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3AAC4BE058; Thu, 27 Aug 2020 20:47:21 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55997BE051; Thu, 27 Aug 2020 20:47:20 +0000 (GMT) Received: from sig-9-65-193-110.ibm.com (unknown [9.65.193.110]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2020 20:47:20 +0000 (GMT) Message-ID: <1696f9df157a3b64e4b0f67b00feb635d8807793.camel@vnet.ibm.com> Subject: Re: [PATCH 3/4] PowerPC: Add power10 xsmaxcqp/xsmincqp support From: will schmidt To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Date: Thu, 27 Aug 2020 15:47:19 -0500 In-Reply-To: <20200827024525.GC21803@ibm-toto.the-meissners.org> References: <20200827024142.GA15560@ibm-toto.the-meissners.org> <20200827024525.GC21803@ibm-toto.the-meissners.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_12:2020-08-27, 2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=4 bulkscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270151 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Aug 2020 20:47:26 -0000 On Wed, 2020-08-26 at 22:45 -0400, Michael Meissner via Gcc-patches wrote: > PowerPC: Add power10 xsmaxcqp/xsmincqp support. > > This patch adds support for the ISA 3.1 (power10) IEEE 128-bit "C" minimum and > maximum functions. Because of the NaN differences, the built-in functions will > only generate these instructions if -ffast-math is used until the conditional > move support is added in the next patch. > > I have built compilers on a little endian power9 Linux system with all 4 > patches applied. I did bootstrap builds and ran the testsuite, with no > regressions. Previous versions of the patch was also tested on a little endian > power8 Linux system. I would like to check this patch into the master branch > for GCC 11. At this time, I do not anticipate needing to backport these > changes to GCC 10.3. > > > gcc/ > 2020-08-26 Michael Meissner > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add 128-bit clause to if-check. > * config/rs6000/rs6000.h (FLOAT128_IEEE_MINMAX_P): New helper > macro. ok > * config/rs6000/rs6000.md (FSCALAR): New mode iterator for floating > point scalars. > (Fm): New mode attribute for floating point scalars. Mixed feels on mixed case, but I defer. :-) > (s): Add support for the ISA 3.1 IEEE 128-bit > minimum and maximum instructions. > (s3_vsx): Add support for the ISA 3.1 IEEE 128-bit > minimum and maximum instructions. > > gcc/testsuite/ > 2020-08-26 Michael Meissner > > * gcc.target/powerpc/float128-minmax-2.c: New test. > the rest lgtm, thanks -Will > --- > gcc/config/rs6000/rs6000.c | 3 +- > gcc/config/rs6000/rs6000.h | 4 +++ > gcc/config/rs6000/rs6000.md | 28 +++++++++++++++---- > .../gcc.target/powerpc/float128-minmax-2.c | 15 ++++++++++ > 4 files changed, 43 insertions(+), 7 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c > > diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c > index 6324f930628..05eb141a2cd 100644 > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -15445,7 +15445,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) > /* VSX/altivec have direct min/max insns. */ > if ((code == SMAX || code == SMIN) > && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) > - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)))) > + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)) > + || FLOAT128_IEEE_MINMAX_P (mode))) > { > emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1))); > return; > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index bbd8060e143..b504aaa0199 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -345,6 +345,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); > || ((MODE) == TDmode) \ > || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) > > +/* Macro whether the float128 min/max instructions are enabled. */ > +#define FLOAT128_IEEE_MINMAX_P(MODE) \ > + (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE)) > + > /* Return true for floating point that does not use a vector register. */ > #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ > (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 43b620ae1c0..006e60f09bc 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -789,6 +789,18 @@ (define_code_attr minmax [(smin "min") > (define_code_attr SMINMAX [(smin "SMIN") > (smax "SMAX")]) > > +;; Mode iterator for scalar binary floating point operations > +(define_mode_iterator FSCALAR [SF > + DF > + (KF "FLOAT128_IEEE_MINMAX_P (KFmode)") > + (TF "FLOAT128_IEEE_MINMAX_P (TFmode)")]) > + > +;; Constraints to use for scalar FP operations > +(define_mode_attr Fm [(SF "wa") > + (DF "wa") > + (TF "v") > + (KF "v")]) > + > ;; Iterator to optimize the following cases: > ;; D-form load to FPR register & move to Altivec register > ;; Move Altivec register to FPR register and store > @@ -5142,9 +5154,9 @@ (define_insn "copysign3_fcpsgn" > ;; to allow either DF/SF to use only traditional registers. > > (define_expand "s3" > - [(set (match_operand:SFDF 0 "gpc_reg_operand") > - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") > - (match_operand:SFDF 2 "gpc_reg_operand")))] > + [(set (match_operand:FSCALAR 0 "gpc_reg_operand") > + (fp_minmax:FSCALAR (match_operand:FSCALAR 1 "gpc_reg_operand") > + (match_operand:FSCALAR 2 "gpc_reg_operand")))] > "TARGET_MINMAX" > { > rs6000_emit_minmax (operands[0], , operands[1], operands[2]); > @@ -5152,11 +5164,15 @@ (define_expand "s3" > }) > > (define_insn "*s3_vsx" > - [(set (match_operand:SFDF 0 "vsx_register_operand" "=") > - (fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "") > - (match_operand:SFDF 2 "vsx_register_operand" "")))] > + [(set (match_operand:FSCALAR 0 "vsx_register_operand" "=") > + (fp_minmax:FSCALAR > + (match_operand:FSCALAR 1 "vsx_register_operand" "") > + (match_operand:FSCALAR 2 "vsx_register_operand" "")))] > "TARGET_VSX && TARGET_HARD_FLOAT" > { > + if (FLOAT128_IEEE_P (mode)) > + return "xscqp %0,%1,%2"; > + > return (TARGET_P9_MINMAX > ? "xscdp %x0,%x1,%x2" > : "xsdp %x0,%x1,%x2"); > diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c > new file mode 100644 > index 00000000000..c71ba08c9f8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c > @@ -0,0 +1,15 @@ > +/* { dg-require-effective-target ppc_float128_hw } */ > +/* { dg-require-effective-target power10_ok } */ > +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */ > + > +#ifndef TYPE > +#define TYPE _Float128 > +#endif > + > +/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a > + call. */ > +TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); } > +TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); } > + > +/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ > +/* { dg-final { scan-assembler {\mxsmincqp\M} } } */ > -- > 2.22.0 > >