I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>
for each instruction.

We can reference riscv.md:
(define_attr "ext_enabled" "no,yes"
  (cond [(eq_attr "ext" "base")
   (const_string "yes")

   (and (eq_attr "ext" "f")
        (match_test "TARGET_HARD_FLOAT"))
   (const_string "yes")

   (and (eq_attr "ext" "d")
        (match_test "TARGET_DOUBLE_FLOAT"))
   (const_string "yes")

   (and (eq_attr "ext" "vector")
        (match_test "TARGET_VECTOR"))
   (const_string "yes")
  ]
  (const_string "no")))

Define a new attribute as follows:
(define_attr "fp16_vector_enabled" "no,yes"
  (cond [
   (and (eq_attr "type" "vfalu")
(and eq_attr "mode" "VNx1HF")
        (match_test "!TARGET_ZVFH")))
   (const_string "no")
  ]
  (const_string "yes")))


I think you can do experiment with this to see whether it can disable MD pattern.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zhong@rivai.ai
CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?
 
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
  (VNx1HF "TARGET_ZVFH")
...
  (VNx1SF "1")
...
])
 
 
  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
  "TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
 
 
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h               |   1 +
> gcc/config/riscv/riscv-v.cc                   |  12 ++
> gcc/config/riscv/vector-iterators.md          |  23 +--
> gcc/config/riscv/vector.md                    | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c        |  15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec<location_t>, unsigned int,
>    tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
>   && IN_RANGE (INTVAL (elt), minval, maxval));
> }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> +   float point machine mode.  */
> +bool
> +float_mode_supported_p (machine_mode mode)
> +{
> +  machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> +  gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> +  return inner_mode == HFmode ? TARGET_ZVFH : true;
> +}
> +
> /* Return true if VEC is a constant in which every element is in the range
>     [MINVAL, MAXVAL].  The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
>    (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
>    (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> -  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> -  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> +  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
>    (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
>    (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
>    (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
>    (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
>    (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> +  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> +  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> +  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
>    (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
>    (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
>    (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> -  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> -  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> -  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> -  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> -  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> -  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> +  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> +  (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> +  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
>    (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>    (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
>   (vec_duplicate:VF
>     (match_operand:<VEL> 3 "direct_broadcast_operand"       " f,  f,Wdm,Wdm,Wdm,Wdm,  f,  f"))
>   (match_operand:VF 2 "vector_merge_operand"                "vu,  0, vu,  0, vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vfmv.v.f\t%0,%3
>     vfmv.v.f\t%0,%3
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr")
>     (match_operand:VF 4 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr")
>     (match_operand:VF 4 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
>       (match_operand:<VEL> 4 "register_operand"  "  f,  f,  f,  f"))
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
>       (match_operand:<VEL> 4 "register_operand"  "  f,  f,  f,  f"))
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
>     (vec_duplicate:VF
>       (match_operand:<VEL> 4 "register_operand"  "  f,  f,  f,  f")))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
>       (match_operand:<VEL> 4 "register_operand"  "  f,  f,  f,  f"))
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfr<insn>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
>     [(match_operand:VF 3 "register_operand"       " vr, vr, vr, vr")
>      (match_operand:VF 4 "register_operand"       " vr, vr, vr, vr")] VCOPYSIGNS)
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfsgnj<nx>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "vfsgnj")
>     (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
>      (vec_duplicate:VF
>        (match_operand:<VEL> 4 "register_operand" "  f,  f,  f,  f"))] VCOPYSIGNS)
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfsgnj<nx>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "vfsgnj")
>     (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
>       (match_operand:VF 3 "register_operand"     " vr,   vr, vr,   vr"))
>     (match_operand:VF 4 "register_operand"       " vr,   vr, vr,   vr"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<madd_msub>.vv\t%0,%3,%4%p1
>     vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
>       (match_operand:VF 3 "register_operand"     " vr,   vr, vr,   vr"))
>     (match_operand:VF 4 "register_operand"       "  0,   vr,  0,   vr"))
>   (match_dup 4)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<macc_msac>.vv\t%0,%2,%3%p1
>     vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
>       (match_operand:VF 3 "register_operand"     "   vr,   vr"))
>     (match_operand:VF 4 "vector_arith_operand"   "   vr,   vr"))
>   (match_operand:VF 5 "register_operand"         "    0,   vr")))]
> -  "TARGET_VECTOR
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
>     && !rtx_equal_p (operands[2], operands[5])
>     && !rtx_equal_p (operands[3], operands[5])
>     && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
>       (match_operand:VF 3 "register_operand"      "  0, vr,    0,   vr"))
>     (match_operand:VF 4 "register_operand"        " vr, vr,   vr,   vr"))
>   (match_dup 3)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<madd_msub>.vf\t%0,%2,%4%p1
>     vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
>       (match_operand:VF 3 "register_operand"      " vr, vr,   vr,   vr"))
>     (match_operand:VF 4 "register_operand"        "  0, vr,    0,   vr"))
>   (match_dup 4)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<macc_msac>.vf\t%0,%2,%3%p1
>     vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
>       (match_operand:VF 3 "register_operand"      "   vr,  vr"))
>     (match_operand:VF 4 "vector_arith_operand"    "   vr,  vr"))
>   (match_operand:VF 5 "register_operand"          "    0,  vr")))]
> -  "TARGET_VECTOR
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
>     && !rtx_equal_p (operands[3], operands[5])
>     && !rtx_equal_p (operands[4], operands[5])"
>    "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
>         (match_operand:VF 3 "register_operand"   " vr,   vr, vr,   vr")))
>     (match_operand:VF 4 "register_operand"       " vr,   vr, vr,   vr"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
>     vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
>         (match_operand:VF 3 "register_operand"   " vr,   vr, vr,   vr")))
>     (match_operand:VF 4 "register_operand"       "  0,   vr,  0,   vr"))
>   (match_dup 4)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
>     vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
>         (match_operand:VF 3 "register_operand"     "   vr,   vr")))
>     (match_operand:VF 4 "vector_arith_operand"   "   vr,   vr"))
>   (match_operand:VF 5 "register_operand"         "    0,   vr")))]
> -  "TARGET_VECTOR
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
>     && !rtx_equal_p (operands[2], operands[5])
>     && !rtx_equal_p (operands[3], operands[5])
>     && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
>         (match_operand:VF 3 "register_operand"      "  0,   vr,  0,   vr")))
>     (match_operand:VF 4 "register_operand"          " vr,   vr, vr,   vr"))
>   (match_dup 3)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
>     vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
>         (match_operand:VF 3 "register_operand"      " vr,   vr, vr,   vr")))
>     (match_operand:VF 4 "register_operand"          "  0,   vr,  0,   vr"))
>   (match_dup 4)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "@
>     vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
>     vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
>         (match_operand:VF 3 "register_operand"      "   vr,  vr")))
>     (match_operand:VF 4 "vector_arith_operand"      "   vr,  vr"))
>   (match_operand:VF 5 "register_operand"            "    0,  vr")))]
> -  "TARGET_VECTOR
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
>     && !rtx_equal_p (operands[3], operands[5])
>     && !rtx_equal_p (operands[4], operands[5])"
>    "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
>   (any_float_unop:VF
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.v\t%0,%3%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
>   (any_float_unop_nofrm:VF
>     (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<insn>.v\t%0,%3%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
>   (unspec:VF
>     [(match_operand:VF 3 "register_operand"       " vr, vr, vr, vr")] VFMISC)
>   (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vf<misc_op>.v\t%0,%3%p1"
>    [(set_attr "type" "<float_insn_type>")
>     (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
>   (unspec:<VCONVERT>
>     [(match_operand:VF 3 "register_operand"          " vr, vr, vr, vr")] UNSPEC_VFCLASS)
>   (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfclass.v\t%0,%3%p1"
>    [(set_attr "type" "vfclass")
>     (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
>     (float_extend:VWEXTF
>       (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
>   (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<insn>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "vf<widen_binop_insn_type>")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
>       (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand"       "    f,    f"))))
>   (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<insn>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "vf<widen_binop_insn_type>")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
>     (float_extend:VWEXTF
>       (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
>   (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<insn>.wv\t%0,%3,%4%p1"
>    [(set_attr "type" "vf<widen_binop_insn_type>")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
>       (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand"       "    f,    f"))))
>   (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<insn>.wf\t%0,%3,%4%p1"
>    [(set_attr "type" "vf<widen_binop_insn_type>")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
>         (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
>     (match_operand:VWEXTF 2 "register_operand"               "    0"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<macc_msac>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwmuladd")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
>         (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
>     (match_operand:VWEXTF 2 "register_operand"               "    0"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<macc_msac>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwmuladd")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
>           (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr"))))
>       (match_operand:VWEXTF 2 "register_operand"               "    0"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwmuladd")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
>           (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr"))))
>     (match_operand:VWEXTF 2 "register_operand"                 "    0"))
>   (match_dup 2)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwmuladd")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
>      [(match_operand:VF 4 "register_operand"          "   vr,   vr")
>       (match_operand:VF 5 "register_operand"          "   vr,   vr")])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
> -  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vv\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
>      [(match_operand:VF 3 "register_operand"           " vr")
>       (match_operand:VF 4 "register_operand"           " vr")])
>   (match_dup 1)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B2.vv\t%0,%3,%4,v0.t"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
>      [(match_operand:VF 4 "register_operand"          "   vr,    0,   vr,    0,    0,   vr,    0,   vr,   vr")
>       (match_operand:VF 5 "register_operand"          "   vr,   vr,    0,    0,   vr,    0,    0,   vr,   vr")])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,   vu,   vu,    0,    0,    0,   vu,    0")))]
> -  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vv\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
>       (vec_duplicate:VF
>         (match_operand:<VEL> 4 "register_operand"     "  f"))])
>   (match_dup 1)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B2.vf\t%0,%3,%4,v0.t"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
>       (vec_duplicate:VF
>         (match_operand:<VEL> 5 "register_operand"     "    f,    f"))])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
> -  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vf\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
>       (vec_duplicate:VF
>         (match_operand:<VEL> 5 "register_operand"     "    f,    f,    f,    f,    f"))])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
> -  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vf\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
>         (match_operand:<VEL> 4 "register_operand"     "  f"))
>       (match_operand:VF 3 "register_operand"          " vr")])
>   (match_dup 1)))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B2.vf\t%0,%3,%4,v0.t"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
>         (match_operand:<VEL> 5 "register_operand"     "    f,    f"))
>       (match_operand:VF 4 "register_operand"          "   vr,   vr")])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
> -  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vf\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
>         (match_operand:<VEL> 5 "register_operand"     "    f,    f,    f,    f,    f"))
>       (match_operand:VF 4 "register_operand"          "   vr,    0,    0,   vr,   vr")])
>   (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
> -  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> +  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vmf%B3.vf\t%0,%4,%5%p1"
>    [(set_attr "type" "vfcmp")
>     (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
>          (match_operand:VF 2 "register_operand"      " vr,vr")
> (match_operand:<VM> 4 "register_operand"    " vm,vm"))
>        (match_operand:VF 1 "vector_merge_operand"    " vu, 0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfmerge.vfm\t%0,%2,%3,%4"
>    [(set_attr "type" "vfmerge")
>     (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
>   (unspec:<VCONVERT>
>      [(match_operand:VF 3 "register_operand"         " vr, vr, vr, vr")] VFCVTS)
>   (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfcvt.x<v_su>.f.v\t%0,%3%p1"
>    [(set_attr "type" "vfcvtftoi")
>     (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
>   (any_fix:<VCONVERT>
>      (match_operand:VF 3 "register_operand"          " vr, vr, vr, vr"))
>   (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
>    [(set_attr "type" "vfcvtftoi")
>     (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
>   (any_float:VF
>      (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
>   (match_operand:VF 2 "vector_merge_operand"        " vu,  0, vu,  0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfcvt.f.x<u>.v\t%0,%3%p1"
>    [(set_attr "type" "vfcvtitof")
>     (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
>   (unspec:VWCONVERTI
>      [(match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr")] VFCVTS)
>   (match_operand:VWCONVERTI 2 "vector_merge_operand"  "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
>    "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
>    [(set_attr "type" "vfwcvtftoi")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
>   (any_fix:VWCONVERTI
>      (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
>   (match_operand:VWCONVERTI 2 "vector_merge_operand" "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
>    "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
>    [(set_attr "type" "vfwcvtftoi")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
>   (any_float:VF
>      (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
>   (match_operand:VF 2 "vector_merge_operand"         "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfwcvt.f.x<u>.v\t%0,%3%p1"
>    [(set_attr "type" "vfwcvtitof")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
>   (float_extend:VWEXTF
>      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
>   (match_operand:VWEXTF 2 "vector_merge_operand"          "   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfwcvt.f.f.v\t%0,%3%p1"
>    [(set_attr "type" "vfwcvtftof")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
>   (unspec:<VNCONVERT>
>      [(match_operand:VF 3 "register_operand"           "  0,  0,  0,  0,   vr,   vr")] VFCVTS)
>   (match_operand:<VNCONVERT> 2 "vector_merge_operand"  " vu,  0, vu,  0,   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfncvt.x<v_su>.f.w\t%0,%3%p1"
>    [(set_attr "type" "vfncvtftoi")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
>   (any_fix:<VNCONVERT>
>      (match_operand:VF 3 "register_operand"           "  0,  0,  0,  0,   vr,   vr"))
>   (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
>    "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
>    [(set_attr "type" "vfncvtftoi")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
>   (any_float:<VNCONVERT>
>      (match_operand:VWCONVERTI 3 "register_operand"   "  0,  0,  0,  0,   vr,   vr"))
>   (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
>    "vfncvt.f.x<u>.w\t%0,%3%p1"
>    [(set_attr "type" "vfncvtitof")
>     (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
>   (float_truncate:<V_DOUBLE_TRUNC>
>      (match_operand:VWEXTF 3 "register_operand"            "  0,  0,  0,  0,   vr,   vr"))
>   (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfncvt.f.f.w\t%0,%3%p1"
>    [(set_attr "type" "vfncvtftof")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
>     [(float_truncate:<V_DOUBLE_TRUNC>
>        (match_operand:VWEXTF 3 "register_operand"          "  0,  0,  0,  0,   vr,   vr"))] UNSPEC_ROD)
>   (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
>    "vfncvt.rod.f.f.w\t%0,%3%p1"
>    [(set_attr "type" "vfncvtftof")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
>          (parallel [(const_int 0)])))
>      (match_operand:VF 3 "register_operand"           "   vr,   vr"))
>    (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<reduc>.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfredu")
>     (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
>          (parallel [(const_int 0)])))
>      (match_operand:VF_ZVE64 3 "register_operand"           "   vr,   vr"))
>    (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<reduc>.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfredu")
>     (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
>          (parallel [(const_int 0)])))
>      (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
>    (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<reduc>.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfredu")
>     (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
>            (parallel [(const_int 0)])))
>        (match_operand:VF 3 "register_operand"           "   vr,   vr"))
>      (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<order>sum.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfred<order>")
>     (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
>            (parallel [(const_int 0)])))
>        (match_operand:VF_ZVE64 3 "register_operand"           "   vr,   vr"))
>      (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<order>sum.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfred<order>")
>     (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
>            (parallel [(const_int 0)])))
>        (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
>      (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC)] ORDER))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfred<order>sum.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfred<order>")
>     (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
>      (match_operand:VWF 3 "register_operand"             "   vr,   vr")
>      (match_operand:<VWLMUL1> 4 "register_operand"       "   vr,   vr")
>      (match_operand:<VWLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_WREDUC_SUM)] ORDER))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfwred<order>sum.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwred<order>")
>     (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
>      (match_operand:VWF_ZVE64 3 "register_operand"             "   vr,   vr")
>      (match_operand:<VWLMUL1_ZVE64> 4 "register_operand"       "   vr,   vr")
>      (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_WREDUC_SUM)] ORDER))]
> -  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> +  "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> +    && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfwred<order>sum.vs\t%0,%3,%4%p1"
>    [(set_attr "type" "vfwred<order>")
>     (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
>      (match_operand:VF 1 "register_operand" "vr")
>      (parallel [(const_int 0)]))
>    (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfmv.f.s\t%0,%1"
>    [(set_attr "type" "vfmovvf")
>     (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
>    (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")
>    (match_operand:VF 3 "register_operand"         " vr, vr, vr, vr")
>    (match_operand:<VEL> 4 "register_operand"      "  f,  f,  f,  f")] VFSLIDES1))]
> -  "TARGET_VECTOR"
> +  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
>    "vfslide<ud>.vf\t%0,%3,%4%p1"
>    [(set_attr "type" "vfslide<ud>")
>     (set_attr "mode" "<MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
>    return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
>    return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> +  return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> +  return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>