From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5982 invoked by alias); 9 Jun 2017 13:59:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 5966 invoked by uid 89); 9 Jun 2017 13:59:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Whats, What's, Hx-languages-length:4189 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 13:59:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EFCEF80D; Fri, 9 Jun 2017 06:59:39 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E6BF43F557; Fri, 9 Jun 2017 06:59:38 -0700 (PDT) Subject: Re: [PATCH 1/2] [ARM] Refactor costs calculation for MEM. To: charles.baylis@linaro.org, Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com Cc: rearnsha@arm.com, gcc-patches@gcc.gnu.org References: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> <1487696064-3233-2-git-send-email-charles.baylis@linaro.org> From: "Richard Earnshaw (lists)" Message-ID: <16a7e0b2-a1d4-424a-5dde-85d32bedcb0a@arm.com> Date: Fri, 09 Jun 2017 13:59:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <1487696064-3233-2-git-send-email-charles.baylis@linaro.org> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SW-Source: 2017-06/txt/msg00652.txt.bz2 On 21/02/17 16:54, charles.baylis@linaro.org wrote: > From: Charles Baylis > > This patch moves the calculation of costs for MEM into a > separate function, and reforms the calculation into two > parts. Firstly any additional cost of the addressing mode > is calculated, and then the cost of the memory access itself > is added. > > In this patch, the calculation of the cost of the addressing > mode is left as a placeholder, to be added in a subsequent > patch. > > gcc/ChangeLog: > > Charles Baylis > > * config/arm/arm.c (arm_mem_costs): New function. > (arm_rtx_costs_internal): Use arm_mem_costs. I like the idea of this patch, but it needs further work... Comments inline. R. > > Change-Id: I99e93406ea39ee31f71c7bf428ad3e127b7a618e > --- > gcc/config/arm/arm.c | 66 +++++++++++++++++++++++++++++++++------------------- > 1 file changed, 42 insertions(+), 24 deletions(-) > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 6cae178..7f002f1 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -9072,6 +9072,47 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) > } \ > while (0); > > +/* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM, > + considering the costs of the addressing mode and memory access > + separately. */ > +static bool > +arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, > + int *cost, bool speed_p) > +{ > + machine_mode mode = GET_MODE (x); > + if (flag_pic > + && GET_CODE (XEXP (x, 0)) == PLUS > + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) > + /* This will be split into two instructions. Add the cost of the > + additional instruction here. The cost of the memory access is computed > + below. See arm.md:calculate_pic_address. */ > + *cost = COSTS_N_INSNS (1); > + else > + *cost = 0; > + > + /* Calculate cost of the addressing mode. */ > + if (speed_p) > + { This patch needs to be reformatted in the GNU style (indentation of braces, braces and else clauses on separate lines etc). > + /* TODO: Add table-driven costs for addressing modes. */ You need to sort out the comment. What's missing here? > + } > + > + /* cost of memory access */ > + if (speed_p) > + { > + /* data transfer is transfer size divided by bus width. */ > + int bus_width = arm_arch7 ? 8 : 4; Basing bus width on the architecture is a bit too simplistic. Instead this should be a parameter that comes from the CPU cost tables, based on the current tune target. > + *cost += COSTS_N_INSNS((GET_MODE_SIZE (mode) + bus_width - 1) / bus_width); Use CEIL (from system.h) > + *cost += extra_cost->ldst.load; > + } else { > + *cost += COSTS_N_INSNS (1); > + } > + > + return true; > +} > +/* Convert fron bytes to ints. */ > +#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > + > + > /* RTX costs. Make an estimate of the cost of executing the operation > X, which is contained with an operation with code OUTER_CODE. > SPEED_P indicates whether the cost desired is the performance cost, > @@ -9152,30 +9193,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, > return false; > > case MEM: > - /* A memory access costs 1 insn if the mode is small, or the address is > - a single register, otherwise it costs one insn per word. */ > - if (REG_P (XEXP (x, 0))) > - *cost = COSTS_N_INSNS (1); > - else if (flag_pic > - && GET_CODE (XEXP (x, 0)) == PLUS > - && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) > - /* This will be split into two instructions. > - See arm.md:calculate_pic_address. */ > - *cost = COSTS_N_INSNS (2); > - else > - *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode)); > - > - /* For speed optimizations, add the costs of the address and > - accessing memory. */ > - if (speed_p) > -#ifdef NOT_YET > - *cost += (extra_cost->ldst.load > - + arm_address_cost (XEXP (x, 0), mode, > - ADDR_SPACE_GENERIC, speed_p)); > -#else > - *cost += extra_cost->ldst.load; > -#endif > - return true; > + return arm_mem_costs (x, extra_cost, cost, speed_p); > > case PARALLEL: > { >