From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12995 invoked by alias); 11 Jul 2017 21:24:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 12661 invoked by uid 89); 11 Jul 2017 21:24:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 11 Jul 2017 21:24:10 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 9BC0C81368; Tue, 11 Jul 2017 23:24:02 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6TAlnWgstOwe; Tue, 11 Jul 2017 23:24:02 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 7C81A81332; Tue, 11 Jul 2017 23:24:02 +0200 (CEST) From: Eric Botcazou To: Qing Zhao Cc: gcc-patches@gcc.gnu.org Subject: Re: A potential bug in lra-constraints.c for special_memory_constraint? Date: Tue, 11 Jul 2017 21:24:00 -0000 Message-ID: <1716229.J62mpvjAe0@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-53-desktop; KDE/4.14.9; x86_64; ; ) In-Reply-To: <4F37C8D3-6C63-4F58-AEE1-4F156CBFAE84@oracle.com> References: <69954BF8-C027-469C-9242-4246028C84E8@oracle.com> <1796181.5sq0F8iaXQ@polaris> <4F37C8D3-6C63-4F58-AEE1-4F156CBFAE84@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-SW-Source: 2017-07/txt/msg00565.txt.bz2 > we need to generate misaligned load/store insns ONLY for misaligned memory > access, therefore need a new constraints for misaligned address. Why? What happens exactly if the memory access turns out to be aligned? -- Eric Botcazou