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From: "Peryt, Sebastian" <sebastian.peryt@intel.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "sandra@codesourcery.com" <sandra@codesourcery.com>,
	"ubizjak@gmail.com"	<ubizjak@gmail.com>,
	"Koval, Julia" <julia.koval@intel.com>
Subject: [PATCH] Match x86 family machine constraints section with constarints.md
Date: Wed, 26 Apr 2017 15:37:00 -0000	[thread overview]
Message-ID: <17623B198193D741876BD81A6E3AE5AD3BBAF0D4@irsmsx105.ger.corp.intel.com> (raw)

[-- Attachment #1: Type: text/plain, Size: 346 bytes --]

Hi,

This patch updates x86 family machine constraints section in '16.8.5 Constraints for Particular Machines' section to match the ones in 'config/i386/constraints.md'.

gcc/
	* doc/md.texi (Machine Constraints): Update x86 family machine constraints
	   section to match 'config/i386/constraints.md'.

Is it ok for trunk?

Sebastian

[-- Attachment #2: x86_constraints_doc.patch --]
[-- Type: application/octet-stream, Size: 3350 bytes --]

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index dde3644..7315967 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -4003,6 +4003,8 @@ unsigned long long rdtsc (void)
 @}
 @end smallexample
 
+@item U
+The call-clobbered integer registers.
 
 @item f
 Any 80387 floating-point (stack) register.
@@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}).
 @item u
 Second from top of 80387 floating-point stack (@code{%st(1)}).
 
+@ifset INTERNALS
+@item Yk
+Any mask register that can be used as predicate, i.e. k1-k7.
+
+@item k
+Any mask register.
+@end ifset
+
 @item y
 Any MMX register.
 
 @item x
 Any SSE register.
 
+@item v
+Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
+
+@ifset INTERNALS
+@item w
+Any bound register.
+@end ifset
+
 @item Yz
 First SSE register (@code{%xmm0}).
 
 @ifset INTERNALS
-@item Y2
-Any SSE register, when SSE2 is enabled.
-
 @item Yi
 Any SSE register, when SSE2 and inter-unit moves are enabled.
 
+@item Yj
+Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
+
 @item Ym
 Any MMX register, when inter-unit moves are enabled.
+
+@item Yn
+Any MMX register, when inter-unit moves from vector registers are enabled.
+
+@item Yp
+Any integer register when TARGET_PARTIAL_REG_STALL is disabled.
+
+@item Ya
+Any integer register when zero extensions with AND are disabled.
+
+@item Yb
+Any register that can be used as the GOT base when calling ___tls_get_addr:
+that is, any general register except @code{a} and @code{sp} registers,
+for -fno-plt if linker supports it. Otherwise, @code{b} register.
+
+@item Yf
+Any x87 register when 80387 FP arithmetic is enabled.
+
+@item Yr
+Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
+
+@item Yv
+For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}),
+otherwise any SSE register.
+
+@item Yh
+Any EVEX encodable SSE register, which has number factor of four.
+
+@item Bf
+Flags register operand.
+
+@item Bg
+GOT memory operand.
+
+@item Bm
+Vector memory operand.
+
+@item Bc
+Constant memory operand.
+
+@item Bn
+Memory operand without REX prefix.
+
+@item Bs
+Sibcall memory operand.
+
+@item Bw
+Call memory operand.
+
+@item Bz
+Constant call address operand.
+
+@item BC
+SSE constant -1 operand.
 @end ifset
 
 @item I
@@ -4068,11 +4140,37 @@ SSE constant zero operand.
 to fit that range (for immediate operands in sign-extending x86-64
 instructions).
 
+@item We
+32-bit signed integer constant, or a symbolic reference known
+to fit that range (for sign-extending conversion operations that
+require non-VOIDmode immediate operands).
+
+@item Wz
+32-bit unsigned integer constant, or a symbolic reference known
+to fit that range (for zero-extending conversion operations that
+require non-VOIDmode immediate operands).
+
+@item Wd
+128-bit integer constant where both the high and low 64-bit word
+of it satisfies the e constraint.
+
 @item Z
 32-bit unsigned integer constant, or a symbolic reference known
 to fit that range (for immediate operands in zero-extending x86-64
 instructions).
 
+@item Tv
+VSIB address operand.
+
+@item Ts
+Address operand without segment register.
+
+@item Ti
+MPX address operand without index.
+
+@item Tb
+MPX address operand without base.
+
 @end table
 
 @item Xstormy16---@file{config/stormy16/stormy16.h}

             reply	other threads:[~2017-04-26 14:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-26 15:37 Peryt, Sebastian [this message]
2017-04-27 21:03 ` Sandra Loosemore
2017-04-28  9:31   ` Peryt, Sebastian
2017-05-23  9:18     ` Peryt, Sebastian
2017-05-23 15:49     ` Sandra Loosemore
2017-05-24 13:40       ` Uros Bizjak
2017-05-25  6:50         ` Peryt, Sebastian
2017-05-25 19:56           ` Uros Bizjak

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