* [PATCH] Match x86 family machine constraints section with constarints.md @ 2017-04-26 15:37 Peryt, Sebastian 2017-04-27 21:03 ` Sandra Loosemore 0 siblings, 1 reply; 8+ messages in thread From: Peryt, Sebastian @ 2017-04-26 15:37 UTC (permalink / raw) To: gcc-patches; +Cc: sandra, ubizjak, Koval, Julia [-- Attachment #1: Type: text/plain, Size: 346 bytes --] Hi, This patch updates x86 family machine constraints section in '16.8.5 Constraints for Particular Machines' section to match the ones in 'config/i386/constraints.md'. gcc/ * doc/md.texi (Machine Constraints): Update x86 family machine constraints section to match 'config/i386/constraints.md'. Is it ok for trunk? Sebastian [-- Attachment #2: x86_constraints_doc.patch --] [-- Type: application/octet-stream, Size: 3350 bytes --] diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index dde3644..7315967 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4003,6 +4003,8 @@ unsigned long long rdtsc (void) @} @end smallexample +@item U +The call-clobbered integer registers. @item f Any 80387 floating-point (stack) register. @@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}). @item u Second from top of 80387 floating-point stack (@code{%st(1)}). +@ifset INTERNALS +@item Yk +Any mask register that can be used as predicate, i.e. k1-k7. + +@item k +Any mask register. +@end ifset + @item y Any MMX register. @item x Any SSE register. +@item v +Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). + +@ifset INTERNALS +@item w +Any bound register. +@end ifset + @item Yz First SSE register (@code{%xmm0}). @ifset INTERNALS -@item Y2 -Any SSE register, when SSE2 is enabled. - @item Yi Any SSE register, when SSE2 and inter-unit moves are enabled. +@item Yj +Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. + @item Ym Any MMX register, when inter-unit moves are enabled. + +@item Yn +Any MMX register, when inter-unit moves from vector registers are enabled. + +@item Yp +Any integer register when TARGET_PARTIAL_REG_STALL is disabled. + +@item Ya +Any integer register when zero extensions with AND are disabled. + +@item Yb +Any register that can be used as the GOT base when calling ___tls_get_addr: +that is, any general register except @code{a} and @code{sp} registers, +for -fno-plt if linker supports it. Otherwise, @code{b} register. + +@item Yf +Any x87 register when 80387 FP arithmetic is enabled. + +@item Yr +Lower SSE register when avoiding REX prefix and all SSE registers otherwise. + +@item Yv +For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), +otherwise any SSE register. + +@item Yh +Any EVEX encodable SSE register, which has number factor of four. + +@item Bf +Flags register operand. + +@item Bg +GOT memory operand. + +@item Bm +Vector memory operand. + +@item Bc +Constant memory operand. + +@item Bn +Memory operand without REX prefix. + +@item Bs +Sibcall memory operand. + +@item Bw +Call memory operand. + +@item Bz +Constant call address operand. + +@item BC +SSE constant -1 operand. @end ifset @item I @@ -4068,11 +4140,37 @@ SSE constant zero operand. to fit that range (for immediate operands in sign-extending x86-64 instructions). +@item We +32-bit signed integer constant, or a symbolic reference known +to fit that range (for sign-extending conversion operations that +require non-VOIDmode immediate operands). + +@item Wz +32-bit unsigned integer constant, or a symbolic reference known +to fit that range (for zero-extending conversion operations that +require non-VOIDmode immediate operands). + +@item Wd +128-bit integer constant where both the high and low 64-bit word +of it satisfies the e constraint. + @item Z 32-bit unsigned integer constant, or a symbolic reference known to fit that range (for immediate operands in zero-extending x86-64 instructions). +@item Tv +VSIB address operand. + +@item Ts +Address operand without segment register. + +@item Ti +MPX address operand without index. + +@item Tb +MPX address operand without base. + @end table @item Xstormy16---@file{config/stormy16/stormy16.h} ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Match x86 family machine constraints section with constarints.md 2017-04-26 15:37 [PATCH] Match x86 family machine constraints section with constarints.md Peryt, Sebastian @ 2017-04-27 21:03 ` Sandra Loosemore 2017-04-28 9:31 ` Peryt, Sebastian 0 siblings, 1 reply; 8+ messages in thread From: Sandra Loosemore @ 2017-04-27 21:03 UTC (permalink / raw) To: Peryt, Sebastian, gcc-patches; +Cc: ubizjak, Koval, Julia On 04/26/2017 08:29 AM, Peryt, Sebastian wrote: > Hi, > > This patch updates x86 family machine constraints section in '16.8.5 Constraints for Particular Machines' section to match the ones in 'config/i386/constraints.md'. > > gcc/ > * doc/md.texi (Machine Constraints): Update x86 family machine constraints > section to match 'config/i386/constraints.md'. > > Is it ok for trunk? I have a few comments on grammar and markup, but I can't comment intelligently on whether the technical content is correct. > @@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}). > @item u > Second from top of 80387 floating-point stack (@code{%st(1)}). > > +@ifset INTERNALS > +@item Yk > +Any mask register that can be used as predicate, i.e. k1-k7. s/predicate/a predicate/ Other places in this section use @code markup on literal register names. > + > +@item k > +Any mask register. > +@end ifset > + > @item y > Any MMX register. > > @item x > Any SSE register. > > +@item v > +Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). > + > +@ifset INTERNALS > +@item w > +Any bound register. > +@end ifset > + > @item Yz > First SSE register (@code{%xmm0}). > > @ifset INTERNALS > -@item Y2 > -Any SSE register, when SSE2 is enabled. > - > @item Yi > Any SSE register, when SSE2 and inter-unit moves are enabled. > > +@item Yj > +Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. > + > @item Ym > Any MMX register, when inter-unit moves are enabled. > + > +@item Yn > +Any MMX register, when inter-unit moves from vector registers are enabled. > + > +@item Yp > +Any integer register when TARGET_PARTIAL_REG_STALL is disabled. @code markup on that. > + > +@item Ya > +Any integer register when zero extensions with AND are disabled. I'm not sure what "AND" is, but it probably needs @code markup too. > + > +@item Yb > +Any register that can be used as the GOT base when calling ___tls_get_addr: @code{___tls_get_addr} > +that is, any general register except @code{a} and @code{sp} registers, > +for -fno-plt if linker supports it. Otherwise, @code{b} register. @option{-fno-plt} > + > +@item Yf > +Any x87 register when 80387 FP arithmetic is enabled. Is "FP" a literal feature name used in the processor documentation, or do you just mean "floating-point arithmetic" here? > + > +@item Yr > +Lower SSE register when avoiding REX prefix and all SSE registers otherwise. I don't know what "avoiding REX prefix" means, and don't see the string "REX" in any other GCC documentation. > + > +@item Yv > +For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), > +otherwise any SSE register. This should probably be "EVEX-encodable", whatever that means. > + > +@item Yh > +Any EVEX encodable SSE register, which has number factor of four. Same here, but what is "number factor of four"? Also, if this is supposed to designate a subset of the EVEX-encodable SSE registers rather than describe all of them, you need "that" instead of "which". > + > +@item Bf > +Flags register operand. > + > +@item Bg > +GOT memory operand. > + > +@item Bm > +Vector memory operand. > + > +@item Bc > +Constant memory operand. > + > +@item Bn > +Memory operand without REX prefix. > + > +@item Bs > +Sibcall memory operand. > + > +@item Bw > +Call memory operand. > + > +@item Bz > +Constant call address operand. > + > +@item BC > +SSE constant -1 operand. > @end ifset > > @item I > @@ -4068,11 +4140,37 @@ SSE constant zero operand. > to fit that range (for immediate operands in sign-extending x86-64 > instructions). > > +@item We > +32-bit signed integer constant, or a symbolic reference known > +to fit that range (for sign-extending conversion operations that > +require non-VOIDmode immediate operands). @code{VOIDmode}. > + > +@item Wz > +32-bit unsigned integer constant, or a symbolic reference known > +to fit that range (for zero-extending conversion operations that > +require non-VOIDmode immediate operands). Ditto. > + > +@item Wd > +128-bit integer constant where both the high and low 64-bit word > +of it satisfies the e constraint. ...where both the high and low 64-bit words satisfy the @code{e} constraint. > + > @item Z > 32-bit unsigned integer constant, or a symbolic reference known > to fit that range (for immediate operands in zero-extending x86-64 > instructions). > > +@item Tv > +VSIB address operand. > + > +@item Ts > +Address operand without segment register. > + > +@item Ti > +MPX address operand without index. > + > +@item Tb > +MPX address operand without base. > + > @end table > > @item Xstormy16---@file{config/stormy16/stormy16.h} -Sandra ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] Match x86 family machine constraints section with constarints.md 2017-04-27 21:03 ` Sandra Loosemore @ 2017-04-28 9:31 ` Peryt, Sebastian 2017-05-23 9:18 ` Peryt, Sebastian 2017-05-23 15:49 ` Sandra Loosemore 0 siblings, 2 replies; 8+ messages in thread From: Peryt, Sebastian @ 2017-04-28 9:31 UTC (permalink / raw) To: Sandra Loosemore, gcc-patches; +Cc: ubizjak, Koval, Julia, kirill.yukhin [-- Attachment #1: Type: text/plain, Size: 6110 bytes --] Hi, Thank you for your comments. I edited my patch accordingly. As for some of your doubts: - REX is the opcode prefix to access 64-bit register extensions introduced in IA-32e mode. - EVEX is the encoding prefix which applies to SIMD operating instructions operating on XMM, YMM and ZMM registers. It was introduced with AVX-512 instructions. - "number factor of four" that means that sources start in a multiple of 4 boundary. This is used for some of instructions. Also I'd like to add that this whole patch is strictly based on docstring parts of constraints that are present in config/i386/constraints.md but not in documentation (md.texi file). There is no new (new as in nonexistent in code) content. I'm also adding Kirill Yukhin to CC, because I believe he is the correct person that can catch any technical errors if any has slipped-in. Thanks, Sebastian -----Original Message----- From: Sandra Loosemore [mailto:sandra@codesourcery.com] Sent: Thursday, April 27, 2017 10:17 PM To: Peryt, Sebastian <sebastian.peryt@intel.com>; gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com; Koval, Julia <julia.koval@intel.com> Subject: Re: [PATCH] Match x86 family machine constraints section with constarints.md On 04/26/2017 08:29 AM, Peryt, Sebastian wrote: > Hi, > > This patch updates x86 family machine constraints section in '16.8.5 Constraints for Particular Machines' section to match the ones in 'config/i386/constraints.md'. > > gcc/ > * doc/md.texi (Machine Constraints): Update x86 family machine constraints > section to match 'config/i386/constraints.md'. > > Is it ok for trunk? I have a few comments on grammar and markup, but I can't comment intelligently on whether the technical content is correct. > @@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}). > @item u > Second from top of 80387 floating-point stack (@code{%st(1)}). > > +@ifset INTERNALS > +@item Yk > +Any mask register that can be used as predicate, i.e. k1-k7. s/predicate/a predicate/ Other places in this section use @code markup on literal register names. > + > +@item k > +Any mask register. > +@end ifset > + > @item y > Any MMX register. > > @item x > Any SSE register. > > +@item v > +Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). > + > +@ifset INTERNALS > +@item w > +Any bound register. > +@end ifset > + > @item Yz > First SSE register (@code{%xmm0}). > > @ifset INTERNALS > -@item Y2 > -Any SSE register, when SSE2 is enabled. > - > @item Yi > Any SSE register, when SSE2 and inter-unit moves are enabled. > > +@item Yj > +Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. > + > @item Ym > Any MMX register, when inter-unit moves are enabled. > + > +@item Yn > +Any MMX register, when inter-unit moves from vector registers are enabled. > + > +@item Yp > +Any integer register when TARGET_PARTIAL_REG_STALL is disabled. @code markup on that. > + > +@item Ya > +Any integer register when zero extensions with AND are disabled. I'm not sure what "AND" is, but it probably needs @code markup too. > + > +@item Yb > +Any register that can be used as the GOT base when calling ___tls_get_addr: @code{___tls_get_addr} > +that is, any general register except @code{a} and @code{sp} > +registers, for -fno-plt if linker supports it. Otherwise, @code{b} register. @option{-fno-plt} > + > +@item Yf > +Any x87 register when 80387 FP arithmetic is enabled. Is "FP" a literal feature name used in the processor documentation, or do you just mean "floating-point arithmetic" here? > + > +@item Yr > +Lower SSE register when avoiding REX prefix and all SSE registers otherwise. I don't know what "avoiding REX prefix" means, and don't see the string "REX" in any other GCC documentation. > + > +@item Yv > +For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), > +otherwise any SSE register. This should probably be "EVEX-encodable", whatever that means. > + > +@item Yh > +Any EVEX encodable SSE register, which has number factor of four. Same here, but what is "number factor of four"? Also, if this is supposed to designate a subset of the EVEX-encodable SSE registers rather than describe all of them, you need "that" instead of "which". > + > +@item Bf > +Flags register operand. > + > +@item Bg > +GOT memory operand. > + > +@item Bm > +Vector memory operand. > + > +@item Bc > +Constant memory operand. > + > +@item Bn > +Memory operand without REX prefix. > + > +@item Bs > +Sibcall memory operand. > + > +@item Bw > +Call memory operand. > + > +@item Bz > +Constant call address operand. > + > +@item BC > +SSE constant -1 operand. > @end ifset > > @item I > @@ -4068,11 +4140,37 @@ SSE constant zero operand. > to fit that range (for immediate operands in sign-extending x86-64 > instructions). > > +@item We > +32-bit signed integer constant, or a symbolic reference known to fit > +that range (for sign-extending conversion operations that require > +non-VOIDmode immediate operands). @code{VOIDmode}. > + > +@item Wz > +32-bit unsigned integer constant, or a symbolic reference known to > +fit that range (for zero-extending conversion operations that require > +non-VOIDmode immediate operands). Ditto. > + > +@item Wd > +128-bit integer constant where both the high and low 64-bit word of > +it satisfies the e constraint. ...where both the high and low 64-bit words satisfy the @code{e} constraint. > + > @item Z > 32-bit unsigned integer constant, or a symbolic reference known to > fit that range (for immediate operands in zero-extending x86-64 > instructions). > > +@item Tv > +VSIB address operand. > + > +@item Ts > +Address operand without segment register. > + > +@item Ti > +MPX address operand without index. > + > +@item Tb > +MPX address operand without base. > + > @end table > > @item Xstormy16---@file{config/stormy16/stormy16.h} -Sandra [-- Attachment #2: x86_constraints_doc_v2.patch --] [-- Type: application/octet-stream, Size: 3416 bytes --] diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index dde3644..e2fce67 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4003,6 +4003,8 @@ unsigned long long rdtsc (void) @} @end smallexample +@item U +The call-clobbered integer registers. @item f Any 80387 floating-point (stack) register. @@ -4013,24 +4015,95 @@ Top of 80387 floating-point stack (@code{%st(0)}). @item u Second from top of 80387 floating-point stack (@code{%st(1)}). +@ifset INTERNALS +@item Yk +Any mask register that can be used as a predicate, i.e. @code{k1-k7}. + +@item k +Any mask register. +@end ifset + @item y Any MMX register. @item x Any SSE register. +@item v +Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). + +@ifset INTERNALS +@item w +Any bound register. +@end ifset + @item Yz First SSE register (@code{%xmm0}). @ifset INTERNALS -@item Y2 -Any SSE register, when SSE2 is enabled. - @item Yi Any SSE register, when SSE2 and inter-unit moves are enabled. +@item Yj +Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. + @item Ym Any MMX register, when inter-unit moves are enabled. + +@item Yn +Any MMX register, when inter-unit moves from vector registers are enabled. + +@item Yp +Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled. + +@item Ya +Any integer register when zero extensions with @code{AND} are disabled. + +@item Yb +Any register that can be used as the GOT base when calling@* +@code{___tls_get_addr}: that is, any general register except @code{a} +and @code{sp} registers, for @option{-fno-plt} if linker supports it. +Otherwise, @code{b} register. + +@item Yf +Any x87 register when 80387 floating-point arithmetic is enabled. + +@item Yr +Lower SSE register when avoiding REX prefix and all SSE registers otherwise. + +@item Yv +For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}), +otherwise any SSE register. + +@item Yh +Any EVEX-encodable SSE register, that has number factor of four. + +@item Bf +Flags register operand. + +@item Bg +GOT memory operand. + +@item Bm +Vector memory operand. + +@item Bc +Constant memory operand. + +@item Bn +Memory operand without REX prefix. + +@item Bs +Sibcall memory operand. + +@item Bw +Call memory operand. + +@item Bz +Constant call address operand. + +@item BC +SSE constant -1 operand. @end ifset @item I @@ -4068,11 +4141,37 @@ SSE constant zero operand. to fit that range (for immediate operands in sign-extending x86-64 instructions). +@item We +32-bit signed integer constant, or a symbolic reference known +to fit that range (for sign-extending conversion operations that +require non-@code{VOIDmode} immediate operands). + +@item Wz +32-bit unsigned integer constant, or a symbolic reference known +to fit that range (for zero-extending conversion operations that +require non-@code{VOIDmode} immediate operands). + +@item Wd +128-bit integer constant where both the high and low 64-bit word +satisfy the @code{e} constraint. + @item Z 32-bit unsigned integer constant, or a symbolic reference known to fit that range (for immediate operands in zero-extending x86-64 instructions). +@item Tv +VSIB address operand. + +@item Ts +Address operand without segment register. + +@item Ti +MPX address operand without index. + +@item Tb +MPX address operand without base. + @end table @item Xstormy16---@file{config/stormy16/stormy16.h} ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] Match x86 family machine constraints section with constarints.md 2017-04-28 9:31 ` Peryt, Sebastian @ 2017-05-23 9:18 ` Peryt, Sebastian 2017-05-23 15:49 ` Sandra Loosemore 1 sibling, 0 replies; 8+ messages in thread From: Peryt, Sebastian @ 2017-05-23 9:18 UTC (permalink / raw) To: 'Sandra Loosemore', 'gcc-patches@gcc.gnu.org' Cc: 'ubizjak@gmail.com', Koval, Julia, 'kirill.yukhin@gmail.com' Gentle ping. Thanks, Sebastian -----Original Message----- From: Peryt, Sebastian Sent: Friday, April 28, 2017 11:31 AM To: Sandra Loosemore <sandra@codesourcery.com>; gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com; Koval, Julia <julia.koval@intel.com>; kirill.yukhin@gmail.com Subject: RE: [PATCH] Match x86 family machine constraints section with constarints.md Hi, Thank you for your comments. I edited my patch accordingly. As for some of your doubts: - REX is the opcode prefix to access 64-bit register extensions introduced in IA-32e mode. - EVEX is the encoding prefix which applies to SIMD operating instructions operating on XMM, YMM and ZMM registers. It was introduced with AVX-512 instructions. - "number factor of four" that means that sources start in a multiple of 4 boundary. This is used for some of instructions. Also I'd like to add that this whole patch is strictly based on docstring parts of constraints that are present in config/i386/constraints.md but not in documentation (md.texi file). There is no new (new as in nonexistent in code) content. I'm also adding Kirill Yukhin to CC, because I believe he is the correct person that can catch any technical errors if any has slipped-in. Thanks, Sebastian -----Original Message----- From: Sandra Loosemore [mailto:sandra@codesourcery.com] Sent: Thursday, April 27, 2017 10:17 PM To: Peryt, Sebastian <sebastian.peryt@intel.com>; gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com; Koval, Julia <julia.koval@intel.com> Subject: Re: [PATCH] Match x86 family machine constraints section with constarints.md On 04/26/2017 08:29 AM, Peryt, Sebastian wrote: > Hi, > > This patch updates x86 family machine constraints section in '16.8.5 Constraints for Particular Machines' section to match the ones in 'config/i386/constraints.md'. > > gcc/ > * doc/md.texi (Machine Constraints): Update x86 family machine constraints > section to match 'config/i386/constraints.md'. > > Is it ok for trunk? I have a few comments on grammar and markup, but I can't comment intelligently on whether the technical content is correct. > @@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}). > @item u > Second from top of 80387 floating-point stack (@code{%st(1)}). > > +@ifset INTERNALS > +@item Yk > +Any mask register that can be used as predicate, i.e. k1-k7. s/predicate/a predicate/ Other places in this section use @code markup on literal register names. > + > +@item k > +Any mask register. > +@end ifset > + > @item y > Any MMX register. > > @item x > Any SSE register. > > +@item v > +Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). > + > +@ifset INTERNALS > +@item w > +Any bound register. > +@end ifset > + > @item Yz > First SSE register (@code{%xmm0}). > > @ifset INTERNALS > -@item Y2 > -Any SSE register, when SSE2 is enabled. > - > @item Yi > Any SSE register, when SSE2 and inter-unit moves are enabled. > > +@item Yj > +Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. > + > @item Ym > Any MMX register, when inter-unit moves are enabled. > + > +@item Yn > +Any MMX register, when inter-unit moves from vector registers are enabled. > + > +@item Yp > +Any integer register when TARGET_PARTIAL_REG_STALL is disabled. @code markup on that. > + > +@item Ya > +Any integer register when zero extensions with AND are disabled. I'm not sure what "AND" is, but it probably needs @code markup too. > + > +@item Yb > +Any register that can be used as the GOT base when calling ___tls_get_addr: @code{___tls_get_addr} > +that is, any general register except @code{a} and @code{sp} > +registers, for -fno-plt if linker supports it. Otherwise, @code{b} register. @option{-fno-plt} > + > +@item Yf > +Any x87 register when 80387 FP arithmetic is enabled. Is "FP" a literal feature name used in the processor documentation, or do you just mean "floating-point arithmetic" here? > + > +@item Yr > +Lower SSE register when avoiding REX prefix and all SSE registers otherwise. I don't know what "avoiding REX prefix" means, and don't see the string "REX" in any other GCC documentation. > + > +@item Yv > +For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), > +otherwise any SSE register. This should probably be "EVEX-encodable", whatever that means. > + > +@item Yh > +Any EVEX encodable SSE register, which has number factor of four. Same here, but what is "number factor of four"? Also, if this is supposed to designate a subset of the EVEX-encodable SSE registers rather than describe all of them, you need "that" instead of "which". > + > +@item Bf > +Flags register operand. > + > +@item Bg > +GOT memory operand. > + > +@item Bm > +Vector memory operand. > + > +@item Bc > +Constant memory operand. > + > +@item Bn > +Memory operand without REX prefix. > + > +@item Bs > +Sibcall memory operand. > + > +@item Bw > +Call memory operand. > + > +@item Bz > +Constant call address operand. > + > +@item BC > +SSE constant -1 operand. > @end ifset > > @item I > @@ -4068,11 +4140,37 @@ SSE constant zero operand. > to fit that range (for immediate operands in sign-extending x86-64 > instructions). > > +@item We > +32-bit signed integer constant, or a symbolic reference known to fit > +that range (for sign-extending conversion operations that require > +non-VOIDmode immediate operands). @code{VOIDmode}. > + > +@item Wz > +32-bit unsigned integer constant, or a symbolic reference known to > +fit that range (for zero-extending conversion operations that require > +non-VOIDmode immediate operands). Ditto. > + > +@item Wd > +128-bit integer constant where both the high and low 64-bit word of > +it satisfies the e constraint. ...where both the high and low 64-bit words satisfy the @code{e} constraint. > + > @item Z > 32-bit unsigned integer constant, or a symbolic reference known to > fit that range (for immediate operands in zero-extending x86-64 > instructions). > > +@item Tv > +VSIB address operand. > + > +@item Ts > +Address operand without segment register. > + > +@item Ti > +MPX address operand without index. > + > +@item Tb > +MPX address operand without base. > + > @end table > > @item Xstormy16---@file{config/stormy16/stormy16.h} -Sandra ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Match x86 family machine constraints section with constarints.md 2017-04-28 9:31 ` Peryt, Sebastian 2017-05-23 9:18 ` Peryt, Sebastian @ 2017-05-23 15:49 ` Sandra Loosemore 2017-05-24 13:40 ` Uros Bizjak 1 sibling, 1 reply; 8+ messages in thread From: Sandra Loosemore @ 2017-05-23 15:49 UTC (permalink / raw) To: Peryt, Sebastian, gcc-patches; +Cc: ubizjak, Koval, Julia, kirill.yukhin On 04/28/2017 03:30 AM, Peryt, Sebastian wrote: > Hi, > > Thank you for your comments. I edited my patch accordingly. As for some of your doubts: > - REX is the opcode prefix to access 64-bit register extensions introduced in IA-32e mode. > - EVEX is the encoding prefix which applies to SIMD operating instructions operating on XMM, YMM and ZMM registers. It was introduced with AVX-512 instructions. > - "number factor of four" that means that sources start in a multiple of 4 boundary. This is used for some of instructions. > > Also I'd like to add that this whole patch is strictly based on docstring parts of constraints that are present in config/i386/constraints.md but not in documentation (md.texi file). There is no new (new as in nonexistent in code) content. > > I'm also adding Kirill Yukhin to CC, because I believe he is the correct person that can catch any technical errors if any has slipped-in. The grammar/markup/etc are OK now, but I can't comment on technical correctness of the information. -Sandra ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Match x86 family machine constraints section with constarints.md 2017-05-23 15:49 ` Sandra Loosemore @ 2017-05-24 13:40 ` Uros Bizjak 2017-05-25 6:50 ` Peryt, Sebastian 0 siblings, 1 reply; 8+ messages in thread From: Uros Bizjak @ 2017-05-24 13:40 UTC (permalink / raw) To: Sandra Loosemore Cc: Peryt, Sebastian, gcc-patches, Koval, Julia, kirill.yukhin On Tue, May 23, 2017 at 5:33 PM, Sandra Loosemore <sandra@codesourcery.com> wrote: > On 04/28/2017 03:30 AM, Peryt, Sebastian wrote: >> >> Hi, >> >> Thank you for your comments. I edited my patch accordingly. As for some of >> your doubts: >> - REX is the opcode prefix to access 64-bit register extensions >> introduced in IA-32e mode. >> - EVEX is the encoding prefix which applies to SIMD operating instructions >> operating on XMM, YMM and ZMM registers. It was introduced with AVX-512 >> instructions. >> - "number factor of four" that means that sources start in a multiple of 4 >> boundary. This is used for some of instructions. >> >> Also I'd like to add that this whole patch is strictly based on docstring >> parts of constraints that are present in config/i386/constraints.md but not >> in documentation (md.texi file). There is no new (new as in nonexistent in >> code) content. >> >> I'm also adding Kirill Yukhin to CC, because I believe he is the correct >> person that can catch any technical errors if any has slipped-in. > > > The grammar/markup/etc are OK now, but I can't comment on technical > correctness of the information. LGTM. Thanks, Uros. ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] Match x86 family machine constraints section with constarints.md 2017-05-24 13:40 ` Uros Bizjak @ 2017-05-25 6:50 ` Peryt, Sebastian 2017-05-25 19:56 ` Uros Bizjak 0 siblings, 1 reply; 8+ messages in thread From: Peryt, Sebastian @ 2017-05-25 6:50 UTC (permalink / raw) To: Uros Bizjak, Sandra Loosemore; +Cc: gcc-patches, Koval, Julia, kirill.yukhin Hi, Thank you very much for the answers. Can someone please commit this patch for me? Thanks, Sebastian -----Original Message----- From: Uros Bizjak [mailto:ubizjak@gmail.com] Sent: Wednesday, May 24, 2017 3:31 PM To: Sandra Loosemore <sandra@codesourcery.com> Cc: Peryt, Sebastian <sebastian.peryt@intel.com>; gcc-patches@gcc.gnu.org; Koval, Julia <julia.koval@intel.com>; kirill.yukhin@gmail.com Subject: Re: [PATCH] Match x86 family machine constraints section with constarints.md On Tue, May 23, 2017 at 5:33 PM, Sandra Loosemore <sandra@codesourcery.com> wrote: > On 04/28/2017 03:30 AM, Peryt, Sebastian wrote: >> >> Hi, >> >> Thank you for your comments. I edited my patch accordingly. As for >> some of your doubts: >> - REX is the opcode prefix to access 64-bit register extensions >> introduced in IA-32e mode. >> - EVEX is the encoding prefix which applies to SIMD operating >> instructions operating on XMM, YMM and ZMM registers. It was >> introduced with AVX-512 instructions. >> - "number factor of four" that means that sources start in a multiple >> of 4 boundary. This is used for some of instructions. >> >> Also I'd like to add that this whole patch is strictly based on >> docstring parts of constraints that are present in >> config/i386/constraints.md but not in documentation (md.texi file). >> There is no new (new as in nonexistent in >> code) content. >> >> I'm also adding Kirill Yukhin to CC, because I believe he is the >> correct person that can catch any technical errors if any has slipped-in. > > > The grammar/markup/etc are OK now, but I can't comment on technical > correctness of the information. LGTM. Thanks, Uros. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Match x86 family machine constraints section with constarints.md 2017-05-25 6:50 ` Peryt, Sebastian @ 2017-05-25 19:56 ` Uros Bizjak 0 siblings, 0 replies; 8+ messages in thread From: Uros Bizjak @ 2017-05-25 19:56 UTC (permalink / raw) To: Peryt, Sebastian Cc: Sandra Loosemore, gcc-patches, Koval, Julia, kirill.yukhin On Thu, May 25, 2017 at 8:22 AM, Peryt, Sebastian <sebastian.peryt@intel.com> wrote: > Hi, > > Thank you very much for the answers. Can someone please commit this patch for me? Committed as r248468. Uros. ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-05-25 19:42 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-04-26 15:37 [PATCH] Match x86 family machine constraints section with constarints.md Peryt, Sebastian 2017-04-27 21:03 ` Sandra Loosemore 2017-04-28 9:31 ` Peryt, Sebastian 2017-05-23 9:18 ` Peryt, Sebastian 2017-05-23 15:49 ` Sandra Loosemore 2017-05-24 13:40 ` Uros Bizjak 2017-05-25 6:50 ` Peryt, Sebastian 2017-05-25 19:56 ` Uros Bizjak
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