* [arm-embedded] [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions
@ 2016-07-11 18:25 Thomas Preudhomme
0 siblings, 0 replies; 3+ messages in thread
From: Thomas Preudhomme @ 2016-07-11 18:25 UTC (permalink / raw)
To: gcc-patches
We've decided to apply the following patch to ARM/embedded-6-branch.
Best regards,
Thomas
---------- Forwarded Message ----------
Subject: Re: [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2
only == ARMv7-M assumptions
Date: Wednesday 06 July 2016, 17:20:04
From: Ramana Radhakrishnan <ramana.gcc@googlemail.com>
To: Thomas Preudhomme <thomas.preudhomme@foss.arm.com>
CC: gcc-patches <gcc-patches@gcc.gnu.org>
On Mon, Jun 27, 2016 at 5:51 PM, Thomas Preudhomme
<thomas.preudhomme@foss.arm.com> wrote:
> Hi Ramana,
>
> On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote:
>>
>> From here down to ....
>>
>> > -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
>> > - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
>> > - || defined(__ARM_ARCH_5TEJ__)
>> > -#define HAVE_ARM_CLZ 1
>> > -#endif
>> > -
>> >
>> > #ifdef L_clzsi2
>> >
>> > -#if defined(__ARM_ARCH_6M__)
>> > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
>> >
>> > FUNC_START clzsi2
>> >
>> > mov r1, #28
>> > mov r3, #1
>> >
>> > @@ -1544,7 +1538,7 @@ FUNC_START clzsi2
>> >
>> > FUNC_END clzsi2
>> >
>> > #else
>> > ARM_FUNC_START clzsi2
>> >
>> > -# if defined(HAVE_ARM_CLZ)
>> > +# if defined(__ARM_FEATURE_CLZ)
>> >
>> > clz r0, r0
>> > RET
>> >
>> > # else
>> >
>> > @@ -1568,15 +1562,15 @@ ARM_FUNC_START clzsi2
>> >
>> > .align 2
>> > 1:
>> > .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0
>> >
>> > -# endif /* !HAVE_ARM_CLZ */
>> > +# endif /* !__ARM_FEATURE_CLZ */
>> >
>> > FUNC_END clzsi2
>> >
>> > #endif
>> > #endif /* L_clzsi2 */
>> >
>> > #ifdef L_clzdi2
>> >
>> > -#if !defined(HAVE_ARM_CLZ)
>> > +#if !defined(__ARM_FEATURE_CLZ)
>>
>> here should be it's own little patchlet and can go in separately.
>
> The patch in attachment changes the CLZ availability check in libgcc to test
> ISA supported and architecture version rather than encode a specific list of
> architectures. __ARM_FEATURE_CLZ is not used because its value depends on
what
> mode the user is targeting but only the architecture support matters in this
> case. Indeed, the code using CLZ is written in assembler and uses mnemonics
> available both in ARM and Thumb mode so only CLZ availability in one of the
> mode matters.
>
> This change was split out from [PATCH, GCC, ARM 1/7] Fix Thumb-1 only ==
> ARMv6-M & Thumb-2 only == ARMv7-M assumptions.
>
> ChangeLog entry is as follows:
>
> *** libgcc/ChangeLog ***
>
> 2016-06-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later
> and ARMv5t* rather than for a fixed list of architectures.
>
> Looking for code generation change accross a number of combinations of ISAs
> (ARM/Thumb), optimization levels (Os/O2), and architectures (armv4, armv4t,
> armv5, armv5t, armv5te, armv6, armv6j, armv6k, armv6s-m, armv6kz, armv6t2,
> armv6z, armv6zk, armv7, armv7-a, armv7e-m, armv7-m, armv7-r, armv7ve, armv8-
a,
> armv8-a+crc, iwmmxt and iwmmxt2) shows that only ARMv5T is impacted (uses
CLZ
> now). This is expected because currently HAVE_ARM_CLZ is not defined for this
> architecture while the ARMv7-a/ARMv7-R Architecture Reference Manual [1]
> states that all ARMv5T* architectures have CLZ. ARMv5E should also be
impacted
> (not using CLZ anymore) but testing it is difficult since current binutils
does
> not support ARMv5E.
>
> [1] Document ARM DDI0406C in http://infocenter.arm.com
>
> Best regards,
>
> Thomas
OK.
Ramana
-----------------------------------------
^ permalink raw reply [flat|nested] 3+ messages in thread
* [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions
@ 2015-12-17 5:57 Thomas Preud'homme
2015-12-17 7:01 ` Thomas Preud'homme
0 siblings, 1 reply; 3+ messages in thread
From: Thomas Preud'homme @ 2015-12-17 5:57 UTC (permalink / raw)
To: gcc-patches
Hi,
We decided to apply the following patch to the ARM embedded 5 branch. This is *not* intended for trunk for now. We will send a separate email for trunk.
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch fixes some assumptions related to M profile architectures. Currently GCC (mostly libgcc) contains several assumptions that the only ARM architecture with Thumb-1 only instructions is ARMv6-M and the only one with Thumb-2 only instructions is ARMv7-M. ARMv8-M [1] make this wrong since ARMv8-M baseline is also (mostly) Thumb-1 only and ARMv8-M mainline is also Thumb-2 only. This patch replace checks for __ARM_ARCH_*__ for checks against __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM instead. For instance, Thumb-1 only can be checked with #if !defined(__ARM_ARCH_ISA_ARM) && (__ARM_ARCH_ISA_THUMB == 1). It also fixes the guard for DIV code to not apply to ARMv8-M Baseline since it uses Thumb-2 instructions.
[1] For a quick overview of ARMv8-M please refer to the initial cover letter.
ChangeLog entries are as follow:
*** gcc/ChangeLog ***
2015-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to
decide whether to prevent some libgcc routines being included for some
multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the
link between this condition and the one in
libgcc/config/arm/lib1func.S.
* config/arm/arm.h (TARGET_ARM_V6M): Add check to TARGET_ARM_ARCH.
(TARGET_ARM_V7M): Likewise.
*** gcc/testsuite/ChangeLog ***
2015-11-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* lib/target-supports.exp (check_effective_target_arm_cortex_m): Use
__ARM_ARCH_ISA_ARM to test for Cortex-M devices.
*** libgcc/ChangeLog ***
2015-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/bpabi-v6m.S: Fix header comment to mention Thumb-1 rather
than ARMv6-M.
* config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases
for all Thumb-1 only targets.
(__only_thumb1__): Define for all Thumb-1 only targets.
(THUMB_LDIV0): Test for __only_thumb1__ rather than __ARM_ARCH_6M__.
(EQUIV): Likewise.
(ARM_FUNC_ALIAS): Likewise.
(umodsi3): Add check to __only_thumb1__ to guard the idiv version.
(modsi3): Likewise.
(HAVE_ARM_CLZ): Test for __only_thumb1__ rather than __ARM_ARCH_6M__.
(clzsi2): Likewise.
(clzdi2): Likewise.
(ctzsi2): Likewise.
(L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than
__ARM_ARCH_6M__ in guard for checking whether it is defined.
(final includes): Test for __only_thumb1__ rather than
__ARM_ARCH_6M__ and add comment to indicate the connection between
this condition and the one in gcc/config/arm/elf.h.
* config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and
__ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.
* config/arm/t-softfp: Likewise.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 6ed8ad3..06abcf3 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2181,8 +2181,10 @@ extern int making_const_table;
#define TARGET_ARM_ARCH \
(arm_base_arch) \
-#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
-#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
+#define TARGET_ARM_V6M (TARGET_ARM_ARCH == BASE_ARCH_6M && !arm_arch_notm \
+ && !arm_arch_thumb2)
+#define TARGET_ARM_V7M (TARGET_ARM_ARCH == BASE_ARCH_7M && !arm_arch_notm \
+ && arm_arch_thumb2)
/* The highest Thumb instruction set version supported by the chip. */
#define TARGET_ARM_ARCH_ISA_THUMB \
diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h
index 3795728..579a580 100644
--- a/gcc/config/arm/elf.h
+++ b/gcc/config/arm/elf.h
@@ -148,8 +148,9 @@
while (0)
/* Horrible hack: We want to prevent some libgcc routines being included
- for some multilibs. */
-#ifndef __ARM_ARCH_6M__
+ for some multilibs. The condition should match the one in
+ libgcc/config/arm/lib1funcs.S. */
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
#undef L_fixdfsi
#undef L_fixunsdfsi
#undef L_truncdfsf2
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 254c4e3..6cf7ee1 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3210,10 +3210,8 @@ proc check_effective_target_arm_cortex_m { } {
return 0
}
return [check_no_compiler_messages arm_cortex_m assembly {
- #if !defined(__ARM_ARCH_7M__) \
- && !defined (__ARM_ARCH_7EM__) \
- && !defined (__ARM_ARCH_6M__)
- #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__
+ #if defined(__ARM_ARCH_ISA_ARM)
+ #error __ARM_ARCH_ISA_ARM is defined
#endif
int i;
} "-mthumb"]
diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S
index a1e1640..9ae0bb8 100644
--- a/libgcc/config/arm/bpabi-v6m.S
+++ b/libgcc/config/arm/bpabi-v6m.S
@@ -1,4 +1,4 @@
-/* Miscellaneous BPABI functions. ARMv6M implementation
+/* Miscellaneous BPABI functions. Thumb-1 only implementation
Copyright (C) 2006-2015 Free Software Foundation, Inc.
Contributed by CodeSourcery.
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 252efcb..befb042 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
&& !defined(__thumb2__) \
&& (!defined(__THUMB_INTERWORK__) \
|| defined (__OPTIMIZE_SIZE__) \
- || defined(__ARM_ARCH_6M__)))
+ || !__ARM_ARCH_ISA_ARM))
# define __prefer_thumb__
#endif
@@ -305,7 +305,7 @@ LSYM(Lend_fde):
#ifdef __ARM_EABI__
.macro THUMB_LDIV0 name signed
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
.ifc \signed, unsigned
cmp r0, #0
beq 1f
@@ -478,7 +478,7 @@ _L__\name:
#else /* !(__INTERWORKING_STUBS__ || __thumb2__) */
-#ifdef __ARM_ARCH_6M__
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
#define EQUIV .thumb_set
#else
.macro ARM_FUNC_START name sp_section=
@@ -510,7 +510,7 @@ SYM (__\name):
#endif
.endm
-#ifndef __ARM_ARCH_6M__
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
.macro ARM_FUNC_ALIAS new old
.globl SYM (__\new)
EQUIV SYM (__\new), SYM (__\old)
@@ -1054,7 +1054,7 @@ ARM_FUNC_START aeabi_uidivmod
/* ------------------------------------------------------------------------ */
#ifdef L_umodsi3
-#ifdef __ARM_ARCH_EXT_IDIV__
+#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
ARM_FUNC_START umodsi3
@@ -1240,7 +1240,7 @@ ARM_FUNC_START aeabi_idivmod
/* ------------------------------------------------------------------------ */
#ifdef L_modsi3
-#if defined(__ARM_ARCH_EXT_IDIV__)
+#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
ARM_FUNC_START modsi3
@@ -1508,14 +1508,14 @@ LSYM(Lover12):
#endif /* __symbian__ */
-#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
+#if ((__ARM_ARCH__ > 5) && (__ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1)) \
|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
|| defined(__ARM_ARCH_5TEJ__)
#define HAVE_ARM_CLZ 1
#endif
#ifdef L_clzsi2
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START clzsi2
mov r1, #28
mov r3, #1
@@ -1576,7 +1576,7 @@ ARM_FUNC_START clzsi2
#ifdef L_clzdi2
#if !defined(HAVE_ARM_CLZ)
-# if defined(__ARM_ARCH_6M__)
+# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START clzdi2
push {r4, lr}
# else
@@ -1601,7 +1601,7 @@ ARM_FUNC_START clzdi2
bl __clzsi2
# endif
2:
-# if defined(__ARM_ARCH_6M__)
+# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
pop {r4, pc}
# else
RETLDM r4
@@ -1623,7 +1623,7 @@ ARM_FUNC_START clzdi2
#endif /* L_clzdi2 */
#ifdef L_ctzsi2
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START ctzsi2
neg r1, r0
and r0, r0, r1
@@ -1738,7 +1738,7 @@ ARM_FUNC_START ctzsi2
/* Don't bother with the old interworking routines for Thumb-2. */
/* ??? Maybe only omit these on "m" variants. */
-#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__)
+#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM
#if defined L_interwork_call_via_rX
@@ -1983,11 +1983,12 @@ LSYM(Lchange_\register):
.endm
#ifndef __symbian__
-#ifndef __ARM_ARCH_6M__
+/* The condition here must match the one in gcc/config/arm/elf.h. */
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
#include "ieee754-df.S"
#include "ieee754-sf.S"
#include "bpabi.S"
-#else /* __ARM_ARCH_6M__ */
+#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 */
#include "bpabi-v6m.S"
-#endif /* __ARM_ARCH_6M__ */
+#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 */
#endif /* !__symbian__ */
diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S
index cac1022..393ec8a 100644
--- a/libgcc/config/arm/libunwind.S
+++ b/libgcc/config/arm/libunwind.S
@@ -58,7 +58,7 @@
#endif
#endif
-#ifdef __ARM_ARCH_6M__
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
/* r0 points to a 16-word block. Upload these values to the actual core
state. */
@@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC
UNPREFIX \name
.endm
-#else /* !__ARM_ARCH_6M__ */
+#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
/* r0 points to a 16-word block. Upload these values to the actual core
state. */
@@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC
UNPREFIX \name
.endm
-#endif /* !__ARM_ARCH_6M__ */
+#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
UNWIND_WRAPPER _Unwind_RaiseException 1
UNWIND_WRAPPER _Unwind_Resume 1
diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp
index 4ede438..554ec9b 100644
--- a/libgcc/config/arm/t-softfp
+++ b/libgcc/config/arm/t-softfp
@@ -1,2 +1,2 @@
-softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__'
+softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1'
softfp_wrap_end := '\#endif'
Testing:
* Toolchain was built successfully with and without the ARMv8-M support patches with the following multilib list: armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o, crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a and libsupc++.a is unchanged for all these targets.
* GCC also showed no testsuite regression when targeting ARMv8-M Baseline compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and ARMv7-M (compared to without the patch)
* GCC was bootstrapped successfully targeting Thumb-1 and targeting Thumb-2
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions
2015-12-17 5:57 [arm-embedded][PATCH, " Thomas Preud'homme
@ 2015-12-17 7:01 ` Thomas Preud'homme
0 siblings, 0 replies; 3+ messages in thread
From: Thomas Preud'homme @ 2015-12-17 7:01 UTC (permalink / raw)
To: gcc-patches
The following was committed, once rebased on top of the embedded branch (patch was generated on top of gcc-5-branch):
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8c10ea3c9053e89b8eae1e5353b92d6020499409..bf1a0e874b1669f3ebe1e5870556a46b80686b82 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2336,8 +2336,10 @@ extern int making_const_table;
#define TARGET_ARM_ARCH \
(arm_base_arch) \
-#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
-#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
+#define TARGET_ARM_V6M (TARGET_ARM_ARCH == BASE_ARCH_6M && !arm_arch_notm \
+ && !arm_arch_thumb2)
+#define TARGET_ARM_V7M (TARGET_ARM_ARCH == BASE_ARCH_7M && !arm_arch_notm \
+ && arm_arch_thumb2)
/* The highest Thumb instruction set version supported by the chip. */
#define TARGET_ARM_ARCH_ISA_THUMB \
diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h
index c56bbdff69466af8b2e8db70f99f33054748b650..fe06cd1a2857db44fb7c1d9407aa6710a061d4df 100644
--- a/gcc/config/arm/elf.h
+++ b/gcc/config/arm/elf.h
@@ -149,8 +149,9 @@
while (0)
/* Horrible hack: We want to prevent some libgcc routines being included
- for some multilibs. */
-#ifndef __ARM_ARCH_6M__
+ for some multilibs. The condition should match the one in
+ libgcc/config/arm/lib1funcs.S. */
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
#undef L_fixdfsi
#undef L_fixunsdfsi
#undef L_truncdfsf2
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 950db11637636f46e805beee3bd55ead62aec67e..35867a281a01cbbb3810013b17e3b2173eb275ee 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2973,10 +2973,8 @@ proc check_effective_target_arm_cortex_m { } {
return 0
}
return [check_no_compiler_messages arm_cortex_m assembly {
- #if !defined(__ARM_ARCH_7M__) \
- && !defined (__ARM_ARCH_7EM__) \
- && !defined (__ARM_ARCH_6M__)
- #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__
+ #if defined(__ARM_ARCH_ISA_ARM)
+ #error __ARM_ARCH_ISA_ARM is defined
#endif
int i;
} "-mthumb"]
diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S
index a1e164032a08d04f7e8be80094d3b054b4e8bed4..9ae0bb82d1b3e3f81baf73e11b484f4212ea28e4 100644
--- a/libgcc/config/arm/bpabi-v6m.S
+++ b/libgcc/config/arm/bpabi-v6m.S
@@ -1,4 +1,4 @@
-/* Miscellaneous BPABI functions. ARMv6M implementation
+/* Miscellaneous BPABI functions. Thumb-1 only implementation
Copyright (C) 2006-2015 Free Software Foundation, Inc.
Contributed by CodeSourcery.
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index a1e41c292b22bcbd6b6ec9e11060d7a1f6e28fba..e8fd73f48a197fe4b81eaf73c13a11f913bba9e0 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
&& !defined(__thumb2__) \
&& (!defined(__THUMB_INTERWORK__) \
|| defined (__OPTIMIZE_SIZE__) \
- || defined(__ARM_ARCH_6M__)))
+ || !__ARM_ARCH_ISA_ARM))
# define __prefer_thumb__
#endif
@@ -305,7 +305,7 @@ LSYM(Lend_fde):
#ifdef __ARM_EABI__
.macro THUMB_LDIV0 name signed
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
push {r0, lr}
mov r0, #0
@@ -456,7 +456,7 @@ _L__\name:
#else /* !(__INTERWORKING_STUBS__ || __thumb2__) */
-#ifdef __ARM_ARCH_6M__
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
#define EQUIV .thumb_set
#else
.macro ARM_FUNC_START name sp_section=
@@ -488,7 +488,7 @@ SYM (__\name):
#endif
.endm
-#ifndef __ARM_ARCH_6M__
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
.macro ARM_FUNC_ALIAS new old
.globl SYM (__\new)
EQUIV SYM (__\new), SYM (__\old)
@@ -1213,7 +1213,7 @@ ARM_FUNC_START aeabi_uidivmod
/* ------------------------------------------------------------------------ */
#ifdef L_umodsi3
-#ifdef __ARM_ARCH_EXT_IDIV__
+#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
ARM_FUNC_START umodsi3
@@ -1424,7 +1424,7 @@ ARM_FUNC_START aeabi_idivmod
/* ------------------------------------------------------------------------ */
#ifdef L_modsi3
-#if defined(__ARM_ARCH_EXT_IDIV__)
+#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
ARM_FUNC_START modsi3
@@ -1685,14 +1685,14 @@ LSYM(Lover12):
#endif /* __symbian__ */
-#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
+#if ((__ARM_ARCH__ > 5) && (__ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1)) \
|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
|| defined(__ARM_ARCH_5TEJ__)
#define HAVE_ARM_CLZ 1
#endif
#ifdef L_clzsi2
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START clzsi2
mov r1, #28
mov r3, #1
@@ -1753,7 +1753,7 @@ ARM_FUNC_START clzsi2
#ifdef L_clzdi2
#if !defined(HAVE_ARM_CLZ)
-# if defined(__ARM_ARCH_6M__)
+# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START clzdi2
push {r4, lr}
# else
@@ -1778,7 +1778,7 @@ ARM_FUNC_START clzdi2
bl __clzsi2
# endif
2:
-# if defined(__ARM_ARCH_6M__)
+# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
pop {r4, pc}
# else
RETLDM r4
@@ -1800,7 +1800,7 @@ ARM_FUNC_START clzdi2
#endif /* L_clzdi2 */
#ifdef L_ctzsi2
-#if defined(__ARM_ARCH_6M__)
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
FUNC_START ctzsi2
neg r1, r0
and r0, r0, r1
@@ -1915,7 +1915,7 @@ ARM_FUNC_START ctzsi2
/* Don't bother with the old interworking routines for Thumb-2. */
/* ??? Maybe only omit these on "m" variants. */
-#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__)
+#if __ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
#if defined L_interwork_call_via_rX
@@ -2150,11 +2150,12 @@ LSYM(Lchange_\register):
#endif /* Arch supports thumb. */
#ifndef __symbian__
-#ifndef __ARM_ARCH_6M__
+/* The condition here must match the one in gcc/config/arm/elf.h. */
+#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
#include "ieee754-df.S"
#include "ieee754-sf.S"
#include "bpabi.S"
-#else /* __ARM_ARCH_6M__ */
+#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 */
#include "bpabi-v6m.S"
-#endif /* __ARM_ARCH_6M__ */
+#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 */
#endif /* !__symbian__ */
diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S
index cac102231914aa85320ff579168a17afa8479f67..393ec8aaee43948154956b72960860902400df50 100644
--- a/libgcc/config/arm/libunwind.S
+++ b/libgcc/config/arm/libunwind.S
@@ -58,7 +58,7 @@
#endif
#endif
-#ifdef __ARM_ARCH_6M__
+#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
/* r0 points to a 16-word block. Upload these values to the actual core
state. */
@@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC
UNPREFIX \name
.endm
-#else /* !__ARM_ARCH_6M__ */
+#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
/* r0 points to a 16-word block. Upload these values to the actual core
state. */
@@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC
UNPREFIX \name
.endm
-#endif /* !__ARM_ARCH_6M__ */
+#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
UNWIND_WRAPPER _Unwind_RaiseException 1
UNWIND_WRAPPER _Unwind_Resume 1
diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp
index 4ede438baf6a297737e52db00395f6c3a359f681..554ec9bc47b04445e79e84b1f957bf88680c08d1 100644
--- a/libgcc/config/arm/t-softfp
+++ b/libgcc/config/arm/t-softfp
@@ -1,2 +1,2 @@
-softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__'
+softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1'
softfp_wrap_end := '\#endif'
Best regards,
Thomas
> -----Original Message-----
> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> owner@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Thursday, December 17, 2015 1:58 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only ==
> ARMv6-M & Thumb-2 only == ARMv7-M assumptions
>
> Hi,
>
> We decided to apply the following patch to the ARM embedded 5 branch.
> This is *not* intended for trunk for now. We will send a separate email
> for trunk.
>
> This patch is part of a patch series to add support for ARMv8-M[1] to GCC.
> This specific patch fixes some assumptions related to M profile
> architectures. Currently GCC (mostly libgcc) contains several assumptions
> that the only ARM architecture with Thumb-1 only instructions is ARMv6-
> M and the only one with Thumb-2 only instructions is ARMv7-M. ARMv8-
> M [1] make this wrong since ARMv8-M baseline is also (mostly) Thumb-1
> only and ARMv8-M mainline is also Thumb-2 only. This patch replace
> checks for __ARM_ARCH_*__ for checks against
> __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM instead. For
> instance, Thumb-1 only can be checked with
> #if !defined(__ARM_ARCH_ISA_ARM) && (__ARM_ARCH_ISA_THUMB
> == 1). It also fixes the guard for DIV code to not apply to ARMv8-M
> Baseline since it uses Thumb-2 instructions.
>
> [1] For a quick overview of ARMv8-M please refer to the initial cover
> letter.
>
> ChangeLog entries are as follow:
>
>
> *** gcc/ChangeLog ***
>
> 2015-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and
> __ARM_ARCH_ISA_ARM to
> decide whether to prevent some libgcc routines being included for
> some
> multilibs rather than __ARM_ARCH_6M__ and add comment to
> indicate the
> link between this condition and the one in
> libgcc/config/arm/lib1func.S.
> * config/arm/arm.h (TARGET_ARM_V6M): Add check to
> TARGET_ARM_ARCH.
> (TARGET_ARM_V7M): Likewise.
>
>
> *** gcc/testsuite/ChangeLog ***
>
> 2015-11-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * lib/target-supports.exp (check_effective_target_arm_cortex_m):
> Use
> __ARM_ARCH_ISA_ARM to test for Cortex-M devices.
>
>
> *** libgcc/ChangeLog ***
>
> 2015-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/bpabi-v6m.S: Fix header comment to mention Thumb-
> 1 rather
> than ARMv6-M.
> * config/arm/lib1funcs.S (__prefer_thumb__): Define among other
> cases
> for all Thumb-1 only targets.
> (__only_thumb1__): Define for all Thumb-1 only targets.
> (THUMB_LDIV0): Test for __only_thumb1__ rather than
> __ARM_ARCH_6M__.
> (EQUIV): Likewise.
> (ARM_FUNC_ALIAS): Likewise.
> (umodsi3): Add check to __only_thumb1__ to guard the idiv version.
> (modsi3): Likewise.
> (HAVE_ARM_CLZ): Test for __only_thumb1__ rather than
> __ARM_ARCH_6M__.
> (clzsi2): Likewise.
> (clzdi2): Likewise.
> (ctzsi2): Likewise.
> (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather
> than
> __ARM_ARCH_6M__ in guard for checking whether it is defined.
> (final includes): Test for __only_thumb1__ rather than
> __ARM_ARCH_6M__ and add comment to indicate the connection
> between
> this condition and the one in gcc/config/arm/elf.h.
> * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and
> __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.
> * config/arm/t-softfp: Likewise.
>
>
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index 6ed8ad3..06abcf3 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -2181,8 +2181,10 @@ extern int making_const_table;
> #define TARGET_ARM_ARCH \
> (arm_base_arch) \
>
> -#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
> -#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
> +#define TARGET_ARM_V6M (TARGET_ARM_ARCH == BASE_ARCH_6M
> && !arm_arch_notm \
> + && !arm_arch_thumb2)
> +#define TARGET_ARM_V7M (TARGET_ARM_ARCH == BASE_ARCH_7M
> && !arm_arch_notm \
> + && arm_arch_thumb2)
>
> /* The highest Thumb instruction set version supported by the chip. */
> #define TARGET_ARM_ARCH_ISA_THUMB \
> diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h
> index 3795728..579a580 100644
> --- a/gcc/config/arm/elf.h
> +++ b/gcc/config/arm/elf.h
> @@ -148,8 +148,9 @@
> while (0)
>
> /* Horrible hack: We want to prevent some libgcc routines being
> included
> - for some multilibs. */
> -#ifndef __ARM_ARCH_6M__
> + for some multilibs. The condition should match the one in
> + libgcc/config/arm/lib1funcs.S. */
> +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
> #undef L_fixdfsi
> #undef L_fixunsdfsi
> #undef L_truncdfsf2
> diff --git a/gcc/testsuite/lib/target-supports.exp
> b/gcc/testsuite/lib/target-supports.exp
> index 254c4e3..6cf7ee1 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -3210,10 +3210,8 @@ proc check_effective_target_arm_cortex_m { }
> {
> return 0
> }
> return [check_no_compiler_messages arm_cortex_m assembly {
> - #if !defined(__ARM_ARCH_7M__) \
> - && !defined (__ARM_ARCH_7EM__) \
> - && !defined (__ARM_ARCH_6M__)
> - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__
> && !__ARM_ARCH_6M__
> + #if defined(__ARM_ARCH_ISA_ARM)
> + #error __ARM_ARCH_ISA_ARM is defined
> #endif
> int i;
> } "-mthumb"]
> diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-
> v6m.S
> index a1e1640..9ae0bb8 100644
> --- a/libgcc/config/arm/bpabi-v6m.S
> +++ b/libgcc/config/arm/bpabi-v6m.S
> @@ -1,4 +1,4 @@
> -/* Miscellaneous BPABI functions. ARMv6M implementation
> +/* Miscellaneous BPABI functions. Thumb-1 only implementation
>
> Copyright (C) 2006-2015 Free Software Foundation, Inc.
> Contributed by CodeSourcery.
> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
> index 252efcb..befb042 100644
> --- a/libgcc/config/arm/lib1funcs.S
> +++ b/libgcc/config/arm/lib1funcs.S
> @@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME
> respectively. If not, see
> && !defined(__thumb2__) \
> && (!defined(__THUMB_INTERWORK__) \
> || defined (__OPTIMIZE_SIZE__) \
> - || defined(__ARM_ARCH_6M__)))
> + || !__ARM_ARCH_ISA_ARM))
> # define __prefer_thumb__
> #endif
>
> @@ -305,7 +305,7 @@ LSYM(Lend_fde):
>
> #ifdef __ARM_EABI__
> .macro THUMB_LDIV0 name signed
> -#if defined(__ARM_ARCH_6M__)
> +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> .ifc \signed, unsigned
> cmp r0, #0
> beq 1f
> @@ -478,7 +478,7 @@ _L__\name:
>
> #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */
>
> -#ifdef __ARM_ARCH_6M__
> +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> #define EQUIV .thumb_set
> #else
> .macro ARM_FUNC_START name sp_section=
> @@ -510,7 +510,7 @@ SYM (__\name):
> #endif
> .endm
>
> -#ifndef __ARM_ARCH_6M__
> +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
> .macro ARM_FUNC_ALIAS new old
> .globl SYM (__\new)
> EQUIV SYM (__\new), SYM (__\old)
> @@ -1054,7 +1054,7 @@ ARM_FUNC_START aeabi_uidivmod
> /* ------------------------------------------------------------------------ */
> #ifdef L_umodsi3
>
> -#ifdef __ARM_ARCH_EXT_IDIV__
> +#if defined(__ARM_ARCH_EXT_IDIV__) &&
> __ARM_ARCH_ISA_THUMB != 1
>
> ARM_FUNC_START umodsi3
>
> @@ -1240,7 +1240,7 @@ ARM_FUNC_START aeabi_idivmod
> /* ------------------------------------------------------------------------ */
> #ifdef L_modsi3
>
> -#if defined(__ARM_ARCH_EXT_IDIV__)
> +#if defined(__ARM_ARCH_EXT_IDIV__) &&
> __ARM_ARCH_ISA_THUMB != 1
>
> ARM_FUNC_START modsi3
>
> @@ -1508,14 +1508,14 @@ LSYM(Lover12):
>
> #endif /* __symbian__ */
>
> -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
> +#if ((__ARM_ARCH__ > 5) && (__ARM_ARCH_ISA_ARM ||
> __ARM_ARCH_ISA_THUMB != 1)) \
> || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
> || defined(__ARM_ARCH_5TEJ__)
> #define HAVE_ARM_CLZ 1
> #endif
>
> #ifdef L_clzsi2
> -#if defined(__ARM_ARCH_6M__)
> +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> FUNC_START clzsi2
> mov r1, #28
> mov r3, #1
> @@ -1576,7 +1576,7 @@ ARM_FUNC_START clzsi2
> #ifdef L_clzdi2
> #if !defined(HAVE_ARM_CLZ)
>
> -# if defined(__ARM_ARCH_6M__)
> +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> FUNC_START clzdi2
> push {r4, lr}
> # else
> @@ -1601,7 +1601,7 @@ ARM_FUNC_START clzdi2
> bl __clzsi2
> # endif
> 2:
> -# if defined(__ARM_ARCH_6M__)
> +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> pop {r4, pc}
> # else
> RETLDM r4
> @@ -1623,7 +1623,7 @@ ARM_FUNC_START clzdi2
> #endif /* L_clzdi2 */
>
> #ifdef L_ctzsi2
> -#if defined(__ARM_ARCH_6M__)
> +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
> FUNC_START ctzsi2
> neg r1, r0
> and r0, r0, r1
> @@ -1738,7 +1738,7 @@ ARM_FUNC_START ctzsi2
>
> /* Don't bother with the old interworking routines for Thumb-2. */
> /* ??? Maybe only omit these on "m" variants. */
> -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__)
> +#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM
>
> #if defined L_interwork_call_via_rX
>
> @@ -1983,11 +1983,12 @@ LSYM(Lchange_\register):
> .endm
>
> #ifndef __symbian__
> -#ifndef __ARM_ARCH_6M__
> +/* The condition here must match the one in gcc/config/arm/elf.h. */
> +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
> #include "ieee754-df.S"
> #include "ieee754-sf.S"
> #include "bpabi.S"
> -#else /* __ARM_ARCH_6M__ */
> +#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB ==
> 1 */
> #include "bpabi-v6m.S"
> -#endif /* __ARM_ARCH_6M__ */
> +#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB ==
> 1 */
> #endif /* !__symbian__ */
> diff --git a/libgcc/config/arm/libunwind.S
> b/libgcc/config/arm/libunwind.S
> index cac1022..393ec8a 100644
> --- a/libgcc/config/arm/libunwind.S
> +++ b/libgcc/config/arm/libunwind.S
> @@ -58,7 +58,7 @@
> #endif
> #endif
>
> -#ifdef __ARM_ARCH_6M__
> +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
>
> /* r0 points to a 16-word block. Upload these values to the actual core
> state. */
> @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC
> UNPREFIX \name
> .endm
>
> -#else /* !__ARM_ARCH_6M__ */
> +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
> */
>
> /* r0 points to a 16-word block. Upload these values to the actual core
> state. */
> @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC
> UNPREFIX \name
> .endm
>
> -#endif /* !__ARM_ARCH_6M__ */
> +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
> */
>
> UNWIND_WRAPPER _Unwind_RaiseException 1
> UNWIND_WRAPPER _Unwind_Resume 1
> diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp
> index 4ede438..554ec9b 100644
> --- a/libgcc/config/arm/t-softfp
> +++ b/libgcc/config/arm/t-softfp
> @@ -1,2 +1,2 @@
> -softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__'
> +softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM &&
> __ARM_ARCH_ISA_THUMB == 1'
> softfp_wrap_end := '\#endif'
>
>
> Testing:
>
> * Toolchain was built successfully with and without the ARMv8-M
> support patches with the following multilib list: armv6-m,armv7-
> m,armv7e-m,cortex-m7. The code generation for crtbegin.o, crtend.o,
> crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, libgloss-linux.a, libm.a,
> libnosys.a, librdimon.a, librdpmon.a, libstdc++.a and libsupc++.a is
> unchanged for all these targets.
>
> * GCC also showed no testsuite regression when targeting ARMv8-M
> Baseline compared to ARMv6-M on ARM Fast Models and when
> targeting ARMv6-M and ARMv7-M (compared to without the patch)
> * GCC was bootstrapped successfully targeting Thumb-1 and targeting
> Thumb-2
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2016-07-11 18:25 UTC | newest]
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2016-07-11 18:25 [arm-embedded] [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions Thomas Preudhomme
-- strict thread matches above, loose matches on Subject: below --
2015-12-17 5:57 [arm-embedded][PATCH, " Thomas Preud'homme
2015-12-17 7:01 ` Thomas Preud'homme
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