* MIPS 74k scheduler adjustments
@ 2007-07-04 13:28 Joseph S. Myers
2007-07-04 16:26 ` Richard Sandiford
2007-07-07 7:35 ` Fu, Chao-Ying
0 siblings, 2 replies; 7+ messages in thread
From: Joseph S. Myers @ 2007-07-04 13:28 UTC (permalink / raw)
To: gcc-patches; +Cc: David Ung
This patch adjusts the MIPS 74k scheduler to reflect that certain
arithmetic instructions take only 1 cycle. This in turn requires various
instructions to be marked as "logical", "signext" or "move" instead of
"arith".
Tested with no regressions with cross to mips-linux-gnu. OK to commit?
2007-07-04 David Ung <davidu@mips.com>
Joseph Myers <joseph@codesourcery.com>
gcc/
* config/mips/mips.md (type): Add logical, signext and move.
(one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
*ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
*nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
combinations", *zero_extend<SHORT:mode><GPR:mode>2,
*zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
*movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
*movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
*movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
movv2sf_hardfloat_64bit): Use the new types.
(*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
*movdf_softfloat, *movdf_mips16): Use "multi".
(extendqihi2): Replace with a define_expand.
(*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
Based on extend<SHORT:mode><GPR:mode>2 patterns.
* config/mips/74k.md (r74k_int_logical): New reservation and
bypasses.
(r74k_int_arith): Remove "slt".
* config/mips/24k.md, config/mips/4130.md, config/mips/4k.md,
config/mips/5400.md, config/mips/5500.md, config/mips/5k.md,
config/mips/7000.md, config/mips/9000.md, config/mips/generic.md,
config/mips/sb1.md, config/mips/sr71k.md: Add new types to
reservations for "arith".
Index: gcc/config/mips/4130.md
===================================================================
--- gcc/config/mips/4130.md (revision 126276)
+++ gcc/config/mips/4130.md (working copy)
@@ -66,7 +66,7 @@
(define_insn_reservation "vr4130_int" 1
(and (eq_attr "cpu" "r4130")
- (eq_attr "type" "const,arith,shift,slt,nop"))
+ (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
"vr4130_alu1 | vr4130_alu2")
(define_insn_reservation "vr4130_load" 3
Index: gcc/config/mips/7000.md
===================================================================
--- gcc/config/mips/7000.md (revision 126276)
+++ gcc/config/mips/7000.md (working copy)
@@ -88,7 +88,7 @@
(define_insn_reservation "rm7_int_other" 1
(and (eq_attr "cpu" "r7000")
- (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
+ (eq_attr "type" "arith,shift,signext,slt,clz,const,condmove,logical,move,nop,trap"))
"rm7_iaddsub")
(define_insn_reservation "rm7_ld" 2
Index: gcc/config/mips/9000.md
===================================================================
--- gcc/config/mips/9000.md (revision 126276)
+++ gcc/config/mips/9000.md (working copy)
@@ -52,7 +52,7 @@
(define_insn_reservation "rm9k_int" 1
(and (eq_attr "cpu" "r9000")
- (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+ (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
"rm9k_any1 | rm9k_any2")
(define_insn_reservation "rm9k_int_cmove" 2
Index: gcc/config/mips/5400.md
===================================================================
--- gcc/config/mips/5400.md (revision 126276)
+++ gcc/config/mips/5400.md (working copy)
@@ -60,7 +60,7 @@
(define_insn_reservation "ir_vr54_arith" 1
(and (eq_attr "cpu" "r5400")
- (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+ (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_si" 3
Index: gcc/config/mips/generic.md
===================================================================
--- gcc/config/mips/generic.md (revision 126276)
+++ gcc/config/mips/generic.md (working copy)
@@ -24,7 +24,7 @@
(define_insn_reservation "generic_alu" 1
(eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
- shift,slt,clz,trap,multi,nop")
+ shift,slt,clz,trap,multi,nop,logical,signext,move")
"alu")
(define_insn_reservation "generic_load" 3
Index: gcc/config/mips/5500.md
===================================================================
--- gcc/config/mips/5500.md (revision 126276)
+++ gcc/config/mips/5500.md (working copy)
@@ -56,7 +56,7 @@
(define_insn_reservation "ir_vr55_arith" 1
(and (eq_attr "cpu" "r5500")
- (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+ (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
"vr55_dp0|vr55_dp1")
(define_bypass 2
Index: gcc/config/mips/24k.md
===================================================================
--- gcc/config/mips/24k.md (revision 126276)
+++ gcc/config/mips/24k.md (working copy)
@@ -55,7 +55,7 @@
;; differentiate between integer/float moves)
(define_insn_reservation "r24k_int_arith" 1
(and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
- (eq_attr "type" "arith,const,nop,shift,slt"))
+ (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
"r24k_iss+r24k_ixu_arith")
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md (revision 126276)
+++ gcc/config/mips/mips.md (working copy)
@@ -252,15 +252,18 @@
;; mthilo transfer to hi/lo registers
;; mfhilo transfer from hi/lo registers
;; const load constant
-;; arith integer arithmetic and logical instructions
+;; arith integer arithmetic instructions
+;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
+;; signext sign extend instuctions
;; clz the clz and clo instructions
;; trap trap if instructions
;; imul integer multiply 2 operands
;; imul3 integer multiply 3 operands
;; imadd integer multiply-add
;; idiv integer divide
+;; move integer register move (ADD (rt=0) and ADDU (rt=0))
;; fmove floating point register move
;; fadd floating point add/subtract
;; fmul floating point multiply
@@ -280,7 +283,7 @@
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
@@ -2110,7 +2113,7 @@
else
return "nor\t%0,%.,%1";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
\f
;;
@@ -2142,7 +2145,7 @@
"@
and\t%0,%1,%2
andi\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn "*and<mode>3_mips16"
@@ -2151,7 +2154,7 @@
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"and\t%0,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_expand "ior<mode>3"
@@ -2172,7 +2175,7 @@
"@
or\t%0,%1,%2
ori\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn "*ior<mode>3_mips16"
@@ -2181,7 +2184,7 @@
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"or\t%0,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_expand "xor<mode>3"
@@ -2199,7 +2202,7 @@
"@
xor\t%0,%1,%2
xori\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn ""
@@ -2211,7 +2214,7 @@
xor\t%0,%2
cmpi\t%1,%2
cmp\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical,arith,arith")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
[(const_int 4)
@@ -2226,7 +2229,7 @@
(not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
"!TARGET_MIPS16"
"nor\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
\f
;;
@@ -2357,7 +2360,7 @@
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xffff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "SI")])
(define_insn ""
@@ -2366,7 +2369,7 @@
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "SI")])
(define_insn ""
@@ -2375,7 +2378,7 @@
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "HI")])
\f
;;
@@ -2453,7 +2456,7 @@
"@
andi\t%0,%1,<SHORT:mask>
l<SHORT:size>u\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "logical,load")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
@@ -2492,7 +2495,7 @@
"@
andi\t%0,%1,0x00ff
lbu\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "logical,load")
(set_attr "mode" "HI")])
(define_insn "*zero_extendqihi2_mips16"
@@ -2549,7 +2552,7 @@
"@
se<SHORT:size>\t%0
l<SHORT:size>\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "signext,load")
(set_attr "mode" "<GPR:MODE>")])
(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
@@ -2580,23 +2583,55 @@
"@
se<SHORT:size>\t%0,%1
l<SHORT:size>\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "signext,load")
(set_attr "mode" "<GPR:MODE>")])
-;; This pattern generates the same code as extendqisi2; split it into
-;; that form after reload.
-(define_insn_and_split "extendqihi2"
+(define_expand "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
+ "")
+
+(define_insn "*extendqihi2_mips16e"
[(set (match_operand:HI 0 "register_operand" "=d,d")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
- ""
- "#"
- "reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
- { operands[0] = gen_lowpart (SImode, operands[0]); }
- [(set_attr "type" "arith,load")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ seb\t%0
+ lb\t%0,%1"
+ [(set_attr "type" "signext,load")
+ (set_attr "mode" "SI")])
+
+(define_insn_and_split "*extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
+ "@
+ #
+ lb\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
+{
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
+ - GET_MODE_BITSIZE (QImode));
+}
+ [(set_attr "type" "multi,load")
(set_attr "mode" "SI")
(set_attr "length" "8,*")])
+(define_insn "*extendqihi2_seb"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "ISA_HAS_SEB_SEH"
+ "@
+ seb\t%0,%1
+ lb\t%0,%1"
+ [(set_attr "type" "signext,load")
+ (set_attr "mode" "SI")])
+
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
@@ -3320,7 +3355,7 @@
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,mtc,load,mfc,store")
+ [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
@@ -3331,7 +3366,7 @@
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
+ [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
@@ -3342,7 +3377,7 @@
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
+ [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
(set_attr "mode" "DI")
(set_attr "length" "8,8,8,8,12,*,*,8")])
@@ -3353,7 +3388,7 @@
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
+ [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
(set_attr "mode" "DI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
@@ -3364,7 +3399,7 @@
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,const,load,store")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
@@ -3449,7 +3484,7 @@
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
+ [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
(set_attr "mode" "SI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
@@ -3460,7 +3495,7 @@
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,const,load,store")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
@@ -3550,7 +3585,7 @@
(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,arith,load,store,mfc,mtc,fmove,fpload,fpstore")
+ [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
(set_attr "mode" "SI")
(set_attr "length" "8,4,*,*,4,4,4,*,*")])
@@ -3650,7 +3685,7 @@
mtc1\t%1,%0
mov.s\t%0,%1
mt%0\t%1"
- [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
+ [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
(set_attr "mode" "HI")
(set_attr "length" "4,4,*,*,4,4,4,4")])
@@ -3668,7 +3703,7 @@
#
lhu\t%0,%1
sh\t%1,%0"
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,load,store")
(set_attr "mode" "HI")
(set_attr_alternative "length"
[(const_int 4)
@@ -3757,7 +3792,7 @@
mtc1\t%1,%0
mov.s\t%0,%1
mt%0\t%1"
- [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
+ [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
(set_attr "mode" "QI")
(set_attr "length" "4,4,*,*,4,4,4,4")])
@@ -3775,7 +3810,7 @@
#
lbu\t%0,%1
sb\t%1,%0"
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,load,store")
(set_attr "mode" "QI")
(set_attr "length" "4,4,4,4,8,*,*")])
@@ -3827,7 +3862,7 @@
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
@@ -3838,7 +3873,7 @@
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,load,store")
+ [(set_attr "type" "move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,*,*")])
@@ -3849,7 +3884,7 @@
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,4,*,*")])
@@ -3872,7 +3907,7 @@
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
@@ -3884,7 +3919,7 @@
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
@@ -3895,7 +3930,7 @@
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,load,store,mfc,mtc,fmove")
+ [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
(set_attr "mode" "DF")
(set_attr "length" "8,*,*,4,4,4")])
@@ -3906,7 +3941,7 @@
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,load,store")
+ [(set_attr "type" "multi,multi,multi,load,store")
(set_attr "mode" "DF")
(set_attr "length" "8,8,8,*,*")])
@@ -3966,7 +4001,7 @@
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
Index: gcc/config/mips/4k.md
===================================================================
--- gcc/config/mips/4k.md (revision 126276)
+++ gcc/config/mips/4k.md (working copy)
@@ -127,7 +127,7 @@
;; All other integer insns.
(define_insn_reservation "r4k_int_alu" 1
(and (eq_attr "cpu" "4kc,4kp")
- (eq_attr "type" "arith,condmove,shift,const,nop,slt"))
+ (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
"r4k_ixu_arith")
(define_insn_reservation "r4k_int_branch" 1
Index: gcc/config/mips/5k.md
===================================================================
--- gcc/config/mips/5k.md (revision 126276)
+++ gcc/config/mips/5k.md (working copy)
@@ -101,7 +101,7 @@
;; All other integer insns.
(define_insn_reservation "r5k_int_alu" 1
(and (eq_attr "cpu" "5kc,5kf")
- (eq_attr "type" "arith,condmove,shift,const,nop,slt"))
+ (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
"r5k_ixu_arith")
(define_insn_reservation "r5k_int_branch" 1
Index: gcc/config/mips/sb1.md
===================================================================
--- gcc/config/mips/sb1.md (revision 126276)
+++ gcc/config/mips/sb1.md (working copy)
@@ -236,7 +236,7 @@
(define_insn_reservation "ir_sb1_simple_alu" 2
(and (eq_attr "cpu" "sb1")
- (eq_attr "type" "const,arith"))
+ (eq_attr "type" "const,arith,logical,move,signext"))
"sb1_ls1 | sb1_ex1 | sb1_ex0")
;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
@@ -244,7 +244,7 @@
(define_insn_reservation "ir_sb1a_simple_alu" 1
(and (eq_attr "cpu" "sb1a")
- (eq_attr "type" "const,arith"))
+ (eq_attr "type" "const,arith,logical,move,signext"))
"sb1_ex1 | sb1_ex0")
;; ??? condmove also includes some FP instructions that execute on the FP
Index: gcc/config/mips/74k.md
===================================================================
--- gcc/config/mips/74k.md (revision 126276)
+++ gcc/config/mips/74k.md (working copy)
@@ -35,13 +35,18 @@
;; Producers
;; --------------------------------------------------------------
-;; Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
-;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
-;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
-;; xor, xori
+;; ALU: Logicals/Arithmetics
+;; - Logicals, move (addu/addiu with rt = 0), Set less than,
+;; sign extend - 1 cycle
+(define_insn_reservation "r74k_int_logical" 1
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
+ (eq_attr "type" "logical,move,signext,slt"))
+ "r74k_alu")
+
+;; - Arithmetics - 2 cycles
(define_insn_reservation "r74k_int_arith" 2
(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
- (eq_attr "type" "arith,const,shift,slt,clz"))
+ (eq_attr "type" "arith,const,shift,clz"))
"r74k_alu")
(define_insn_reservation "r74k_int_nop" 0
@@ -137,6 +142,12 @@
(define_bypass 4 "r74k_int_load" "r74k_int_load")
(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
+;; logical/move/slt/signext->next use : 1 cycles (Default)
+;; logical/move/slt/signext->load base: 2 cycles
+;; logical/move/slt/signext->store base: 2 cycles
+(define_bypass 2 "r74k_int_logical" "r74k_int_load")
+(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
+
;; arith->next use : 2 cycles (Default)
;; arith->load base: 3 cycles
;; arith->store base: 3 cycles
Index: gcc/config/mips/sr71k.md
===================================================================
--- gcc/config/mips/sr71k.md (revision 126276)
+++ gcc/config/mips/sr71k.md (working copy)
@@ -188,7 +188,7 @@
(define_insn_reservation "ir_sr70_arith" 1
(and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "arith,shift,slt,clz,const,trap"))
+ (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,trap"))
"ri_insns")
;; emulate repeat (dispatch stall) by spending extra cycle(s) in
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: MIPS 74k scheduler adjustments
2007-07-04 13:28 MIPS 74k scheduler adjustments Joseph S. Myers
@ 2007-07-04 16:26 ` Richard Sandiford
2007-07-07 7:35 ` Fu, Chao-Ying
1 sibling, 0 replies; 7+ messages in thread
From: Richard Sandiford @ 2007-07-04 16:26 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: gcc-patches, David Ung
OK, but...
"Joseph S. Myers" <joseph@codesourcery.com> writes:
> +;; move integer register move (ADD (rt=0) and ADDU (rt=0))
...change this to "{,D}ADD{,U} with rt = 0", as we're using it for
64-bit moves too.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: MIPS 74k scheduler adjustments
2007-07-04 13:28 MIPS 74k scheduler adjustments Joseph S. Myers
2007-07-04 16:26 ` Richard Sandiford
@ 2007-07-07 7:35 ` Fu, Chao-Ying
2007-07-08 15:19 ` Adam Nemet
2007-07-18 11:40 ` Richard Sandiford
1 sibling, 2 replies; 7+ messages in thread
From: Fu, Chao-Ying @ 2007-07-07 7:35 UTC (permalink / raw)
To: Joseph S. Myers, gcc-patches; +Cc: Ung, David, Stephens, Nigel
Joseph S. Myers wrote:
>
> This patch adjusts the MIPS 74k scheduler to reflect that certain
> arithmetic instructions take only 1 cycle. This in turn
> requires various
> instructions to be marked as "logical", "signext" or "move"
> instead of
> "arith".
>
> Tested with no regressions with cross to mips-linux-gnu. OK
> to commit?
>
> 2007-07-04 David Ung <davidu@mips.com>
> Joseph Myers <joseph@codesourcery.com>
>
> gcc/
> * config/mips/mips.md (type): Add logical, signext and move.
> (one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
> *ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
> *nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
> combinations", *zero_extend<SHORT:mode><GPR:mode>2,
> *zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
> *extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
> *movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
> *movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
> *movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
> *movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
> movv2sf_hardfloat_64bit): Use the new types.
> (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
> *movdf_softfloat, *movdf_mips16): Use "multi".
> (extendqihi2): Replace with a define_expand.
> (*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
> Based on extend<SHORT:mode><GPR:mode>2 patterns.
>
> -;; This pattern generates the same code as extendqisi2; split it into
> -;; that form after reload.
> -(define_insn_and_split "extendqihi2"
> +(define_expand "extendqihi2"
> + [(set (match_operand:HI 0 "register_operand")
> + (sign_extend:HI (match_operand:QI 1
> "nonimmediate_operand")))]
> + "")
> +
> +(define_insn "*extendqihi2_mips16e"
> [(set (match_operand:HI 0 "register_operand" "=d,d")
> - (sign_extend:HI (match_operand:QI 1
> "nonimmediate_operand" "d,m")))]
> - ""
> - "#"
> - "reload_completed"
> - [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
> - { operands[0] = gen_lowpart (SImode, operands[0]); }
> - [(set_attr "type" "arith,load")
> + (sign_extend:HI (match_operand:QI 1
> "nonimmediate_operand" "0,m")))]
> + "GENERATE_MIPS16E"
> + "@
> + seb\t%0
> + lb\t%0,%1"
> + [(set_attr "type" "signext,load")
> + (set_attr "mode" "SI")])
> +
> +(define_insn_and_split "*extendqihi2"
> + [(set (match_operand:HI 0 "register_operand" "=d,d")
> + (sign_extend:HI
> + (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
> + "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
> + "@
> + #
> + lb\t%0,%1"
> + "&& reload_completed && REG_P (operands[1])"
> + [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
> + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
> +{
> + operands[1] = gen_lowpart (SImode, operands[1]);
> + operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
> + - GET_MODE_BITSIZE (QImode));
> +}
> + [(set_attr "type" "multi,load")
> (set_attr "mode" "SI")
> (set_attr "length" "8,*")])
>
> +(define_insn "*extendqihi2_seb"
> + [(set (match_operand:HI 0 "register_operand" "=d,d")
> + (sign_extend:HI
> + (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
> + "ISA_HAS_SEB_SEH"
> + "@
> + seb\t%0,%1
> + lb\t%0,%1"
> + [(set_attr "type" "signext,load")
> + (set_attr "mode" "SI")])
> +
Hi,
I got one test that failed on the target of mipsisa32r2-elf
(compiled with -mips32.) The issue may be from "*extendqihi2"
where operands[0] is not converted to SImode.
The test was ok with "gcc version 4.3.0 20070625 (experimental)",
but not with the current mainline. Thanks!
Ex:
# cat bug129.c
short test(signed char a, signed char b)
{
short c = (short) a;
short d = (short) b;
short e = c * d;
return e;
}
# mipsisa32r2-elf-gcc -O -mips32 -S bug129.c
bug129.c: In function â?~testâ?T:
bug129.c:7: error: unrecognizable insn:
(insn 28 6 29 2 bug129.c:2 (set (reg:HI 2 $2 [orig:199 b ] [199])
(ashift:SI (reg:SI 5 $5 [ b+-7 ])
(const_int 24 [0x18]))) -1 (nil))
bug129.c:7: internal compiler error: in extract_insn, at recog.c:1991
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.
Regards,
Chao-ying
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: MIPS 74k scheduler adjustments
2007-07-07 7:35 ` Fu, Chao-Ying
@ 2007-07-08 15:19 ` Adam Nemet
2007-08-11 9:02 ` Joseph S. Myers
2007-07-18 11:40 ` Richard Sandiford
1 sibling, 1 reply; 7+ messages in thread
From: Adam Nemet @ 2007-07-08 15:19 UTC (permalink / raw)
To: Fu, Chao-Ying; +Cc: Joseph S. Myers, gcc-patches, Ung, David, Stephens, Nigel
"Fu, Chao-Ying" <fu@mips.com> writes:
> Joseph S. Myers wrote:
>> 2007-07-04 David Ung <davidu@mips.com>
>> Joseph Myers <joseph@codesourcery.com>
>>
>> gcc/
>> * config/mips/mips.md (type): Add logical, signext and move.
>> (one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
>> *ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
>> *nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
>> combinations", *zero_extend<SHORT:mode><GPR:mode>2,
Joseph,
It just occured to me that I haven't seen any "Combiner patterns to
optimize truncate/zero_extend combinations" in the original patch. Is
this any incorrect entry in the changelog?
Adam
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: MIPS 74k scheduler adjustments
2007-07-07 7:35 ` Fu, Chao-Ying
2007-07-08 15:19 ` Adam Nemet
@ 2007-07-18 11:40 ` Richard Sandiford
1 sibling, 0 replies; 7+ messages in thread
From: Richard Sandiford @ 2007-07-18 11:40 UTC (permalink / raw)
To: Fu, Chao-Ying; +Cc: Joseph S. Myers, gcc-patches, Ung, David, Stephens, Nigel
"Fu, Chao-Ying" <fu@mips.com> writes:
> Joseph S. Myers wrote:
>> This patch adjusts the MIPS 74k scheduler to reflect that certain
>> arithmetic instructions take only 1 cycle. This in turn
>> requires various
>> instructions to be marked as "logical", "signext" or "move"
>> instead of
>> "arith".
>>
>> Tested with no regressions with cross to mips-linux-gnu. OK
>> to commit?
>>
>> 2007-07-04 David Ung <davidu@mips.com>
>> Joseph Myers <joseph@codesourcery.com>
>>
>> gcc/
>> * config/mips/mips.md (type): Add logical, signext and move.
>> (one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
>> *ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
>> *nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
>> combinations", *zero_extend<SHORT:mode><GPR:mode>2,
>> *zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
>> *extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
>> *movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
>> *movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
>> *movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
>> *movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
>> movv2sf_hardfloat_64bit): Use the new types.
>> (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
>> *movdf_softfloat, *movdf_mips16): Use "multi".
>> (extendqihi2): Replace with a define_expand.
>> (*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
>> Based on extend<SHORT:mode><GPR:mode>2 patterns.
>>[...]
>
> I got one test that failed on the target of mipsisa32r2-elf
> (compiled with -mips32.) The issue may be from "*extendqihi2"
> where operands[0] is not converted to SImode.
> The test was ok with "gcc version 4.3.0 20070625 (experimental)",
> but not with the current mainline. Thanks!
>
> Ex:
> # cat bug129.c
> short test(signed char a, signed char b)
> {
> short c = (short) a;
> short d = (short) b;
> short e = c * d;
> return e;
> }
>
> # mipsisa32r2-elf-gcc -O -mips32 -S bug129.c
> bug129.c: In function â?~testâ?T:
> bug129.c:7: error: unrecognizable insn:
> (insn 28 6 29 2 bug129.c:2 (set (reg:HI 2 $2 [orig:199 b ] [199])
> (ashift:SI (reg:SI 5 $5 [ b+-7 ])
> (const_int 24 [0x18]))) -1 (nil))
> bug129.c:7: internal compiler error: in extract_insn, at recog.c:1991
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <URL:http://gcc.gnu.org/bugs.html> for instructions.
Joseph's away at the moment, so I've installed the fix below after
regression-testing on mipsisa64-elf.
Richard
gcc/
* config/mips/mips.md (*extendqihi2): Convert the destination
to SImode.
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md (revision 176278)
+++ gcc/config/mips/mips.md (working copy)
@@ -2639,6 +2639,7 @@ (define_insn_and_split "*extendqihi2"
[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
{
+ operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
- GET_MODE_BITSIZE (QImode));
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: MIPS 74k scheduler adjustments
2007-07-08 15:19 ` Adam Nemet
@ 2007-08-11 9:02 ` Joseph S. Myers
2007-08-11 22:58 ` Adam Nemet
0 siblings, 1 reply; 7+ messages in thread
From: Joseph S. Myers @ 2007-08-11 9:02 UTC (permalink / raw)
To: Adam Nemet; +Cc: Fu, Chao-Ying, gcc-patches, Ung, David, Stephens, Nigel
On Sun, 8 Jul 2007, Adam Nemet wrote:
> "Fu, Chao-Ying" <fu@mips.com> writes:
> > Joseph S. Myers wrote:
> >> 2007-07-04 David Ung <davidu@mips.com>
> >> Joseph Myers <joseph@codesourcery.com>
> >>
> >> gcc/
> >> * config/mips/mips.md (type): Add logical, signext and move.
> >> (one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
> >> *ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
> >> *nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
> >> combinations", *zero_extend<SHORT:mode><GPR:mode>2,
>
> Joseph,
>
> It just occured to me that I haven't seen any "Combiner patterns to
> optimize truncate/zero_extend combinations" in the original patch. Is
> this any incorrect entry in the changelog?
It refers to the section of mips.md headed by the comment
;; Combiner patterns to optimize truncate/zero_extend combinations.
which contains unnamed define_insns whose "type"s were changed to
"logical". That comment itself would have been outside the range covered
by the diff context.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: MIPS 74k scheduler adjustments
2007-08-11 9:02 ` Joseph S. Myers
@ 2007-08-11 22:58 ` Adam Nemet
0 siblings, 0 replies; 7+ messages in thread
From: Adam Nemet @ 2007-08-11 22:58 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: Fu, Chao-Ying, gcc-patches, Ung, David, Stephens, Nigel
Joseph S. Myers writes:
> It refers to the section of mips.md headed by the comment
>
> ;; Combiner patterns to optimize truncate/zero_extend combinations.
I found them now, thanks.
Adam
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2007-08-11 22:58 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2007-07-04 13:28 MIPS 74k scheduler adjustments Joseph S. Myers
2007-07-04 16:26 ` Richard Sandiford
2007-07-07 7:35 ` Fu, Chao-Ying
2007-07-08 15:19 ` Adam Nemet
2007-08-11 9:02 ` Joseph S. Myers
2007-08-11 22:58 ` Adam Nemet
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