* [PATCH, MIPS] Make more use of macros in scc patterns
@ 2008-04-03 0:24 Adam Nemet
2008-04-03 19:02 ` Richard Sandiford
0 siblings, 1 reply; 2+ messages in thread
From: Adam Nemet @ 2008-04-03 0:24 UTC (permalink / raw)
To: gcc-patches
I am planning to add widening versions of the scc patterns but in preparation
to that this patch merges the signed and unsigned version of each scc pattern
by using new code iterators.
The new test passes and there is no code change on gcc.c-torture/execute.
Tested with mipsisa64-elf.
Sorry about the context diff but I think it is more readable in this case.
OK?
Adam
* config/mips/mips.md (any_gt, any_ge, any_lt, any_le): New code
iterators.
(u): Add attribute values for gt, gtu, ge, geu, lt, ltu, le and
leu.
(sgt<u>): Merge sgt and sgtu into new expander.
(sgt, sgtu): Remove expanders.
(*sgt<u>_<mode>): Merge *sgt_<mode> and *sgtu_<mode> into new
pattern.
(*sgt_<mode>, *sgtu_<mode>): Remove patterns.
(*sgt<u>_<mode>_mips16): Merge *sgt_<mode>_mips16 and
*sgtu_<mode>_mips16 into new pattern.
(*sgt_<mode>_mips16, *sgtu_<mode>_mips16): Remove patterns.
(sge<u>): Merge sge and sgeu into new expander.
(sge, sgeu): Remove expanders.
(*sge<u>_<mode>): Merge *sge_<mode> and second *sge_<mode> into
new pattern.
(*sge_<mode>, second *sge_<mode>): Remove patterns.
(slt<u>): Merge slt and sltu into new expander.
(slt, sltu): Remove expanders.
(*slt<u>_<mode>): Merge *slt_<mode> and *sltu_<mode> into new
pattern.
(*slt_<mode>, *sltu_<mode>): Remove patterns.
(*slt<u>_<mode>_mips16): Merge *slt_<mode>_mips16 and
*sltu_<mode>_mips16 into new pattern.
(*slt_<mode>_mips16, *sltu_<mode>_mips16): Remove patterns.
(sle<u>): Merge sle and sleu into new expander.
(sle, sleu): Remove expanders.
(*sle<u>_<mode>): Merge *sle_<mode> and *sleu_<mode> into new
pattern.
(*sle_<mode>, *sleu_<mode>): Remove patterns.
(*sle<u>_<mode>_mips16): Merge *sle_<mode>_mips16 and
*sleu_<mode>_mips16 into new pattern.
(*sle_<mode>_mips16, *sleu_<mode>_mips16): Remove patterns.
testsuite/
* gcc.target/mips/scc-1.c: New test.
Index: config/mips/mips.md
===================================================================
*** config/mips/mips.md (revision 133332)
--- config/mips/mips.md (working copy)
*************** (define_code_iterator fcond [unordered u
*** 610,618 ****
;; by swapping the operands.
(define_code_iterator swapped_fcond [ge gt unge ungt])
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
! (define_code_attr u [(sign_extend "") (zero_extend "u")])
;; <su> is like <u>, but the signed form expands to "s" rather than "".
(define_code_attr su [(sign_extend "s") (zero_extend "u")])
--- 610,629 ----
;; by swapping the operands.
(define_code_iterator swapped_fcond [ge gt unge ungt])
+ ;; These code iterators allow the signed and unsigned scc operations to use
+ ;; the same template.
+ (define_code_iterator any_gt [gt gtu])
+ (define_code_iterator any_ge [ge geu])
+ (define_code_iterator any_lt [lt ltu])
+ (define_code_iterator any_le [le leu])
+
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
! (define_code_attr u [(sign_extend "") (zero_extend "u")
! (gt "") (gtu "u")
! (ge "") (geu "u")
! (lt "") (ltu "u")
! (le "") (leu "u")])
;; <su> is like <u>, but the signed form expands to "s" rather than "".
(define_code_attr su [(sign_extend "s") (zero_extend "u")])
*************** (define_insn "*sne_<mode>"
*** 5098,5271 ****
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "sgt"
! [(set (match_operand:SI 0 "register_operand")
! (gt:SI (match_dup 1)
! (match_dup 2)))]
! ""
! { if (mips_expand_scc (GT, operands[0])) DONE; else FAIL; })
!
! (define_insn "*sgt_<mode>"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (gt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
! "!TARGET_MIPS16"
! "slt\t%0,%z2,%1"
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")])
!
! (define_insn "*sgt_<mode>_mips16"
! [(set (match_operand:GPR 0 "register_operand" "=t")
! (gt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "register_operand" "d")))]
! "TARGET_MIPS16"
! "slt\t%2,%1"
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")])
!
! (define_expand "sge"
! [(set (match_operand:SI 0 "register_operand")
! (ge:SI (match_dup 1)
! (match_dup 2)))]
! ""
! { if (mips_expand_scc (GE, operands[0])) DONE; else FAIL; })
!
! (define_insn "*sge_<mode>"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (ge:GPR (match_operand:GPR 1 "register_operand" "d")
! (const_int 1)))]
! "!TARGET_MIPS16"
! "slt\t%0,%.,%1"
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")])
!
! (define_expand "slt"
! [(set (match_operand:SI 0 "register_operand")
! (lt:SI (match_dup 1)
! (match_dup 2)))]
! ""
! { if (mips_expand_scc (LT, operands[0])) DONE; else FAIL; })
!
! (define_insn "*slt_<mode>"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (lt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "arith_operand" "dI")))]
! "!TARGET_MIPS16"
! "slt\t%0,%1,%2"
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")])
!
! (define_insn "*slt_<mode>_mips16"
! [(set (match_operand:GPR 0 "register_operand" "=t,t")
! (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
! (match_operand:GPR 2 "arith_operand" "d,I")))]
! "TARGET_MIPS16"
! "slt\t%1,%2"
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")
! (set_attr_alternative "length"
! [(const_int 4)
! (if_then_else (match_operand 2 "m16_uimm8_1")
! (const_int 4)
! (const_int 8))])])
!
! (define_expand "sle"
! [(set (match_operand:SI 0 "register_operand")
! (le:SI (match_dup 1)
! (match_dup 2)))]
! ""
! { if (mips_expand_scc (LE, operands[0])) DONE; else FAIL; })
!
! (define_insn "*sle_<mode>"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (le:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sle_operand" "")))]
! "!TARGET_MIPS16"
! {
! operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "slt\t%0,%1,%2";
! }
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")])
!
! (define_insn "*sle_<mode>_mips16"
! [(set (match_operand:GPR 0 "register_operand" "=t")
! (le:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sle_operand" "")))]
! "TARGET_MIPS16"
! {
! operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "slt\t%1,%2";
! }
! [(set_attr "type" "slt")
! (set_attr "mode" "<MODE>")
! (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
! (const_int 4)
! (const_int 8)))])
!
! (define_expand "sgtu"
[(set (match_operand:SI 0 "register_operand")
! (gtu:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (GTU, operands[0])) DONE; else FAIL; })
! (define_insn "*sgtu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16"
! "sltu\t%0,%z2,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*sgtu_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t")
! (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
! "sltu\t%2,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "sgeu"
[(set (match_operand:SI 0 "register_operand")
! (geu:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (GEU, operands[0])) DONE; else FAIL; })
! (define_insn "*sge_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (geu:GPR (match_operand:GPR 1 "register_operand" "d")
! (const_int 1)))]
"!TARGET_MIPS16"
! "sltu\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "sltu"
[(set (match_operand:SI 0 "register_operand")
! (ltu:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (LTU, operands[0])) DONE; else FAIL; })
! (define_insn "*sltu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
! "sltu\t%0,%1,%2"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*sltu_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t,t")
! (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
! (match_operand:GPR 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
! "sltu\t%1,%2"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
--- 5109,5177 ----
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "sgt<u>"
[(set (match_operand:SI 0 "register_operand")
! (any_gt:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
! (define_insn "*sgt<u>_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (any_gt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16"
! "slt<u>\t%0,%z2,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*sgt<u>_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t")
! (any_gt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
! "slt<u>\t%2,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "sge<u>"
[(set (match_operand:SI 0 "register_operand")
! (any_ge:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
! (define_insn "*sge<u>_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (any_ge:GPR (match_operand:GPR 1 "register_operand" "d")
! (const_int 1)))]
"!TARGET_MIPS16"
! "slt<u>\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_expand "slt<u>"
[(set (match_operand:SI 0 "register_operand")
! (any_lt:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
! (define_insn "*slt<u>_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (any_lt:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
! "slt<u>\t%0,%1,%2"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*slt<u>_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t,t")
! (any_lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
! (match_operand:GPR 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
! "slt<u>\t%1,%2"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
*************** (define_insn "*sltu_<mode>_mips16"
*** 5274,5306 ****
(const_int 4)
(const_int 8))])])
! (define_expand "sleu"
[(set (match_operand:SI 0 "register_operand")
! (leu:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (LEU, operands[0])) DONE; else FAIL; })
! (define_insn "*sleu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (leu:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sleu_operand" "")))]
"!TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "sltu\t%0,%1,%2";
}
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*sleu_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t")
! (leu:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sleu_operand" "")))]
"TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "sltu\t%1,%2";
}
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")
--- 5180,5212 ----
(const_int 4)
(const_int 8))])])
! (define_expand "sle<u>"
[(set (match_operand:SI 0 "register_operand")
! (any_le:SI (match_dup 1)
! (match_dup 2)))]
""
! { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
! (define_insn "*sle<u>_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (any_le:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sle_operand" "")))]
"!TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "slt<u>\t%0,%1,%2";
}
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
! (define_insn "*sle<u>_<mode>_mips16"
[(set (match_operand:GPR 0 "register_operand" "=t")
! (any_le:GPR (match_operand:GPR 1 "register_operand" "d")
! (match_operand:GPR 2 "sle_operand" "")))]
"TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
! return "slt<u>\t%1,%2";
}
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")
Index: testsuite/gcc.target/mips/scc-1.c
===================================================================
*** testsuite/gcc.target/mips/scc-1.c (revision 0)
--- testsuite/gcc.target/mips/scc-1.c (revision 0)
***************
*** 0 ****
--- 1,35 ----
+ /* { dg-do compile } */
+ /* { dg-mips-options "-O -mips32" } */
+
+ /* { dg-final { scan-assembler-times {slt \$2,\$5,\$4} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$2,\$5,\$4} 1 } } */
+ /* { dg-final { scan-assembler-times {slt \$5,\$4} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$5,\$4} 1 } } */
+
+ /* { dg-final { scan-assembler-times {slt \$2,\$0,\$4} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$2,\$0,\$4} 1 } } */
+
+ /* { dg-final { scan-assembler-times {slt \$2,\$4,\$5} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$2,\$4,\$5} 1 } } */
+ /* { dg-final { scan-assembler-times {slt \$4,\$5} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$4,\$5} 1 } } */
+
+ /* { dg-final { scan-assembler-times {slt \$2,\$4,23} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$2,\$4,23} 1 } } */
+ /* { dg-final { scan-assembler-times {slt \$4,23} 1 } } */
+ /* { dg-final { scan-assembler-times {sltu \$4,23} 1 } } */
+
+ #define TEST(N, LHS, REL, RHS) \
+ NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+ NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } \
+ MIPS16 int s##N##_16 (int a, int b) { return LHS REL RHS; } \
+ MIPS16 int u##N##_16 (unsigned a, unsigned b) { return LHS REL RHS; }
+
+ #define TEST_NO16(N, LHS, REL, RHS) \
+ NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+ NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; }
+
+ TEST (1, a, >, b);
+ TEST_NO16 (2, a, >=, 1);
+ TEST (3, a, <, b);
+ TEST (4, a, <=, 22);
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH, MIPS] Make more use of macros in scc patterns
2008-04-03 0:24 [PATCH, MIPS] Make more use of macros in scc patterns Adam Nemet
@ 2008-04-03 19:02 ` Richard Sandiford
0 siblings, 0 replies; 2+ messages in thread
From: Richard Sandiford @ 2008-04-03 19:02 UTC (permalink / raw)
To: Adam Nemet; +Cc: gcc-patches
Adam Nemet <anemet@caviumnetworks.com> writes:
> I am planning to add widening versions of the scc patterns but in preparation
> to that this patch merges the signed and unsigned version of each scc pattern
> by using new code iterators.
Nice patch, thanks. Really should have noticed that we could
do that before...
> * config/mips/mips.md (any_gt, any_ge, any_lt, any_le): New code
> iterators.
> (u): Add attribute values for gt, gtu, ge, geu, lt, ltu, le and
> leu.
> (sgt<u>): Merge sgt and sgtu into new expander.
> (sgt, sgtu): Remove expanders.
> (*sgt<u>_<mode>): Merge *sgt_<mode> and *sgtu_<mode> into new
> pattern.
> (*sgt_<mode>, *sgtu_<mode>): Remove patterns.
> (*sgt<u>_<mode>_mips16): Merge *sgt_<mode>_mips16 and
> *sgtu_<mode>_mips16 into new pattern.
> (*sgt_<mode>_mips16, *sgtu_<mode>_mips16): Remove patterns.
> (sge<u>): Merge sge and sgeu into new expander.
> (sge, sgeu): Remove expanders.
> (*sge<u>_<mode>): Merge *sge_<mode> and second *sge_<mode> into
> new pattern.
> (*sge_<mode>, second *sge_<mode>): Remove patterns.
(doh!)
> (slt<u>): Merge slt and sltu into new expander.
> (slt, sltu): Remove expanders.
> (*slt<u>_<mode>): Merge *slt_<mode> and *sltu_<mode> into new
> pattern.
> (*slt_<mode>, *sltu_<mode>): Remove patterns.
> (*slt<u>_<mode>_mips16): Merge *slt_<mode>_mips16 and
> *sltu_<mode>_mips16 into new pattern.
> (*slt_<mode>_mips16, *sltu_<mode>_mips16): Remove patterns.
> (sle<u>): Merge sle and sleu into new expander.
> (sle, sleu): Remove expanders.
> (*sle<u>_<mode>): Merge *sle_<mode> and *sleu_<mode> into new
> pattern.
> (*sle_<mode>, *sleu_<mode>): Remove patterns.
> (*sle<u>_<mode>_mips16): Merge *sle_<mode>_mips16 and
> *sleu_<mode>_mips16 into new pattern.
> (*sle_<mode>_mips16, *sleu_<mode>_mips16): Remove patterns.
>
> testsuite/
>
> * gcc.target/mips/scc-1.c: New test.
OK, thanks.
Richard
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2008-04-03 19:02 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2008-04-03 0:24 [PATCH, MIPS] Make more use of macros in scc patterns Adam Nemet
2008-04-03 19:02 ` Richard Sandiford
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).