From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 63306 invoked by alias); 21 Apr 2016 11:40:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 63173 invoked by uid 89); 21 Apr 2016 11:40:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=Hx-languages-length:2166 X-HELO: mail-wm0-f50.google.com Received: from mail-wm0-f50.google.com (HELO mail-wm0-f50.google.com) (74.125.82.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 21 Apr 2016 11:39:54 +0000 Received: by mail-wm0-f50.google.com with SMTP id v188so240841006wme.1 for ; Thu, 21 Apr 2016 04:39:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=YQfYeZDnShXnvRiop9DC0ZEN2wxlrIzHJG7VRoyl4MY=; b=maNXFAowLlNPXPFzCL2AE25nUnOWscmNyvBEDY/ZMGQTshOrj6dMH/xT35TLdyG5rz AKvE/EAH7Bz3S5AiBy2BPMJUiIlNxZ3o6QfkTeMvRYc2XNCknqI/kbneAPhs69oNeJF1 LUZMkDdUroQmC6LZaTxxu7sC72PuYPWPzKJ/Lh/n5Lg2dIGtOos5xKsyCHGVXSPfZxf0 oy8MLZ8NhqE6ASPLUATqnj9t5Nq04ptKTNoSFcjxHfPWeq8evBG5iT0ZAbAakMY506Tw Xwyg9mmUMItje8AtXHgpY5Up61fmnvZzA4TQJc3dlavYDEE6qnDJrlS1a1S0o1X9REMa Qjqg== X-Gm-Message-State: AOPr4FWniUqjKzERzFG2Fl++rRL1oJx4cHRJo2/DfbE5DGYRTVP98Hs95w3Lrkh/P7pzBA== X-Received: by 10.28.91.199 with SMTP id p190mr34581896wmb.47.1461238791338; Thu, 21 Apr 2016 04:39:51 -0700 (PDT) Received: from localhost (host86-155-190-186.range86-155.btcentralplus.com. [86.155.190.186]) by smtp.gmail.com with ESMTPSA id g78sm14528025wme.21.2016.04.21.04.39.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 04:39:50 -0700 (PDT) From: Andrew Burgess To: gcc-patches@gcc.gnu.org, gnu@amylaar.uk Cc: noamca@mellanox.com, Claudiu.Zissulescu@synopsys.com, Andrew Burgess Subject: [PATCHv2 6/7] gcc/arc: Mask integer 'L' operands to 32-bit Date: Thu, 21 Apr 2016 11:40:00 -0000 Message-Id: <18b0f70e52c5132970c07d7b469909bbe57405f1.1461238348.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes X-SW-Source: 2016-04/txt/msg01149.txt.bz2 When formatting 'L' operands (least significant word) only print 32-bits, don't sign extend to 64-bits. This commit could really be applied directly to the current GCC trunk, however, the only test I have for this issue right now relies on the nps400 bitops support. gcc/ChangeLog: * config/arc/arc.c (arc_print_operand): Print integer 'L' operands as 32-bits. gcc/testsuite/ChangeLog: * gcc.target/arc/movh_cl-1.c: New file. --- gcc/ChangeLog.NPS400 | 6 ++++++ gcc/config/arc/arc.c | 10 ++++------ gcc/testsuite/ChangeLog.NPS400 | 4 ++++ gcc/testsuite/gcc.target/arc/movh_cl-1.c | 27 +++++++++++++++++++++++++++ 4 files changed, 41 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/movh_cl-1.c diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 72a0825..b7b8516 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -3181,18 +3181,16 @@ arc_print_operand (FILE *file, rtx x, int code) else if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) { - rtx first, second; + rtx first, second, word; split_double (x, &first, &second); if((WORDS_BIG_ENDIAN) == 0) - fprintf (file, "0x%08" PRIx64, - code == 'L' ? INTVAL (first) : INTVAL (second)); + word = (code == 'L' ? first : second); else - fprintf (file, "0x%08" PRIx64, - code == 'L' ? INTVAL (second) : INTVAL (first)); - + word = (code == 'L' ? second : first); + fprintf (file, "0x%08" PRIx32, ((uint32_t) INTVAL (word))); } else output_operand_lossage ("invalid operand to %%H/%%L code"); diff --git a/gcc/testsuite/gcc.target/arc/movh_cl-1.c b/gcc/testsuite/gcc.target/arc/movh_cl-1.c new file mode 100644 index 0000000..220cd9d --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/movh_cl-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */ + +struct thing +{ + union + { + int raw; + struct + { + unsigned a : 1; + unsigned b : 1; + }; + }; +}; + +extern void func (int); + +void +blah () +{ + struct thing xx; + xx.a = xx.b = 1; + func (xx.raw); +} + +/* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */ -- 2.6.4